Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071844
I. Ghorbel, F. Haddad, W. Rahajandraibe
Optimization of CMOS circuits is essential to reduce power consumption and improve phase noise performance. A novel method to optimize voltage-controlled oscillator VCO is proposed using a current reuse technique. In this paper, three VCO topology for 2.4 GHz application are designed in 0.13μm CMOS process and are simulated using Cadence Spectre. The improvement of the VCO topology is described and analyzed. The traditional current reuse with a tuning range of 14.8% is presented in the first topology. It consumes about 0.267mW from 1V supply voltage. For the second topology, NMOS cross-coupled pair is added to speed up the oscillation and stability .The tuning range and power consumption are 28% and 0.366 mW respectively. It has a high performance of phase noise @ 1MHz with -120 dBc/Hz. The current-reuse oscillator with source degeneration resistance is presented in the third topology. The total power consumption is 0.234mW under 1V supply voltage and the frequency tuning range is 21.8%.
{"title":"Optimization of voltage-controlled oscillator VCO using current-reuse technique","authors":"I. Ghorbel, F. Haddad, W. Rahajandraibe","doi":"10.1109/ICM.2014.7071844","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071844","url":null,"abstract":"Optimization of CMOS circuits is essential to reduce power consumption and improve phase noise performance. A novel method to optimize voltage-controlled oscillator VCO is proposed using a current reuse technique. In this paper, three VCO topology for 2.4 GHz application are designed in 0.13μm CMOS process and are simulated using Cadence Spectre. The improvement of the VCO topology is described and analyzed. The traditional current reuse with a tuning range of 14.8% is presented in the first topology. It consumes about 0.267mW from 1V supply voltage. For the second topology, NMOS cross-coupled pair is added to speed up the oscillation and stability .The tuning range and power consumption are 28% and 0.366 mW respectively. It has a high performance of phase noise @ 1MHz with -120 dBc/Hz. The current-reuse oscillator with source degeneration resistance is presented in the third topology. The total power consumption is 0.234mW under 1V supply voltage and the frequency tuning range is 21.8%.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127067608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071813
Ahmed T. Elthakeb, H. A. Elhamid, H. Mostafa, Y. Ismail
FinFET devices are the most promising solutions for further technology scaling in the long term projections of the ITRS. The performance of extremely scaled FinFET-based 256-bit (6T) SRAM is evaluated with technology scaling for channel lengths of 20nm down to 7nm showing the scaling trends of basic performance metrics. In addition, the impact of threshold voltage variations on the delay, power, and stability is reported considering die-to-die variations. Significant performance degradation is found starting from the 10nm channel length and continues down to 7nm.
{"title":"Performance evaluation of finFET based SRAM under statistical VT variability","authors":"Ahmed T. Elthakeb, H. A. Elhamid, H. Mostafa, Y. Ismail","doi":"10.1109/ICM.2014.7071813","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071813","url":null,"abstract":"FinFET devices are the most promising solutions for further technology scaling in the long term projections of the ITRS. The performance of extremely scaled FinFET-based 256-bit (6T) SRAM is evaluated with technology scaling for channel lengths of 20nm down to 7nm showing the scaling trends of basic performance metrics. In addition, the impact of threshold voltage variations on the delay, power, and stability is reported considering die-to-die variations. Significant performance degradation is found starting from the 10nm channel length and continues down to 7nm.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130865615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071846
N. Ramzan, Zeeshan Pervez, A. Amira
This paper presents a performance evaluation of the three newest video coding standards Advanced Video Coding (H.264/MPEG-AVC), High-Efficiency Video Coding (H.265/MPEG-HEVC) and VP9 on the basis of subjective and objective quality evaluations. The main goal of the encoder is to compress video contents. In this paper, the compression of High Definition (HD) and Ultra High Definition (UHD) video contents are studied by above mentioned codecs for different scenarios, such as broadcasting and streaming. An extensive range of bit-rates from low to high bit-rates were selected and encoded the video sequences. of each encoder configuration corresponds to low quality up to excellent quality were compared to original and uncompressed video. Four video sequences were encoded by using same encoding configurations for all the examined video encoders. According to the experimental analysis, HEVC showed a clear supremacy of HEVC encoding algorithm as compared to other alternatives such as AVC and VP9. In addition, VP9 shows competitive results as compared to AVC.
{"title":"Quality of experience evaluation of H.265/MPEG-HEVC and VP9 comparison efficiency","authors":"N. Ramzan, Zeeshan Pervez, A. Amira","doi":"10.1109/ICM.2014.7071846","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071846","url":null,"abstract":"This paper presents a performance evaluation of the three newest video coding standards Advanced Video Coding (H.264/MPEG-AVC), High-Efficiency Video Coding (H.265/MPEG-HEVC) and VP9 on the basis of subjective and objective quality evaluations. The main goal of the encoder is to compress video contents. In this paper, the compression of High Definition (HD) and Ultra High Definition (UHD) video contents are studied by above mentioned codecs for different scenarios, such as broadcasting and streaming. An extensive range of bit-rates from low to high bit-rates were selected and encoded the video sequences. of each encoder configuration corresponds to low quality up to excellent quality were compared to original and uncompressed video. Four video sequences were encoded by using same encoding configurations for all the examined video encoders. According to the experimental analysis, HEVC showed a clear supremacy of HEVC encoding algorithm as compared to other alternatives such as AVC and VP9. In addition, VP9 shows competitive results as compared to AVC.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129611842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071836
A. A. El-Slehdar, A. Radwan
This paper introduces a step forward towards memristor-MOS hybrid circuit to achieve any combinational function. The proposed design is based on reducing the area by replacing the complete pull-down network with just one memristor and one comparator. The concept is then verified using an example of a simple function. Also, a proposed architecture for memristor based redundant multiplier circuit is introduced and verified using the SPICE simulation. Therefore, any redundant functions can be implemented using the same concept.
{"title":"Memristor-MOS hybrid circuit redundant multiplier","authors":"A. A. El-Slehdar, A. Radwan","doi":"10.1109/ICM.2014.7071836","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071836","url":null,"abstract":"This paper introduces a step forward towards memristor-MOS hybrid circuit to achieve any combinational function. The proposed design is based on reducing the area by replacing the complete pull-down network with just one memristor and one comparator. The concept is then verified using an example of a simple function. Also, a proposed architecture for memristor based redundant multiplier circuit is introduced and verified using the SPICE simulation. Therefore, any redundant functions can be implemented using the same concept.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123373272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071810
Andrianiaina Ravelomanantsoa, H. Rabah, A. Rouane
In a wireless body sensor network (WBSN), the available energy and bandwidth are limited. Therefore, compressing the electromyogram (EMG) signal is of great importance since it is generally sensed at a relatively high frequency of the order of kHz. In this paper, we use the compressed sensing (CS) technique to compress and recover the EMG signal. The main advantage with CS is that its compression process requires less computational complexity. We propose a deterministic measurement matrix that greatly facilitates the implementation of the encoder device. The simulation and experiment results showed that the proposed approach can compress and recover the EMG signal without perceptible loss if the compression ratio was greater than or equal to 0.25, which saved up to 75 % of both the available bandwidth and power consumption of the transceiver. A comparison with the current stat-of-the-art of EMG compression shows that we obtained a better performance. Furthermore, the proposed encoder has the lowest computational complexity.
{"title":"Simple deterministic measurement matrix: application to EMG signals","authors":"Andrianiaina Ravelomanantsoa, H. Rabah, A. Rouane","doi":"10.1109/ICM.2014.7071810","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071810","url":null,"abstract":"In a wireless body sensor network (WBSN), the available energy and bandwidth are limited. Therefore, compressing the electromyogram (EMG) signal is of great importance since it is generally sensed at a relatively high frequency of the order of kHz. In this paper, we use the compressed sensing (CS) technique to compress and recover the EMG signal. The main advantage with CS is that its compression process requires less computational complexity. We propose a deterministic measurement matrix that greatly facilitates the implementation of the encoder device. The simulation and experiment results showed that the proposed approach can compress and recover the EMG signal without perceptible loss if the compression ratio was greater than or equal to 0.25, which saved up to 75 % of both the available bandwidth and power consumption of the transceiver. A comparison with the current stat-of-the-art of EMG compression shows that we obtained a better performance. Furthermore, the proposed encoder has the lowest computational complexity.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122574924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071822
Mageda Sharafeddine, Hasanin Harkous, Salim Mansour, M. Saghir, Haitham Akkary, H. Artail, Hazem M. Hajj
Modern high level synthesis (HLS) tools generate Register Transfer Language (RTL) from designs specified in high level languages such as C. By raising the design abstraction level while still promising competitive performance, HLS tools can greatly reduce design effort and time. Contemporary HLS tools can support most manual hardware design optimization techniques such as pipelining and fine-grain data communication. In this paper we study the effectiveness of the Xilinx Vivado HLS tool in generating hardware accelerators for map/reduce kernels, and we compare their performance and logic resource utilization to accelerators generated from hand-coded RTL. Our experimental results show that for most cases, the Vivado tool produces accelerators whose performance is within 9% of handcoded RTL, and whose logic resource utilization is significantly lower.
{"title":"On the efficiency of automatically generated accelerators for reconfigurable active SSDs","authors":"Mageda Sharafeddine, Hasanin Harkous, Salim Mansour, M. Saghir, Haitham Akkary, H. Artail, Hazem M. Hajj","doi":"10.1109/ICM.2014.7071822","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071822","url":null,"abstract":"Modern high level synthesis (HLS) tools generate Register Transfer Language (RTL) from designs specified in high level languages such as C. By raising the design abstraction level while still promising competitive performance, HLS tools can greatly reduce design effort and time. Contemporary HLS tools can support most manual hardware design optimization techniques such as pipelining and fine-grain data communication. In this paper we study the effectiveness of the Xilinx Vivado HLS tool in generating hardware accelerators for map/reduce kernels, and we compare their performance and logic resource utilization to accelerators generated from hand-coded RTL. Our experimental results show that for most cases, the Vivado tool produces accelerators whose performance is within 9% of handcoded RTL, and whose logic resource utilization is significantly lower.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116612514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071834
M. Fouda, A. Radwan
Mem-element based synaptic bridge is very promising topic due to its learning capability where the synaptic bridge can be build using either memristors or memcapacitors. In this paper, the detailed mathematical analysis of memcapacitor bridge circuit is introduced. This mathematical analysis is build when a current input signal is applied to excite the bridge. Closed form expressions for the required pulse width; synaptic weight; and conditions for positive, negative and zero synaptic weight are derived. The obtained expressions are verified using SPICE simulations showing very good matching.
{"title":"On the mathematical modeling of memcapacitor bridge synapses","authors":"M. Fouda, A. Radwan","doi":"10.1109/ICM.2014.7071834","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071834","url":null,"abstract":"Mem-element based synaptic bridge is very promising topic due to its learning capability where the synaptic bridge can be build using either memristors or memcapacitors. In this paper, the detailed mathematical analysis of memcapacitor bridge circuit is introduced. This mathematical analysis is build when a current input signal is applied to excite the bridge. Closed form expressions for the required pulse width; synaptic weight; and conditions for positive, negative and zero synaptic weight are derived. The obtained expressions are verified using SPICE simulations showing very good matching.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116835455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071850
M. A. Sankhare, E. Bergeret, P. Pannier, R. Coppard
Impacts of the series resistances scattering in fullprinted organic circuits manufacturing process is studied in this work. The modeling was done by using the well-known Amorphous-Silicon Hydrogenated Thin Film Transistor (A-Si: H TFT) model initially planned for Amorphous Thin Film Transistors. Extractions methods dedicated to this model were applied to organic thin film transistors (OTFTs) using an automatic procedure. This extraction procedure including all above-threshold parameters was applied to a sample of N-type and P-type organic transistors. It then appeared a non-negligible process dispersion correlated and fitted with ideal statistic model. Afterwards, these statistic models are integrated to model cards in order to achieve Monte-Carlo simulations, thus permitting to evaluate the impact of series resistances on full-printed organic circuits. An organic inverter was chosen as example to do the study.
本文研究了串联电阻散射对全印刷有机电路制造过程的影响。建模采用了著名的非晶硅氢化薄膜晶体管(A-Si: H TFT)模型，该模型最初计划用于非晶薄膜晶体管。将该模型的提取方法应用于有机薄膜晶体管(OTFTs)的自动提取。该提取程序包括所有高于阈值的参数，应用于n型和p型有机晶体管样品。出现了一个不可忽略的过程离散度，并与理想的统计模型相拟合。之后，这些统计模型被集成到模型卡中，以实现蒙特卡罗模拟，从而允许评估串联电阻对全印刷有机电路的影响。以有机逆变器为例进行了研究。
{"title":"Series resistances impacts on full-printed organic circuits","authors":"M. A. Sankhare, E. Bergeret, P. Pannier, R. Coppard","doi":"10.1109/ICM.2014.7071850","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071850","url":null,"abstract":"Impacts of the series resistances scattering in fullprinted organic circuits manufacturing process is studied in this work. The modeling was done by using the well-known Amorphous-Silicon Hydrogenated Thin Film Transistor (A-Si: H TFT) model initially planned for Amorphous Thin Film Transistors. Extractions methods dedicated to this model were applied to organic thin film transistors (OTFTs) using an automatic procedure. This extraction procedure including all above-threshold parameters was applied to a sample of N-type and P-type organic transistors. It then appeared a non-negligible process dispersion correlated and fitted with ideal statistic model. Afterwards, these statistic models are integrated to model cards in order to achieve Monte-Carlo simulations, thus permitting to evaluate the impact of series resistances on full-printed organic circuits. An organic inverter was chosen as example to do the study.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127822388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071812
M. R. Soliman, H. Fahmy, S. Habib
This paper introduces CUSPARC-M, a many-core message-passing processor based on the Cairo University SPARC processor, CUSPARC, core. CUSPARC-M consists of 16 cores arranged in 4×4 mesh architecture. A Network-on-Chip (NoC) that incorporates X-Y routing, wormhole switching and dynamic virtual channels for flow control provides intra-chip communication. The design is synthesized using TSMC 65nm LP kit achieving power consumption of 13.68× and area of 17× compared to CUSPARC. The NoC consumes only 5.2% of the total power. Simulating a 16-block JPEG encoder on 12 cores of CUSPARCM yielded up to 8.72× speedup factor relative to the single-core version.
{"title":"NoC-based many-core processor using CUSPARC architecture","authors":"M. R. Soliman, H. Fahmy, S. Habib","doi":"10.1109/ICM.2014.7071812","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071812","url":null,"abstract":"This paper introduces CUSPARC-M, a many-core message-passing processor based on the Cairo University SPARC processor, CUSPARC, core. CUSPARC-M consists of 16 cores arranged in 4×4 mesh architecture. A Network-on-Chip (NoC) that incorporates X-Y routing, wormhole switching and dynamic virtual channels for flow control provides intra-chip communication. The design is synthesized using TSMC 65nm LP kit achieving power consumption of 13.68× and area of 17× compared to CUSPARC. The NoC consumes only 5.2% of the total power. Simulating a 16-block JPEG encoder on 12 cores of CUSPARCM yielded up to 8.72× speedup factor relative to the single-core version.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126255581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071839
A. Merabet, Khandker Tawfique Ahmed, Md. Aminul Islam, Stephen Enebeli, R. Beguenane
An experimental setup is developed to emulate a wind turbine-generator system. The configuration of the wind energy conversion system is elaborated using OPAL-RT real-time simulator and electrical modules from Lab-Volt. In order to operate such system, a control scheme is designed for the generator side and grid side converters. The experiment can be reconfigured for conducting research and teaching various control concepts to both undergraduate and graduate students in wind energy systems.
{"title":"Wind turbine emulator using OPAL-RT real-time HIL/RCP laboratory","authors":"A. Merabet, Khandker Tawfique Ahmed, Md. Aminul Islam, Stephen Enebeli, R. Beguenane","doi":"10.1109/ICM.2014.7071839","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071839","url":null,"abstract":"An experimental setup is developed to emulate a wind turbine-generator system. The configuration of the wind energy conversion system is elaborated using OPAL-RT real-time simulator and electrical modules from Lab-Volt. In order to operate such system, a control scheme is designed for the generator side and grid side converters. The experiment can be reconfigured for conducting research and teaching various control concepts to both undergraduate and graduate students in wind energy systems.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133464982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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