Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071840
A. S. Shikoh, A. Popelka, F. Touati, M. Benammar, Zhaozhao Zhu, T. Mankowski, K. Balakrishnan, M. Mansuripur, C. Falco
High aspect ratio copper nanowires were synthesized, using a solution-based approach. The nanowires along with reduced graphene oxide thin films were sprayed onto glass and flexible substrates and later annealed in order to produce transparent conducting electrodes (TCEs). These electrodes exhibited 91.5% optical transmissivity and around 9- Ω/sq sheet resistance, which are comparable to Indium Tin Oxide (ITO). In addition, the hybrid TCEs, when exposed to ambient temperature showed slowed sheet resistance degradation. The electrodes deposited on a flexible substrate, showed immunity against any notable changes in the sheet resistance, when gone through numerous bending cycles. Adaption of such nanomaterials in conducting films could lead to the potential alternatives for the conventional ITO, with applications in numerous industries, including solar cells manufacturing.
{"title":"Highly transparent low sheet resistance electrodes for solar cell applications","authors":"A. S. Shikoh, A. Popelka, F. Touati, M. Benammar, Zhaozhao Zhu, T. Mankowski, K. Balakrishnan, M. Mansuripur, C. Falco","doi":"10.1109/ICM.2014.7071840","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071840","url":null,"abstract":"High aspect ratio copper nanowires were synthesized, using a solution-based approach. The nanowires along with reduced graphene oxide thin films were sprayed onto glass and flexible substrates and later annealed in order to produce transparent conducting electrodes (TCEs). These electrodes exhibited 91.5% optical transmissivity and around 9- Ω/sq sheet resistance, which are comparable to Indium Tin Oxide (ITO). In addition, the hybrid TCEs, when exposed to ambient temperature showed slowed sheet resistance degradation. The electrodes deposited on a flexible substrate, showed immunity against any notable changes in the sheet resistance, when gone through numerous bending cycles. Adaption of such nanomaterials in conducting films could lead to the potential alternatives for the conventional ITO, with applications in numerous industries, including solar cells manufacturing.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129580938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071806
Heba Abunahla, B. Mohammad, D. Homouz
Memristor has a potential to play a big role in the electronics industry as it provides small size, low cost and low power. However, the asymmetry between the ON and OFF switching times of the device hinders the adaption of the device in modern electronics systems. The contribution of this paper is to explore the relationship between the length of the memristor and the switching times. To achieve this the nonlinear model of oxygen vacancies is used. The model also includes coupling with electron transfer. The study shows that tuning the device length can affect the switching time significantly. This paper shows that having a device length of 10-nm gives switching ON and OFF times in the range of 4s - 13ns for applied voltage of 1V - 2.3V. In additon, the obtained OFF/ON switching time ratio is 3x compared to several order of magnitudes reported inliterature for device length of 50-nm. The proposed model is also used to study the effect of changing temperature, activation energy and frequency on memristor switching time.
{"title":"Effect of device, size, activation energy, temperature, and frequency on memristor switching time","authors":"Heba Abunahla, B. Mohammad, D. Homouz","doi":"10.1109/ICM.2014.7071806","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071806","url":null,"abstract":"Memristor has a potential to play a big role in the electronics industry as it provides small size, low cost and low power. However, the asymmetry between the ON and OFF switching times of the device hinders the adaption of the device in modern electronics systems. The contribution of this paper is to explore the relationship between the length of the memristor and the switching times. To achieve this the nonlinear model of oxygen vacancies is used. The model also includes coupling with electron transfer. The study shows that tuning the device length can affect the switching time significantly. This paper shows that having a device length of 10-nm gives switching ON and OFF times in the range of 4s - 13ns for applied voltage of 1V - 2.3V. In additon, the obtained OFF/ON switching time ratio is 3x compared to several order of magnitudes reported inliterature for device length of 50-nm. The proposed model is also used to study the effect of changing temperature, activation energy and frequency on memristor switching time.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116281270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071832
Yanan Sun, Hailong Jiao, V. Kursun
A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09% while providing similar read speed as compared to the conventional six-transistor (6T) SRAM cell in a 16nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57x with the proposed 9-CN-MOSFET SRAM cell as compared to the conventional 6T SRAM cell. Furthermore, a 1Kibit SRAM array with the new memory cells consumes 34.18% lower leakage power as compared to the memory array with 6T SRAM cells in idle mode.
{"title":"Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins","authors":"Yanan Sun, Hailong Jiao, V. Kursun","doi":"10.1109/ICM.2014.7071832","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071832","url":null,"abstract":"A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09% while providing similar read speed as compared to the conventional six-transistor (6T) SRAM cell in a 16nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57x with the proposed 9-CN-MOSFET SRAM cell as compared to the conventional 6T SRAM cell. Furthermore, a 1Kibit SRAM array with the new memory cells consumes 34.18% lower leakage power as compared to the memory array with 6T SRAM cells in idle mode.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128682130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071838
A. Wahba, Y. Khalaf, F. Farag
A new design for active filtering technique, used to remove the transmitted leakage signal in frequency division duplex (FDD) RF front-end transceivers, is presented. In this technique, the front-end SAW filter is replaced by an active on-chip bandpass filter. The proposed design covers all the UMTS bands as it can be controlled by switches to select the desired band of operation. The filtering technique is based on using a bandpass sink filter to selectively filter the transmitted leakage before the downconversion mixer, while not affecting the desired signal gain. The proposed circuit achieves (57 dB to 62 dB) of signal-to-leakage ratio for different UMTS bands. Designed in 0.13μm CMOS process, the proposed technique improve the IIP2 by 7 dB. However, the noise figure (NF) is degraded by 1.5 dB. The sink filter draws 4.8 mA current from 1.6 V supply.
提出了一种新的有源滤波技术，用于去除频分双工(FDD)射频前端收发器中传输的泄漏信号。在这种技术中，前端SAW滤波器被一个有源片上带通滤波器取代。所提出的设计涵盖了所有UMTS频段，因为它可以通过开关控制以选择所需的操作频段。该滤波技术是基于使用带通汇聚滤波器在下变频混频器之前选择性地滤波传输泄漏，同时不影响期望的信号增益。该电路在不同的UMTS频段实现了(57 dB ~ 62 dB)的信漏比。采用0.13μm CMOS工艺设计，IIP2提高了7 dB。但是，噪声系数(NF)降低了1.5 dB。sink滤波器从1.6 V电源中提取4.8 mA电流。
{"title":"New UMTS multiband design for TX-leakage suppression in RF front-end transcievers","authors":"A. Wahba, Y. Khalaf, F. Farag","doi":"10.1109/ICM.2014.7071838","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071838","url":null,"abstract":"A new design for active filtering technique, used to remove the transmitted leakage signal in frequency division duplex (FDD) RF front-end transceivers, is presented. In this technique, the front-end SAW filter is replaced by an active on-chip bandpass filter. The proposed design covers all the UMTS bands as it can be controlled by switches to select the desired band of operation. The filtering technique is based on using a bandpass sink filter to selectively filter the transmitted leakage before the downconversion mixer, while not affecting the desired signal gain. The proposed circuit achieves (57 dB to 62 dB) of signal-to-leakage ratio for different UMTS bands. Designed in 0.13μm CMOS process, the proposed technique improve the IIP2 by 7 dB. However, the noise figure (NF) is degraded by 1.5 dB. The sink filter draws 4.8 mA current from 1.6 V supply.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134231039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071829
M. Hajji, S. E. Naimi, B. Hajji, M. E. Hafyani
Currently, the conventional photo-voltaic (PV) systems suffer from the low electrical efficiency due to the operating temperature increase. Indeed, the photo-voltaic module only converts a small part of the absorbed radiation into electricity, with a greater part into heat, increasing its temperature and decreasing its electrical efficiency. The hybrid photo-voltaic/thermal (PV/T) technology offers opportunities that combine a simultaneous conversion of solar radiation into electricity and heat. These devices consist of PV modules and heat extraction units mounted together, by which a circulating fluid of lower temperature than that of PV modules which is heated by cooling them. In this paper, a numerical model of a hybrid photo-voltaic/thermal (PV/T) is being developed. This model is based on the energy balance equations and allows finding the temperature profile across the different layers of the PV/T collector. The electrical performance of the PV/T system is compared to the photo-voltaic panel (PV), and it is found to be higher than the panel PV module. The effect of the water mass flow rate m on the electrical performances of the PV/T is also studied in this work.
{"title":"A numerical modeling of hybrid photovoltaic/thermal(PV/T)collector","authors":"M. Hajji, S. E. Naimi, B. Hajji, M. E. Hafyani","doi":"10.1109/ICM.2014.7071829","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071829","url":null,"abstract":"Currently, the conventional photo-voltaic (PV) systems suffer from the low electrical efficiency due to the operating temperature increase. Indeed, the photo-voltaic module only converts a small part of the absorbed radiation into electricity, with a greater part into heat, increasing its temperature and decreasing its electrical efficiency. The hybrid photo-voltaic/thermal (PV/T) technology offers opportunities that combine a simultaneous conversion of solar radiation into electricity and heat. These devices consist of PV modules and heat extraction units mounted together, by which a circulating fluid of lower temperature than that of PV modules which is heated by cooling them. In this paper, a numerical model of a hybrid photo-voltaic/thermal (PV/T) is being developed. This model is based on the energy balance equations and allows finding the temperature profile across the different layers of the PV/T collector. The electrical performance of the PV/T system is compared to the photo-voltaic panel (PV), and it is found to be higher than the panel PV module. The effect of the water mass flow rate m on the electrical performances of the PV/T is also studied in this work.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121423084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071827
Ghaffari Fakhreddine, F. Sahraoui, M. A. Benkhelifa, B. Granado, M. Kacou, O. Romain
SRAM-based FPGAs are very sensitive to harsh conditions, like radiations or ionizations, and need to be hardened to insure correct running. To validate any fault tolerant solution for these SRAM-FPGA, fault injection campaigns must be conducted carefully. In this work, we present a new design flow to perform localized internal fault injection on specific parts of a Design Under Test (DUT). To achieve this, we combine between Partial Dynamic Reconfiguration (PDR) via Internal Configuration Access Port (ICAP) for rapid fault insertion on SRAM; Isolation Design Flow (IDF) to isolate both of placement and routing of Design Under Test into a specific partial region. Moreover, we applied realistic fault distribution laws deduced from ground-based radiation experiments to reflect realistic behavior of FPGA toward radiations. The implemented injection platform using this flow shows the importance of using distribution laws driven approach. Results show that our fault injection experiments are done more than 15 times faster than one of the traditional FPGA based fault injection methods with a speed-up on simulation time up to 8.
{"title":"Fast SRAM-FPGA fault injection platform based on dynamic partial reconfiguration","authors":"Ghaffari Fakhreddine, F. Sahraoui, M. A. Benkhelifa, B. Granado, M. Kacou, O. Romain","doi":"10.1109/ICM.2014.7071827","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071827","url":null,"abstract":"SRAM-based FPGAs are very sensitive to harsh conditions, like radiations or ionizations, and need to be hardened to insure correct running. To validate any fault tolerant solution for these SRAM-FPGA, fault injection campaigns must be conducted carefully. In this work, we present a new design flow to perform localized internal fault injection on specific parts of a Design Under Test (DUT). To achieve this, we combine between Partial Dynamic Reconfiguration (PDR) via Internal Configuration Access Port (ICAP) for rapid fault insertion on SRAM; Isolation Design Flow (IDF) to isolate both of placement and routing of Design Under Test into a specific partial region. Moreover, we applied realistic fault distribution laws deduced from ground-based radiation experiments to reflect realistic behavior of FPGA toward radiations. The implemented injection platform using this flow shows the importance of using distribution laws driven approach. Results show that our fault injection experiments are done more than 15 times faster than one of the traditional FPGA based fault injection methods with a speed-up on simulation time up to 8.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124219552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071823
A. Qassem, M. El-Nozahi, H. Ragai
This paper presents a comparison between several topologies of Wideband Common Gate Low Noise Amplifiers including conventional and multiple feedback topologies. The comparison is based on finding the best Figure of Merit (FOM) of the different architectures. Accordingly, the proposed design steps to yield the best FOM for each architecture are presented. This FOM shows the tradeoff between noise, nonlinearity, and power consumption. The comparison is verified using circuit level simulation in the 0.13 μm CMOS technology node. Results show that for a certain bias current, the FOM is appreciably enhanced. For the conventional common gate LNA with current reuse, the highest FOM is obtained in spite of its high noise figure compared to other architectures.
{"title":"Analysis and design of wideband common-gate low noise amplifier","authors":"A. Qassem, M. El-Nozahi, H. Ragai","doi":"10.1109/ICM.2014.7071823","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071823","url":null,"abstract":"This paper presents a comparison between several topologies of Wideband Common Gate Low Noise Amplifiers including conventional and multiple feedback topologies. The comparison is based on finding the best Figure of Merit (FOM) of the different architectures. Accordingly, the proposed design steps to yield the best FOM for each architecture are presented. This FOM shows the tradeoff between noise, nonlinearity, and power consumption. The comparison is verified using circuit level simulation in the 0.13 μm CMOS technology node. Results show that for a certain bias current, the FOM is appreciably enhanced. For the conventional common gate LNA with current reuse, the highest FOM is obtained in spite of its high noise figure compared to other architectures.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131381480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071797
Hoda Abdelsalam, E. Hegazi, H. Mostafa, Y. Ismail
The desire of having applications covering all service specifications tremendously increases the demand for multi-band multi-standard receivers. A programmable receiver front-end architecture for multi-band multi-standard receivers is proposed. The receiver adopts a down-conversion quadrature band-pass FIR charge sampling mixer programmed via its controlling clocks. A time varying impedance matching network provides further selectivity. The architecture is simulated over three different frequencies spanning two octaves (2G, 1G and 500MHz) targeting LTE specifications. The proposed design achieves conversion gain of 23dB to 28dB, Noise Figure (NF) of 7dB to 9dB, out of band IIP3 of -1.9dBm to -5.6dBm, in band IIP3 of -1.5dBm to -5.7dBm and S11 <;-10 dB. The design is implemented using a 65nm CMOS technology.
{"title":"A programmable receiver front-end architecture supporting LTE","authors":"Hoda Abdelsalam, E. Hegazi, H. Mostafa, Y. Ismail","doi":"10.1109/ICM.2014.7071797","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071797","url":null,"abstract":"The desire of having applications covering all service specifications tremendously increases the demand for multi-band multi-standard receivers. A programmable receiver front-end architecture for multi-band multi-standard receivers is proposed. The receiver adopts a down-conversion quadrature band-pass FIR charge sampling mixer programmed via its controlling clocks. A time varying impedance matching network provides further selectivity. The architecture is simulated over three different frequencies spanning two octaves (2G, 1G and 500MHz) targeting LTE specifications. The proposed design achieves conversion gain of 23dB to 28dB, Noise Figure (NF) of 7dB to 9dB, out of band IIP3 of -1.9dBm to -5.6dBm, in band IIP3 of -1.5dBm to -5.7dBm and S11 <;-10 dB. The design is implemented using a 65nm CMOS technology.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123240021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071794
A. Jarndal
In this paper, a parameter extraction method for GaN HEMTs is developed. The main advantage of this approach is its accuracy, reliability and dependence on only pinch-off Sparameter measurements to extract the parasitic elements of the device. The extraction results are compared with other extraction results based on pinch-off and forward measurements. The comparison result demonstrates the validity of the proposed method for small- and large-signal modeling of GaN devices.
{"title":"Parasitic elements extraction of AlGaN/GaN HEMTs on SiC substrate using only pinch-off S-parameter measurements","authors":"A. Jarndal","doi":"10.1109/ICM.2014.7071794","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071794","url":null,"abstract":"In this paper, a parameter extraction method for GaN HEMTs is developed. The main advantage of this approach is its accuracy, reliability and dependence on only pinch-off Sparameter measurements to extract the parasitic elements of the device. The extraction results are compared with other extraction results based on pinch-off and forward measurements. The comparison result demonstrates the validity of the proposed method for small- and large-signal modeling of GaN devices.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122660538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071804
A. Benabdelmoumene, B. Djezzar, H. Tahi, A. Chenouf, M. Goudjil, R. Serhane, F. Larbi, M. Kechouane
Negative bias temperature instability (NBTI) has been examined on p-MOSFET and n-MOSFET with different channel lengths. The experiments have shown a channel length dependence on NBTI-degradation, indicating inhomogeneous distribution of NBTI-induced traps along the channel. Simulation results, using SILVACO 2D TCAD tools, have revealed that the degradation is mainly located in the lightly doped drain (LDD) region. Interestingly, simulation results have exhibited the presence of a breakpoint, below which the degradation in the effective channel dominates that of the LDD region and vice versa.
{"title":"Does NBTI effect in MOS transistors depend on channel length?","authors":"A. Benabdelmoumene, B. Djezzar, H. Tahi, A. Chenouf, M. Goudjil, R. Serhane, F. Larbi, M. Kechouane","doi":"10.1109/ICM.2014.7071804","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071804","url":null,"abstract":"Negative bias temperature instability (NBTI) has been examined on p-MOSFET and n-MOSFET with different channel lengths. The experiments have shown a channel length dependence on NBTI-degradation, indicating inhomogeneous distribution of NBTI-induced traps along the channel. Simulation results, using SILVACO 2D TCAD tools, have revealed that the degradation is mainly located in the lightly doped drain (LDD) region. Interestingly, simulation results have exhibited the presence of a breakpoint, below which the degradation in the effective channel dominates that of the LDD region and vice versa.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122382651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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