Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108697
Takafumi Gemma, M. Hasegawa
This paper proposes a robust decoupling current control system to magnetic saturation phenomenon using an extended flux observer for synchronous reluctance motors (Syn-RMs). SynRMs possess considerable magnetic non-linearity, which gives rise to the difficulty in highly accurate decoupling current control. Hence, to realize robust decoupling current control system to magnetic saturation phenomenon, inductance profiles need to be found at various current points for driving SynRMs. This method, however, requires to prepare highly accurate look-up-table of inductances in advance. This paper proposes robust decoupling current control system to magnetic saturation phenomenon without the table of inductances. The proposed method employs the extended flux observer for the realization of robust decoupling control. In addition, the extended flux observer suitable for proposed method is discussed by analyses of bode diagram. Finally, experimental results show the feasibility of the proposed method in this paper.
{"title":"Robust decoupling current control to magnetic saturation for SynRM using flux observer","authors":"Takafumi Gemma, M. Hasegawa","doi":"10.1109/ISIEA.2011.6108697","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108697","url":null,"abstract":"This paper proposes a robust decoupling current control system to magnetic saturation phenomenon using an extended flux observer for synchronous reluctance motors (Syn-RMs). SynRMs possess considerable magnetic non-linearity, which gives rise to the difficulty in highly accurate decoupling current control. Hence, to realize robust decoupling current control system to magnetic saturation phenomenon, inductance profiles need to be found at various current points for driving SynRMs. This method, however, requires to prepare highly accurate look-up-table of inductances in advance. This paper proposes robust decoupling current control system to magnetic saturation phenomenon without the table of inductances. The proposed method employs the extended flux observer for the realization of robust decoupling control. In addition, the extended flux observer suitable for proposed method is discussed by analyses of bode diagram. Finally, experimental results show the feasibility of the proposed method in this paper.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129622093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108803
A. Eroglu, E. Gose, A. Matthew, Todd Hauter
Low cost multiple input multiple output (MIMO) Wireless Data Acquisition System (WDAS) for long range operation has been developed, simulated and implemented. The reference input and output measurement circuits for various sensors to measure strain, vibration and temperature have been designed, and integrated. Low cost microcontroller is used to process and condition the signals that are acquired from measurement circuits. The sequential logic is used to capture and transmit the measurement signals using single receiver and transmitter pair instead of conventional MIMO antenna systems. This reduced the cost significantly. The wireless communication has been established and data acquired from sensors within 20 mile of distance. The acquired data is then processed at the base station using data acquisition system (DAS). The system that is developed can be used for structural health monitoring, or medical applications in rural areas where access is difficult.
{"title":"Design of long range MIMO Wireless Data Acquisition System","authors":"A. Eroglu, E. Gose, A. Matthew, Todd Hauter","doi":"10.1109/ISIEA.2011.6108803","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108803","url":null,"abstract":"Low cost multiple input multiple output (MIMO) Wireless Data Acquisition System (WDAS) for long range operation has been developed, simulated and implemented. The reference input and output measurement circuits for various sensors to measure strain, vibration and temperature have been designed, and integrated. Low cost microcontroller is used to process and condition the signals that are acquired from measurement circuits. The sequential logic is used to capture and transmit the measurement signals using single receiver and transmitter pair instead of conventional MIMO antenna systems. This reduced the cost significantly. The wireless communication has been established and data acquired from sensors within 20 mile of distance. The acquired data is then processed at the base station using data acquisition system (DAS). The system that is developed can be used for structural health monitoring, or medical applications in rural areas where access is difficult.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127198310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108681
C. Chiang
In this paper, a CMOS retinal rotational sensor for clockwise/counterclockwise detecting and velocity measuring is proposed. The proposed chip is attractive due to the fact that analog image processing circuits within a pixel are implemented by digital circuits. It can be integrated robustly and compactly. Based upon the device parameters of 0.35 µm 2P4M CMOS technology with 3 V power supply, all the functions and performance of the proposed CMOS retinal rotational sensor for clockwise/counterclockwise detecting and velocity measuring are successfully tested and proven through SPICE simulations. The chip area is 1.792 × 1.795 mm2. The proposed chip is suitable for rotational image detecting and velocity measuring.
{"title":"A CMOS retinal rotational sensor for clockwise/counterclockwise detecting and velocity measuring","authors":"C. Chiang","doi":"10.1109/ISIEA.2011.6108681","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108681","url":null,"abstract":"In this paper, a CMOS retinal rotational sensor for clockwise/counterclockwise detecting and velocity measuring is proposed. The proposed chip is attractive due to the fact that analog image processing circuits within a pixel are implemented by digital circuits. It can be integrated robustly and compactly. Based upon the device parameters of 0.35 µm 2P4M CMOS technology with 3 V power supply, all the functions and performance of the proposed CMOS retinal rotational sensor for clockwise/counterclockwise detecting and velocity measuring are successfully tested and proven through SPICE simulations. The chip area is 1.792 × 1.795 mm2. The proposed chip is suitable for rotational image detecting and velocity measuring.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126834593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108776
K. Kamil, K. H. Chong, S. K. Tiong, K. Yeap
In this paper, a crossover factor, fTIG is introduced to the Finite Persisting Sphere Genetic Algorithm (FPSGA). The factor provides a variable range of the loop in the process of Finite Persisting Sphere. By the existing of the variable range, the risk to have too large number of loop or too small number of loop in the FPSGA can be reduced. Too large number of loop will risk of repeating using the same data and too small number of loop will cause the loss of good genes in the FPSGA. By the proposed approach, potential to achieve the global solution in a small number of population will be increased and at the same time less time required running the process in the loop. This paper show that FPSGA with fTIG has higher global solution compared to other method and this method has faster converges to the global solution. The experiment result revealed the superiority of fTIG in FPSGA.
{"title":"The implementation of crossover factor, fTIG in the Finite Persisting Sphere Genetic Algorithm","authors":"K. Kamil, K. H. Chong, S. K. Tiong, K. Yeap","doi":"10.1109/ISIEA.2011.6108776","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108776","url":null,"abstract":"In this paper, a crossover factor, fTIG is introduced to the Finite Persisting Sphere Genetic Algorithm (FPSGA). The factor provides a variable range of the loop in the process of Finite Persisting Sphere. By the existing of the variable range, the risk to have too large number of loop or too small number of loop in the FPSGA can be reduced. Too large number of loop will risk of repeating using the same data and too small number of loop will cause the loss of good genes in the FPSGA. By the proposed approach, potential to achieve the global solution in a small number of population will be increased and at the same time less time required running the process in the loop. This paper show that FPSGA with fTIG has higher global solution compared to other method and this method has faster converges to the global solution. The experiment result revealed the superiority of fTIG in FPSGA.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116834965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108714
Liew Yian Mei, B. A. Rosdi, Lee Cheen Kok
Manual place-and-route method in handling structured datapath placement usually requires long design cycles and high design cost. To minimize the human effort in placing cells, Integrated Circuit Compiler (ICC) has been introduced to help user in automate place and route with its powerful embedded placement algorithm. A structured datapath design contains repeating dataflow logics, which is highly regular and structured. Currently, the automated placement tool from ICC is incapable to place structured datapath design effectively. This paper describes an approach for customizing the ICC tool to automate structured datapath placement in Very Large Scaled Integrated (VLSI) layout and achieve better placement quality. An algorithm named structured datapath relative placement (SDP-RP) is proposed to obtain the relative placement (RP) of a SDP design. From the initial placement generated by ICC, structured registers are extracted. Connectivity of all the related cells is traced to form the RP groups for each structured pattern. The relative placement constraint file containing RP groups is generated and read by ICC tool to improve placement optimization process. The implementation of this algorithm in ICC placement flow for SDP design has achieved structural placement with 2∼24% timing improvement and cell counts reduction.
{"title":"A methodology for automation structured datapath placement In VLSI design","authors":"Liew Yian Mei, B. A. Rosdi, Lee Cheen Kok","doi":"10.1109/ISIEA.2011.6108714","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108714","url":null,"abstract":"Manual place-and-route method in handling structured datapath placement usually requires long design cycles and high design cost. To minimize the human effort in placing cells, Integrated Circuit Compiler (ICC) has been introduced to help user in automate place and route with its powerful embedded placement algorithm. A structured datapath design contains repeating dataflow logics, which is highly regular and structured. Currently, the automated placement tool from ICC is incapable to place structured datapath design effectively. This paper describes an approach for customizing the ICC tool to automate structured datapath placement in Very Large Scaled Integrated (VLSI) layout and achieve better placement quality. An algorithm named structured datapath relative placement (SDP-RP) is proposed to obtain the relative placement (RP) of a SDP design. From the initial placement generated by ICC, structured registers are extracted. Connectivity of all the related cells is traced to form the RP groups for each structured pattern. The relative placement constraint file containing RP groups is generated and read by ICC tool to improve placement optimization process. The implementation of this algorithm in ICC placement flow for SDP design has achieved structural placement with 2∼24% timing improvement and cell counts reduction.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131056465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108761
A. S. Al-Khalid, S. Omran
This paper describes a very fast method of calculating the power factor (p.f.) for a power line. Only two progressive samples of the current and voltage are required to execute the measurement. A phase locked loop (PLL) frequency multiplier scheme allows for an accurate measurement independent of the power line frequency fluctuation.
{"title":"A very fast power factor calculation method","authors":"A. S. Al-Khalid, S. Omran","doi":"10.1109/ISIEA.2011.6108761","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108761","url":null,"abstract":"This paper describes a very fast method of calculating the power factor (p.f.) for a power line. Only two progressive samples of the current and voltage are required to execute the measurement. A phase locked loop (PLL) frequency multiplier scheme allows for an accurate measurement independent of the power line frequency fluctuation.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132031075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108712
Md. Arafat Hossain Khan, A. Rahman, T. Muntasir, U. Acharjee, Md. Abu Layek
Early voltage is indeed a very simple form of calculation for mathematical ease. But Channel Length Modulation is not actually linear. The non-linear Channel Length Modulation is in fact tells nothing strict about the Early voltage conception of MOSFET. For very short channel devices or thin oxide insulation, there arises lots of parameters which must be considered. The simulators uses lot more difficult equations to calculate the quantities. This paper deals with HSPICE, that uses hundreds of parameters to return the real world situation as it considers lots of non-ideal effects like- Non-uniform doping, Short channel DIBL effects, Narrow-width effect, Gate to substrate leakage, Bulk charge effect, Velocity saturation of intrinsic and extrinsic case, Drain induced threshold shift by pocket implant, Velocity overshoot, Flicker noise, Temperature dependence and a lot more complexities [1]. This paper describes the numerical approach to show whether the existing Early voltage approximation is valid for BSIM3 or BSIM4 MOSFET Model equations of HSPICE as they almost predict the real world situation. The most significant contribution of this paper is to propose a multiple polynomial regression method that can best approximate the Early voltage as well as the MOSFET characteristics in saturation.
{"title":"Multiple polynomial regression for modeling a MOSFET in saturation to validate the Early voltage","authors":"Md. Arafat Hossain Khan, A. Rahman, T. Muntasir, U. Acharjee, Md. Abu Layek","doi":"10.1109/ISIEA.2011.6108712","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108712","url":null,"abstract":"Early voltage is indeed a very simple form of calculation for mathematical ease. But Channel Length Modulation is not actually linear. The non-linear Channel Length Modulation is in fact tells nothing strict about the Early voltage conception of MOSFET. For very short channel devices or thin oxide insulation, there arises lots of parameters which must be considered. The simulators uses lot more difficult equations to calculate the quantities. This paper deals with HSPICE, that uses hundreds of parameters to return the real world situation as it considers lots of non-ideal effects like- Non-uniform doping, Short channel DIBL effects, Narrow-width effect, Gate to substrate leakage, Bulk charge effect, Velocity saturation of intrinsic and extrinsic case, Drain induced threshold shift by pocket implant, Velocity overshoot, Flicker noise, Temperature dependence and a lot more complexities [1]. This paper describes the numerical approach to show whether the existing Early voltage approximation is valid for BSIM3 or BSIM4 MOSFET Model equations of HSPICE as they almost predict the real world situation. The most significant contribution of this paper is to propose a multiple polynomial regression method that can best approximate the Early voltage as well as the MOSFET characteristics in saturation.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133796406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108788
H. Hussin, N. Soin
Negative Bias Temperature Instability is a serious reliability concerns for modern p-MOSFETs with Effective Oxide Thickness less than 2nm. This reliability problem can severely affect the device performance and limit the lifetime of the device. This paper is focusing on the safe operating condition and lifetime estimation of the p-MOSFET device with regard to NBTI effects. To explore the variation of safe operating condition and lifetime estimation, p-MOSFET having EOT 1nm was systematically simulated by varying the hydrogen species, measurement delay, stress temperature and stress gate voltage. The hydrogen species is varied based on molecular and atomic hydrogen. The measurement delay is simulated based on the measurement delay as found in literature. The stress temperature is varied from 80°C to 100°C and the stress gate voltage is varied from −0.5V to −1V. The simulation result shows that the safe operating voltage for molecular hydrogen and atomic hydrogen is almost the same but the device lifetime estimation for molecular hydrogen is less than atomic hydrogen. For higher measurement delay, the lifetime estimation is higher compare to no delay while the safe operating voltage estimated for 5 years lifetime shows no significant different. The lifetime estimation for variation of temperature shows that the higher stress temperature contributes to more reduction in the device lifetime. The safe operating voltage condition is decreases as the temperature increases. Meanwhile, for the simulated stress voltage, the lifetime estimation of the device is increases as the absolute value of the stress voltage decreases.
{"title":"Safe operating condition and lifetime estimation in p-MOSFET device due to Negative Bias Temperature Instability","authors":"H. Hussin, N. Soin","doi":"10.1109/ISIEA.2011.6108788","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108788","url":null,"abstract":"Negative Bias Temperature Instability is a serious reliability concerns for modern p-MOSFETs with Effective Oxide Thickness less than 2nm. This reliability problem can severely affect the device performance and limit the lifetime of the device. This paper is focusing on the safe operating condition and lifetime estimation of the p-MOSFET device with regard to NBTI effects. To explore the variation of safe operating condition and lifetime estimation, p-MOSFET having EOT 1nm was systematically simulated by varying the hydrogen species, measurement delay, stress temperature and stress gate voltage. The hydrogen species is varied based on molecular and atomic hydrogen. The measurement delay is simulated based on the measurement delay as found in literature. The stress temperature is varied from 80°C to 100°C and the stress gate voltage is varied from −0.5V to −1V. The simulation result shows that the safe operating voltage for molecular hydrogen and atomic hydrogen is almost the same but the device lifetime estimation for molecular hydrogen is less than atomic hydrogen. For higher measurement delay, the lifetime estimation is higher compare to no delay while the safe operating voltage estimated for 5 years lifetime shows no significant different. The lifetime estimation for variation of temperature shows that the higher stress temperature contributes to more reduction in the device lifetime. The safe operating voltage condition is decreases as the temperature increases. Meanwhile, for the simulated stress voltage, the lifetime estimation of the device is increases as the absolute value of the stress voltage decreases.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"359 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133952819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108755
S. Ali, Humza Akhtar, S. Munir, Umair bin Ikram
While designing all the attributes of a Hybrid vehicle, the most important factor is the fuel economy. Reduced aerodynamic drag and light weight vehicle chassis are major factors for improving the fuel economy. The series hybrid vehicle designed utilizes gasoline to generate electricity which is then stabilized and stored in the super capacitor banks. This stored electrical energy is then used for driving the brushless DC motors. A specially designed control system regulates the transmission of electrical energy through a automatic voltage regulator (AVR), programmed for controlling the output of the generator and the super capacitor banks. This results in improved efficiency and reduction in mechanical losses.
{"title":"Design, simulation and fabrication of a fuel efficient urban class series hybrid vehicle","authors":"S. Ali, Humza Akhtar, S. Munir, Umair bin Ikram","doi":"10.1109/ISIEA.2011.6108755","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108755","url":null,"abstract":"While designing all the attributes of a Hybrid vehicle, the most important factor is the fuel economy. Reduced aerodynamic drag and light weight vehicle chassis are major factors for improving the fuel economy. The series hybrid vehicle designed utilizes gasoline to generate electricity which is then stabilized and stored in the super capacitor banks. This stored electrical energy is then used for driving the brushless DC motors. A specially designed control system regulates the transmission of electrical energy through a automatic voltage regulator (AVR), programmed for controlling the output of the generator and the super capacitor banks. This results in improved efficiency and reduction in mechanical losses.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122631311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108754
H. Zulkefle, L. N. Ismail, R. Abu Bakar, M. Mahmood
Magnesium Oxide, MgO is inorganic material with wide band gap (7.8eV) and suitable to be used as dielectric layer. Due to its chemical and structural properties, MgO also can be used as template to prepare ferroelectric thin film [1–3]. In this work, MgO thin films with different molar concentration from 0.1M to 1M were prepared using sol-gel spin coating technique. Magnesium acetate tetrahydrate, ethanol and nitric acid were used as precursor, solvent and stabilizer respectively. The MgO thin films were deposited on the glass substrate and subjected to electrical and structural characterizations. Both electrical and structural characterizations were performed using two point probes (BUKOH KEIKI-EP2000), surface profiler (Veeco) and atomic force microscope respectively. The experimental results show that the thin films resistivity increased from 5.09 ×103 Ω.cm to 2.33 ×104 Ω.cm as the precursor molar concentration increased. The MgO films with 0.4M was observed to be the best MgO films to be used as dielectric layer due to its electrical and structural properties which are uniform, non-porous and small particle size around 43nm.
{"title":"Molar concentration effect on MgO thin films properties","authors":"H. Zulkefle, L. N. Ismail, R. Abu Bakar, M. Mahmood","doi":"10.1109/ISIEA.2011.6108754","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108754","url":null,"abstract":"Magnesium Oxide, MgO is inorganic material with wide band gap (7.8eV) and suitable to be used as dielectric layer. Due to its chemical and structural properties, MgO also can be used as template to prepare ferroelectric thin film [1–3]. In this work, MgO thin films with different molar concentration from 0.1M to 1M were prepared using sol-gel spin coating technique. Magnesium acetate tetrahydrate, ethanol and nitric acid were used as precursor, solvent and stabilizer respectively. The MgO thin films were deposited on the glass substrate and subjected to electrical and structural characterizations. Both electrical and structural characterizations were performed using two point probes (BUKOH KEIKI-EP2000), surface profiler (Veeco) and atomic force microscope respectively. The experimental results show that the thin films resistivity increased from 5.09 ×103 Ω.cm to 2.33 ×104 Ω.cm as the precursor molar concentration increased. The MgO films with 0.4M was observed to be the best MgO films to be used as dielectric layer due to its electrical and structural properties which are uniform, non-porous and small particle size around 43nm.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123843809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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