Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108719
C. Chiang
In this paper, a CMOS retinal computational sensor for 2-D image tracking and velocity measuring is proposed. The proposed chip is attractive due to the fact that analog image processing circuits within a pixel are implemented by digital circuits. It can be integrated robustly and compactly. Based upon the device parameters of 0.35 µm 2P4M CMOS technology with 3 V power supply, all the functions and performance of the proposed CMOS retinal computational sensor for 2-D image tracking and velocity measuring are successfully tested and proven through SPICE simulations. The chip area is 2.34 × 2.33 mm2. The proposed chip is suitable for robot tracking and 2-D image velocity measuring.
{"title":"A CMOS retinal computational sensor for 2-D image tracking and velocity measuring","authors":"C. Chiang","doi":"10.1109/ISIEA.2011.6108719","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108719","url":null,"abstract":"In this paper, a CMOS retinal computational sensor for 2-D image tracking and velocity measuring is proposed. The proposed chip is attractive due to the fact that analog image processing circuits within a pixel are implemented by digital circuits. It can be integrated robustly and compactly. Based upon the device parameters of 0.35 µm 2P4M CMOS technology with 3 V power supply, all the functions and performance of the proposed CMOS retinal computational sensor for 2-D image tracking and velocity measuring are successfully tested and proven through SPICE simulations. The chip area is 2.34 × 2.33 mm2. The proposed chip is suitable for robot tracking and 2-D image velocity measuring.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123341404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108777
M. A. Ayu, T. Mantoro
Bahasa Indonesia and English have many differences in their linguistic structure. Translating sentences from one language to another is not a straight forward task for these pair of languages. Example-Based Machine Translation (EBMT) approach which introduced as a new paradigm in machine translation field is used in this initial work of developing a Bahasa Indonesia to English machine translation. The machine translation is developed by utilizing Moses system. Experiments in translating Bahasa Indonesia to English by tuning the parameters in Moses decoder have set alight about how the effects of manipulating the weight on translation model, language model, distortion (re-ordering) and word penalty on increasing the quality of the translation.
{"title":"An Example-Based Machine Translation approach for Bahasa Indonesia to English: An experiment using MOSES","authors":"M. A. Ayu, T. Mantoro","doi":"10.1109/ISIEA.2011.6108777","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108777","url":null,"abstract":"Bahasa Indonesia and English have many differences in their linguistic structure. Translating sentences from one language to another is not a straight forward task for these pair of languages. Example-Based Machine Translation (EBMT) approach which introduced as a new paradigm in machine translation field is used in this initial work of developing a Bahasa Indonesia to English machine translation. The machine translation is developed by utilizing Moses system. Experiments in translating Bahasa Indonesia to English by tuning the parameters in Moses decoder have set alight about how the effects of manipulating the weight on translation model, language model, distortion (re-ordering) and word penalty on increasing the quality of the translation.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122756876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108684
R. Baharom, N. R. Hamzah, M. K. Hamzah
In this paper, a single-phase DC power supply based on single-phase matrix converter (SPMC) with reduced number of switches is proposed. In the proposed approach, only six switches of the typical SPMC topology are used to convert the voltage 240 Vrms (50Hz) input to a 12 VDC DC link. In the proposed topology a current control loop is used to ensure that the supply current waveform is continuous, sinusoidal and in-phase with the supply voltage resulting in high input power factor with low total harmonic distortion (THD) level. Therefore, the input currents are of a high quality and devoid of low frequency harmonics under varying load conditions, inherently. Simulation results verify the feasibility of the proposed converter.
{"title":"DC power supply based on single-phase matrix converter with reduced number of switches","authors":"R. Baharom, N. R. Hamzah, M. K. Hamzah","doi":"10.1109/ISIEA.2011.6108684","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108684","url":null,"abstract":"In this paper, a single-phase DC power supply based on single-phase matrix converter (SPMC) with reduced number of switches is proposed. In the proposed approach, only six switches of the typical SPMC topology are used to convert the voltage 240 Vrms (50Hz) input to a 12 VDC DC link. In the proposed topology a current control loop is used to ensure that the supply current waveform is continuous, sinusoidal and in-phase with the supply voltage resulting in high input power factor with low total harmonic distortion (THD) level. Therefore, the input currents are of a high quality and devoid of low frequency harmonics under varying load conditions, inherently. Simulation results verify the feasibility of the proposed converter.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125985379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108806
Tommaso Cecchini, Tommaso Baldetti, L. Fanucci, A. Rocchi
The traditional approach for mixed-signal systems is partitioning the design at the beginning of its development cycle: digital and analog portions are then designed and verified separately. The digital design flow is typically top-down, thus allowing a continuous verification of the matching between specification and simulation results. Instead the analog flow is more frequently bottom-up and this makes hard to feedback information from the bottom level simulations to the design top level, being almost impossible SPICE simulations of the whole system (due to the excessive simulation time, convergence troubles and computational effort). This kind of mixed-signal separated flow can easily lead to a final assembly which is not sufficiently tested (such strategy cannot provide the designer with much confidence that digital and analog portions will interface correctly) and thus it's extremely difficult to debug. A full covering test strategy is not allowed also for another reason: many tests are not possible at HDL level, because of the lack of interactivity during simulation process. In fact, if we consider for example a generic calibration sequence, the procedure must assign parameter values depending on DUT state, by changing actions to perform, relating to effects of the previous acted. In this paper we propose a complete environment to test together analog and digital parts by using a semi-automatic VHDL-AMS flow adding the use of Python scripts to drive the simulation, interacting with both Verilog top-level model or real chip, creating a dynamic co-operation for real-time data processing with high re-usability for a fast conditional complete test flow.
{"title":"Efficient test environment for multi-level simulations of mixed-signal systems on chip","authors":"Tommaso Cecchini, Tommaso Baldetti, L. Fanucci, A. Rocchi","doi":"10.1109/ISIEA.2011.6108806","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108806","url":null,"abstract":"The traditional approach for mixed-signal systems is partitioning the design at the beginning of its development cycle: digital and analog portions are then designed and verified separately. The digital design flow is typically top-down, thus allowing a continuous verification of the matching between specification and simulation results. Instead the analog flow is more frequently bottom-up and this makes hard to feedback information from the bottom level simulations to the design top level, being almost impossible SPICE simulations of the whole system (due to the excessive simulation time, convergence troubles and computational effort). This kind of mixed-signal separated flow can easily lead to a final assembly which is not sufficiently tested (such strategy cannot provide the designer with much confidence that digital and analog portions will interface correctly) and thus it's extremely difficult to debug. A full covering test strategy is not allowed also for another reason: many tests are not possible at HDL level, because of the lack of interactivity during simulation process. In fact, if we consider for example a generic calibration sequence, the procedure must assign parameter values depending on DUT state, by changing actions to perform, relating to effects of the previous acted. In this paper we propose a complete environment to test together analog and digital parts by using a semi-automatic VHDL-AMS flow adding the use of Python scripts to drive the simulation, interacting with both Verilog top-level model or real chip, creating a dynamic co-operation for real-time data processing with high re-usability for a fast conditional complete test flow.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117087768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108717
Wong Wai Mun, A. Marzuki, Wong Yew Honn
Noise simulators were never accurate estimators of interconnect noise values as the switching pattern, slew and delay in a cluster of adjacent nets were never addressed. In modern signal integrity flows, a very high level of pessimism is incorporated into the noise methodology to augment the lack of accuracy, such as lumped aggression, noise ramps and lumped slews. Desirably, such pessimistic assumptions are much easier to compute hence efficient on simulation runtime, but often than ever it will result in an overdesigned chip. This paper discusses a recipe to reduce pessimism in interconnect noise methodologies by effectively modeling the downstream degradation on the aggression line. We will be presenting an aggression slew estimation method derived from the Elmore delay, which has less than 0.8% error compared to SPICE simulations and is inclined towards the higher slew bound when compared to both Elmore's delay and SPICE. We also show that the dAP method reduces the average reported noise by 5% even when we account for victim-aggressor reverse aggression issues.
{"title":"An improved interconnect noise methodology for reduced pessimism using dAP model","authors":"Wong Wai Mun, A. Marzuki, Wong Yew Honn","doi":"10.1109/ISIEA.2011.6108717","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108717","url":null,"abstract":"Noise simulators were never accurate estimators of interconnect noise values as the switching pattern, slew and delay in a cluster of adjacent nets were never addressed. In modern signal integrity flows, a very high level of pessimism is incorporated into the noise methodology to augment the lack of accuracy, such as lumped aggression, noise ramps and lumped slews. Desirably, such pessimistic assumptions are much easier to compute hence efficient on simulation runtime, but often than ever it will result in an overdesigned chip. This paper discusses a recipe to reduce pessimism in interconnect noise methodologies by effectively modeling the downstream degradation on the aggression line. We will be presenting an aggression slew estimation method derived from the Elmore delay, which has less than 0.8% error compared to SPICE simulations and is inclined towards the higher slew bound when compared to both Elmore's delay and SPICE. We also show that the dAP method reduces the average reported noise by 5% even when we account for victim-aggressor reverse aggression issues.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130914013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108692
J. Hun, B. Ngo, Chai Sian Han
For the Synchronous DC-DC converter switching performance of low-voltage power MOSFETs, the gate-drain charge density (Qgd) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (Ron.sp) and Qgd is commonly used to quantify the switching performance for a specified off-state breakdown voltage (BVds). Two approaches are taken to reduce the Ron.sp & Qgd. First is by shrinking the trench gate width to increase the cell densities up to 645Mcell/inch2 for an ultra low on state resistance using 0.18um design rule process. The other is to obtain lower Qgd with thick bottom oxide (TBO) at minimum trench gate width by double HDP processing. The results shows that the reduce Qgd 36%, total Qg[Vgs=10V] 27% and Qg uniformity around 7% within wafer.
{"title":"Minimum power loss for high-side power MOSFETs in DC-DC converter with TBO and high cell density","authors":"J. Hun, B. Ngo, Chai Sian Han","doi":"10.1109/ISIEA.2011.6108692","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108692","url":null,"abstract":"For the Synchronous DC-DC converter switching performance of low-voltage power MOSFETs, the gate-drain charge density (Qgd) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (Ron.sp) and Qgd is commonly used to quantify the switching performance for a specified off-state breakdown voltage (BVds). Two approaches are taken to reduce the Ron.sp & Qgd. First is by shrinking the trench gate width to increase the cell densities up to 645Mcell/inch2 for an ultra low on state resistance using 0.18um design rule process. The other is to obtain lower Qgd with thick bottom oxide (TBO) at minimum trench gate width by double HDP processing. The results shows that the reduce Qgd 36%, total Qg[Vgs=10V] 27% and Qg uniformity around 7% within wafer.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131474777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108762
Wei-Chih Chen, M. Cheng, T. Kuo, Cheng-Lin Li
Due to its attractive features such as high power density, long duration, high efficiency, the Brushless DC Motor (BLDCM) has gradually replaced the conventional brush DC motor and has been widely used in home appliances, office equipments, industrial applications and vehicles, etc. This paper proposes an intellectual property design of functions needed to implement a BLDCM drive, including the algorithms for commutation and control. The developed IP is verified by an Altera FPGA Board. In addition, the IP developed in this paper can be implemented as an Application Specific Integrated Circuit (ASIC) or embedded in SoC IC as a motor drive module. It is cost effective and requires shorter development time compared with the conventional microcontroller drive.
{"title":"Development of intellectual property for Brushless DC Motor drives","authors":"Wei-Chih Chen, M. Cheng, T. Kuo, Cheng-Lin Li","doi":"10.1109/ISIEA.2011.6108762","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108762","url":null,"abstract":"Due to its attractive features such as high power density, long duration, high efficiency, the Brushless DC Motor (BLDCM) has gradually replaced the conventional brush DC motor and has been widely used in home appliances, office equipments, industrial applications and vehicles, etc. This paper proposes an intellectual property design of functions needed to implement a BLDCM drive, including the algorithms for commutation and control. The developed IP is verified by an Altera FPGA Board. In addition, the IP developed in this paper can be implemented as an Application Specific Integrated Circuit (ASIC) or embedded in SoC IC as a motor drive module. It is cost effective and requires shorter development time compared with the conventional microcontroller drive.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131887964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108716
Kan Mei War, B. A. Rosdi, C. Wee
Incremental placement or Engineering Change Order (ECO) placement remains one of the most influential steps in Very Large Scale Integration (VLSI) layout design. New logic may be added into design after placement stage to meet functionality requirement. The added logic will cause design timing to become worse. In this paper, we develop an incremental placement Computer Aided Design (CAD) automation module to improve timing of the layout design. This incremental placement serves as a post-placement optimization solution that provide a cells position adjustment strategy such that no cells overlap occur and ensure no significant deviation from initial placement. Experiment is carried out by integrating the developed CAD automation module with standard industrial Electronic Design Automation (EDA) and Intel in-house design tools. Experimental results show that our approach can effectively reduce maximum and total negative slack on most of the benchmark circuits.
{"title":"CAD automation module based on cell moving algorithm for ECO timing optimization","authors":"Kan Mei War, B. A. Rosdi, C. Wee","doi":"10.1109/ISIEA.2011.6108716","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108716","url":null,"abstract":"Incremental placement or Engineering Change Order (ECO) placement remains one of the most influential steps in Very Large Scale Integration (VLSI) layout design. New logic may be added into design after placement stage to meet functionality requirement. The added logic will cause design timing to become worse. In this paper, we develop an incremental placement Computer Aided Design (CAD) automation module to improve timing of the layout design. This incremental placement serves as a post-placement optimization solution that provide a cells position adjustment strategy such that no cells overlap occur and ensure no significant deviation from initial placement. Experiment is carried out by integrating the developed CAD automation module with standard industrial Electronic Design Automation (EDA) and Intel in-house design tools. Experimental results show that our approach can effectively reduce maximum and total negative slack on most of the benchmark circuits.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132982017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108766
Arfah Marini Mohamad, N. Hashim, N. Hamzah, N. F. Nik Ismail, M. F. Abdul Latip
Transient stability analysis has become one of the major analyses in the power system to ensure the system stability to withstand a major disturbance. The effect of transient occurrence can lead to malfunction of electronic control equipment. Transient analysis can be conducted using simulation software package. One of the commercial simulation software package that used by industry worldwide is Siemens Power System Simulation for Engineering (PSS/E). This research paper highlights the usage of PSS/E to analyze Sarawak's Grid System stability using the simplest dynamic model that has been embedded into the program. To observe transient analysis using PSS/E, basic machine model such as generator, exciter and governor were used by varying default data in the program to find the best simulation output. This paper also analyzed the theory of critical clearing time (CCT) of fault occurrence between a transmission line near to the generator and far from the generator. CCT appears to be lesser when the fault occurs at a transmission line near to the generator. On the contrary, when fault occurs far from the generator, the duration of CCT is greater. The stability of the system is observed based on the machine rotor angle, machine speed, output electrical power and terminal voltage.
{"title":"Transient stability analysis on Sarawak's Grid using Power System Simulator for Engineering (PSS/E)","authors":"Arfah Marini Mohamad, N. Hashim, N. Hamzah, N. F. Nik Ismail, M. F. Abdul Latip","doi":"10.1109/ISIEA.2011.6108766","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108766","url":null,"abstract":"Transient stability analysis has become one of the major analyses in the power system to ensure the system stability to withstand a major disturbance. The effect of transient occurrence can lead to malfunction of electronic control equipment. Transient analysis can be conducted using simulation software package. One of the commercial simulation software package that used by industry worldwide is Siemens Power System Simulation for Engineering (PSS/E). This research paper highlights the usage of PSS/E to analyze Sarawak's Grid System stability using the simplest dynamic model that has been embedded into the program. To observe transient analysis using PSS/E, basic machine model such as generator, exciter and governor were used by varying default data in the program to find the best simulation output. This paper also analyzed the theory of critical clearing time (CCT) of fault occurrence between a transmission line near to the generator and far from the generator. CCT appears to be lesser when the fault occurs at a transmission line near to the generator. On the contrary, when fault occurs far from the generator, the duration of CCT is greater. The stability of the system is observed based on the machine rotor angle, machine speed, output electrical power and terminal voltage.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130758223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-22DOI: 10.1109/ISIEA.2011.6108721
N. Md Nor, A. Ibrahim, N. M. Bunnori, S. Shahidan, S. N. M. Saliah
Relationship between acoustic emission (AE) signal strength and damage evaluation has been reviewed. Several case studies have been referred to get information on that relationship. The notion or any opinion relates to the case study also had been discussed. Reviews of AE signal strength relate to damage evaluation of reinforced concrete structure and other materials are significantly useful for newly researchers.
{"title":"Relationship between acoustic emission signal strength and damage evaluation of reinforced concrete structure: Case studies","authors":"N. Md Nor, A. Ibrahim, N. M. Bunnori, S. Shahidan, S. N. M. Saliah","doi":"10.1109/ISIEA.2011.6108721","DOIUrl":"https://doi.org/10.1109/ISIEA.2011.6108721","url":null,"abstract":"Relationship between acoustic emission (AE) signal strength and damage evaluation has been reviewed. Several case studies have been referred to get information on that relationship. The notion or any opinion relates to the case study also had been discussed. Reviews of AE signal strength relate to damage evaluation of reinforced concrete structure and other materials are significantly useful for newly researchers.","PeriodicalId":110449,"journal":{"name":"2011 IEEE Symposium on Industrial Electronics and Applications","volume":"54 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116781531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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