Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606644
G. Yee, C. Sechen
A self-timed dynamic logic family, clock-delayed (CD) domino, was developed to provide non-dual-rail gates with inverting or non-inverting outputs. CD domino circuits are as easy to synthesize as static circuits and synthesis tools developed for static CMOS are used as part of a methodology for automating the design and synthesis of dynamic circuits. The methodology and CD domino's characteristics are demonstrated in the synthesis of five MCNC combinational logic benchmark circuits. Simulations of extracted chip layouts for the circuits show speed improvement factors of 2.17 to 6.28 compared to their static CMOS counterparts.
{"title":"Dynamic logic synthesis","authors":"G. Yee, C. Sechen","doi":"10.1109/CICC.1997.606644","DOIUrl":"https://doi.org/10.1109/CICC.1997.606644","url":null,"abstract":"A self-timed dynamic logic family, clock-delayed (CD) domino, was developed to provide non-dual-rail gates with inverting or non-inverting outputs. CD domino circuits are as easy to synthesize as static circuits and synthesis tools developed for static CMOS are used as part of a methodology for automating the design and synthesis of dynamic circuits. The methodology and CD domino's characteristics are demonstrated in the synthesis of five MCNC combinational logic benchmark circuits. Simulations of extracted chip layouts for the circuits show speed improvement factors of 2.17 to 6.28 compared to their static CMOS counterparts.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127797871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606688
D. Anderson, C. Marcjan, D. Bersch, H. Anderson, P. Hu, O. Palusinski, D. Gettman, I. Macbeth, A. Bratt
A Field Programmable Analog Array (FPAA) is presented based on switched capacitor technology. The architecture offers an unconstrained topology similar to its digital counterpart, containing an array of identical undedicated analog cells. This makes it possible to program both the functionality of each cell and the interconnect between cells. As a result a large number of diverse architectures may be implemented. The analog array can be programmed to perform many of the routine tasks associated with control systems design. Its linear and non-linear signal processing abilities can provide a wide range of waveform generation functions. The device can also be programmed for precise phase and magnitude characteristics. Some examples related to control systems are discussed.
{"title":"A field programmable analog array and its application","authors":"D. Anderson, C. Marcjan, D. Bersch, H. Anderson, P. Hu, O. Palusinski, D. Gettman, I. Macbeth, A. Bratt","doi":"10.1109/CICC.1997.606688","DOIUrl":"https://doi.org/10.1109/CICC.1997.606688","url":null,"abstract":"A Field Programmable Analog Array (FPAA) is presented based on switched capacitor technology. The architecture offers an unconstrained topology similar to its digital counterpart, containing an array of identical undedicated analog cells. This makes it possible to program both the functionality of each cell and the interconnect between cells. As a result a large number of diverse architectures may be implemented. The analog array can be programmed to perform many of the routine tasks associated with control systems design. Its linear and non-linear signal processing abilities can provide a wide range of waveform generation functions. The device can also be programmed for precise phase and magnitude characteristics. Some examples related to control systems are discussed.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126237949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606586
S. C. Munroe
The sampler is often the limitation in determining how early in the signal chain the conversion to discrete time can be done. We have fabricated a high-speed, wideband sampler based upon a charge-domain gated-gm cell that has a measured SFDR of 72 dB at 160 Ms/s and 320.25-MHz input frequency. This performance is achieved at 2% of the power and 4% of the area of a recently-released high-performance but slower sampler. Simulations indicate that far higher performance is possible in a more optimized circuit.
{"title":"2-/spl mu/m, 1.6-mW gated-g/sub m/ sampler with 72 dB SFDR at 160 Ms/s and 320.25-MHz f/sub in/","authors":"S. C. Munroe","doi":"10.1109/CICC.1997.606586","DOIUrl":"https://doi.org/10.1109/CICC.1997.606586","url":null,"abstract":"The sampler is often the limitation in determining how early in the signal chain the conversion to discrete time can be done. We have fabricated a high-speed, wideband sampler based upon a charge-domain gated-gm cell that has a measured SFDR of 72 dB at 160 Ms/s and 320.25-MHz input frequency. This performance is achieved at 2% of the power and 4% of the area of a recently-released high-performance but slower sampler. Simulations indicate that far higher performance is possible in a more optimized circuit.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116943680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606646
T. Gabara, J. Harrington, R. Yan
BERT measurements have been used to characterize the digital receiver sensitivity during asynchronous ground bounce events and provide a reference point to establish a guideline for ground bounce criteria. Simultaneously switched digitally controlled output buffers improve the signal integrity of receivers over seven orders of magnitude when compared to conventional buffers. An algorithm with strong support of measurements has been used to develop a graphical approach to predicting the required power lead count of a packaged CMOS device.
{"title":"Universal guideline for CMOS I/O signal integrity","authors":"T. Gabara, J. Harrington, R. Yan","doi":"10.1109/CICC.1997.606646","DOIUrl":"https://doi.org/10.1109/CICC.1997.606646","url":null,"abstract":"BERT measurements have been used to characterize the digital receiver sensitivity during asynchronous ground bounce events and provide a reference point to establish a guideline for ground bounce criteria. Simultaneously switched digitally controlled output buffers improve the signal integrity of receivers over seven orders of magnitude when compared to conventional buffers. An algorithm with strong support of measurements has been used to develop a graphical approach to predicting the required power lead count of a packaged CMOS device.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122679592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606614
T. Almy
IEEE 1149.1 Boundary-Scan has traditionally been used for continuity and low speed functional testing of integrated circuits. The boundary-scan RUNBIST instruction allows Built-In Self Test for functional testing at full clock speeds. This paper describes an approach that uses the RUNBIST instruction to make timing measurements with a resolution 32 times smaller than the clock period while doing at-speed testing. Measurement commands and results are transmitted via boundary-scan.
{"title":"Making precise at-speed timing measurements via boundary-scan","authors":"T. Almy","doi":"10.1109/CICC.1997.606614","DOIUrl":"https://doi.org/10.1109/CICC.1997.606614","url":null,"abstract":"IEEE 1149.1 Boundary-Scan has traditionally been used for continuity and low speed functional testing of integrated circuits. The boundary-scan RUNBIST instruction allows Built-In Self Test for functional testing at full clock speeds. This paper describes an approach that uses the RUNBIST instruction to make timing measurements with a resolution 32 times smaller than the clock period while doing at-speed testing. Measurement commands and results are transmitted via boundary-scan.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124067240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606595
L. Cooke
VSIA is a new organization with a mission to develop specifications for the creation and integration of Virtual Chips, functional subsystems used in System ASICs. It is made up of EDA, semiconductor, IP development, and System companies. This paper describes the advantages and implications of VSIA from these four perspectives.
{"title":"VSIA: it's advantages from four different perspectives","authors":"L. Cooke","doi":"10.1109/CICC.1997.606595","DOIUrl":"https://doi.org/10.1109/CICC.1997.606595","url":null,"abstract":"VSIA is a new organization with a mission to develop specifications for the creation and integration of Virtual Chips, functional subsystems used in System ASICs. It is made up of EDA, semiconductor, IP development, and System companies. This paper describes the advantages and implications of VSIA from these four perspectives.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124830681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606580
P. Gilbert, P. Tsui, Shih-Wei Sun, S. Jamison, J. Miller
Optimization of a sub-0.5 /spl mu/m ESD protection circuit using halo implant is described. A p-type halo implant significantly improves the ESD robustness of a high performance I/O circuit as noted by Human Body Model (HBM) test results. The improved ESD performance is directly attributed to the ability of the halo implanted Thick Field Oxide (TFO) device to inhibit the turn-on of the n-channel output buffer during an ESD event. Improved ESD performance is achieved without the use of additional series resistance and with no increase in device area. The results represent the first time transmission-line pulse generator (TLPG) analysis has been used on a fully synthesized I/O circuit to predict wafer level ESD performance.
{"title":"Performance improvement of a thick field oxide ESD protection circuit by halo implant","authors":"P. Gilbert, P. Tsui, Shih-Wei Sun, S. Jamison, J. Miller","doi":"10.1109/CICC.1997.606580","DOIUrl":"https://doi.org/10.1109/CICC.1997.606580","url":null,"abstract":"Optimization of a sub-0.5 /spl mu/m ESD protection circuit using halo implant is described. A p-type halo implant significantly improves the ESD robustness of a high performance I/O circuit as noted by Human Body Model (HBM) test results. The improved ESD performance is directly attributed to the ability of the halo implanted Thick Field Oxide (TFO) device to inhibit the turn-on of the n-channel output buffer during an ESD event. Improved ESD performance is achieved without the use of additional series resistance and with no increase in device area. The results represent the first time transmission-line pulse generator (TLPG) analysis has been used on a fully synthesized I/O circuit to predict wafer level ESD performance.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131132493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606642
P. Diodato, J. Clemens, W. Troutman, W. S. Lindenberger
A charged based analysis is used to compare three DRAM cells embedded in a 0.25 /spl mu/m ASIC environment. Critical charge, bit-line response, and sense amplifier sensitivity are calculated. Wafer probe measurements are shown that demonstrate milli-second hold times and explanations presented in support of using multi-transistor DRAM cells for the vast majority of high performance embedded ASIC applications.
{"title":"A reusable embedded DRAM macrocell","authors":"P. Diodato, J. Clemens, W. Troutman, W. S. Lindenberger","doi":"10.1109/CICC.1997.606642","DOIUrl":"https://doi.org/10.1109/CICC.1997.606642","url":null,"abstract":"A charged based analysis is used to compare three DRAM cells embedded in a 0.25 /spl mu/m ASIC environment. Critical charge, bit-line response, and sense amplifier sensitivity are calculated. Wafer probe measurements are shown that demonstrate milli-second hold times and explanations presented in support of using multi-transistor DRAM cells for the vast majority of high performance embedded ASIC applications.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131777782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606610
K. Fong, R. Meyer
A class AB downconversion mixer for 2.4 GHz wireless LAN applications is presented. The circuit is implemented in a 13 GHz f/sub T/ BiCMOS process, and consumes 7.9 mA total current from a 3 V supply. A single-balanced design using bond-wire degeneration in the common-emitter driver stage is optimal for power consumption and noise figure. The design has a power gain of 4.5 dB, a single-side band noise figure of 10 dB, an input third-order intercept point of 1 dBm, and an input 1 dB compression point of -7.5 dBm.
{"title":"A 2.4 GHz monolithic mixer for wireless LAN applications","authors":"K. Fong, R. Meyer","doi":"10.1109/CICC.1997.606610","DOIUrl":"https://doi.org/10.1109/CICC.1997.606610","url":null,"abstract":"A class AB downconversion mixer for 2.4 GHz wireless LAN applications is presented. The circuit is implemented in a 13 GHz f/sub T/ BiCMOS process, and consumes 7.9 mA total current from a 3 V supply. A single-balanced design using bond-wire degeneration in the common-emitter driver stage is optimal for power consumption and noise figure. The design has a power gain of 4.5 dB, a single-side band noise figure of 10 dB, an input third-order intercept point of 1 dBm, and an input 1 dB compression point of -7.5 dBm.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132442810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606694
K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Kuroda
A 300 MIPS/W RISC core processor with variable supply-voltage (VS) scheme in variable threshold-voltage CMOS (VTCMOS) is presented. Performance in MIPS/W can be improved by a factor of more than two with no modification in the RISC core except for substrate contacts for the VTCMOS. From a 3.3 V external power supply the VS scheme automatically generates minimum internal supply voltages which meet the demand on its operation frequency.
{"title":"A 300 MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS","authors":"K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Kuroda","doi":"10.1109/CICC.1997.606694","DOIUrl":"https://doi.org/10.1109/CICC.1997.606694","url":null,"abstract":"A 300 MIPS/W RISC core processor with variable supply-voltage (VS) scheme in variable threshold-voltage CMOS (VTCMOS) is presented. Performance in MIPS/W can be improved by a factor of more than two with no modification in the RISC core except for substrate contacts for the VTCMOS. From a 3.3 V external power supply the VS scheme automatically generates minimum internal supply voltages which meet the demand on its operation frequency.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133363716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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