Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606644
G. Yee, C. Sechen
A self-timed dynamic logic family, clock-delayed (CD) domino, was developed to provide non-dual-rail gates with inverting or non-inverting outputs. CD domino circuits are as easy to synthesize as static circuits and synthesis tools developed for static CMOS are used as part of a methodology for automating the design and synthesis of dynamic circuits. The methodology and CD domino's characteristics are demonstrated in the synthesis of five MCNC combinational logic benchmark circuits. Simulations of extracted chip layouts for the circuits show speed improvement factors of 2.17 to 6.28 compared to their static CMOS counterparts.
{"title":"Dynamic logic synthesis","authors":"G. Yee, C. Sechen","doi":"10.1109/CICC.1997.606644","DOIUrl":"https://doi.org/10.1109/CICC.1997.606644","url":null,"abstract":"A self-timed dynamic logic family, clock-delayed (CD) domino, was developed to provide non-dual-rail gates with inverting or non-inverting outputs. CD domino circuits are as easy to synthesize as static circuits and synthesis tools developed for static CMOS are used as part of a methodology for automating the design and synthesis of dynamic circuits. The methodology and CD domino's characteristics are demonstrated in the synthesis of five MCNC combinational logic benchmark circuits. Simulations of extracted chip layouts for the circuits show speed improvement factors of 2.17 to 6.28 compared to their static CMOS counterparts.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127797871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606685
S. Singh, B. Britton, C. Spivak, H. Nguyen, W. Leung, B. Andrews, G. Powell, R. Albu, J. He, R. Stuby, M. Chin, Pin-Lin Chiu, J. Steward, Doug Rabold
This paper describes a new ORCA FPGA that focuses on enhancing the speed and gate density of logic systems implemented using high-level logic synthesis. The new family called ORCA 3C/3T, follows the successful ORCA families: 1C, 2C, 2CA and 2TA. The architecture has been designed for efficiently implementing behavioral-level "functions", in addition to regular digital "logic". It includes Look-Up Tables (LUTs), Flip-Flops (FFs) and a PAL-type decoder block grouped in a twin-nibble fashion. The programmable interconnections are designed to provide fast hierarchical connections. To meet the challenge of implementing larger systems, the architecture supports system-level features such as a Programmable Clock Manager (PCM) and a microprocessor interface that can be used during and after the configuration.
{"title":"A new synthesis efficient, high density and high speed ORCA FPGA","authors":"S. Singh, B. Britton, C. Spivak, H. Nguyen, W. Leung, B. Andrews, G. Powell, R. Albu, J. He, R. Stuby, M. Chin, Pin-Lin Chiu, J. Steward, Doug Rabold","doi":"10.1109/CICC.1997.606685","DOIUrl":"https://doi.org/10.1109/CICC.1997.606685","url":null,"abstract":"This paper describes a new ORCA FPGA that focuses on enhancing the speed and gate density of logic systems implemented using high-level logic synthesis. The new family called ORCA 3C/3T, follows the successful ORCA families: 1C, 2C, 2CA and 2TA. The architecture has been designed for efficiently implementing behavioral-level \"functions\", in addition to regular digital \"logic\". It includes Look-Up Tables (LUTs), Flip-Flops (FFs) and a PAL-type decoder block grouped in a twin-nibble fashion. The programmable interconnections are designed to provide fast hierarchical connections. To meet the challenge of implementing larger systems, the architecture supports system-level features such as a Programmable Clock Manager (PCM) and a microprocessor interface that can be used during and after the configuration.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132903440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606653
Behzad Razavi
This paper describes the challenges in the design of frequency synthesizers used in wireless transceivers. Following a review of design issues and the effect of nonidealities, we present a number of synthesizer architectures along with their merits and drawbacks. We also describe the difficulties in the design of some of the building blocks and consider the role of synthesizers in emerging applications.
{"title":"Challenges in the design of frequency synthesizers for wireless applications","authors":"Behzad Razavi","doi":"10.1109/CICC.1997.606653","DOIUrl":"https://doi.org/10.1109/CICC.1997.606653","url":null,"abstract":"This paper describes the challenges in the design of frequency synthesizers used in wireless transceivers. Following a review of design issues and the effect of nonidealities, we present a number of synthesizer architectures along with their merits and drawbacks. We also describe the difficulties in the design of some of the building blocks and consider the role of synthesizers in emerging applications.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124673857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606595
L. Cooke
VSIA is a new organization with a mission to develop specifications for the creation and integration of Virtual Chips, functional subsystems used in System ASICs. It is made up of EDA, semiconductor, IP development, and System companies. This paper describes the advantages and implications of VSIA from these four perspectives.
{"title":"VSIA: it's advantages from four different perspectives","authors":"L. Cooke","doi":"10.1109/CICC.1997.606595","DOIUrl":"https://doi.org/10.1109/CICC.1997.606595","url":null,"abstract":"VSIA is a new organization with a mission to develop specifications for the creation and integration of Virtual Chips, functional subsystems used in System ASICs. It is made up of EDA, semiconductor, IP development, and System companies. This paper describes the advantages and implications of VSIA from these four perspectives.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124830681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606622
S. Li, J. Rowlands, P. Ng, M. Gill, D.S. Youm, D. Kam, S. Song, P. Look
The emerging digital audio compression technology brings both an opportunity and a new challenge to IC design. High quality multichannel audio is quickly becoming an indispensable part of an entertainment system. The algorithms used in the compression technology result in complex VLSI ICs. The work presented in this paper is about the design of a dedicated, high precision, and low cost AC3/MPEG multi-standard audio decoder. The audio IC's hardware and software architecture, as well as design and simulation/verification methodology are discussed in detail.
{"title":"An AC-3/MPEG multi-standard audio decoder IC","authors":"S. Li, J. Rowlands, P. Ng, M. Gill, D.S. Youm, D. Kam, S. Song, P. Look","doi":"10.1109/CICC.1997.606622","DOIUrl":"https://doi.org/10.1109/CICC.1997.606622","url":null,"abstract":"The emerging digital audio compression technology brings both an opportunity and a new challenge to IC design. High quality multichannel audio is quickly becoming an indispensable part of an entertainment system. The algorithms used in the compression technology result in complex VLSI ICs. The work presented in this paper is about the design of a dedicated, high precision, and low cost AC3/MPEG multi-standard audio decoder. The audio IC's hardware and software architecture, as well as design and simulation/verification methodology are discussed in detail.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126692676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606614
T. Almy
IEEE 1149.1 Boundary-Scan has traditionally been used for continuity and low speed functional testing of integrated circuits. The boundary-scan RUNBIST instruction allows Built-In Self Test for functional testing at full clock speeds. This paper describes an approach that uses the RUNBIST instruction to make timing measurements with a resolution 32 times smaller than the clock period while doing at-speed testing. Measurement commands and results are transmitted via boundary-scan.
{"title":"Making precise at-speed timing measurements via boundary-scan","authors":"T. Almy","doi":"10.1109/CICC.1997.606614","DOIUrl":"https://doi.org/10.1109/CICC.1997.606614","url":null,"abstract":"IEEE 1149.1 Boundary-Scan has traditionally been used for continuity and low speed functional testing of integrated circuits. The boundary-scan RUNBIST instruction allows Built-In Self Test for functional testing at full clock speeds. This paper describes an approach that uses the RUNBIST instruction to make timing measurements with a resolution 32 times smaller than the clock period while doing at-speed testing. Measurement commands and results are transmitted via boundary-scan.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124067240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606646
T. Gabara, J. Harrington, R. Yan
BERT measurements have been used to characterize the digital receiver sensitivity during asynchronous ground bounce events and provide a reference point to establish a guideline for ground bounce criteria. Simultaneously switched digitally controlled output buffers improve the signal integrity of receivers over seven orders of magnitude when compared to conventional buffers. An algorithm with strong support of measurements has been used to develop a graphical approach to predicting the required power lead count of a packaged CMOS device.
{"title":"Universal guideline for CMOS I/O signal integrity","authors":"T. Gabara, J. Harrington, R. Yan","doi":"10.1109/CICC.1997.606646","DOIUrl":"https://doi.org/10.1109/CICC.1997.606646","url":null,"abstract":"BERT measurements have been used to characterize the digital receiver sensitivity during asynchronous ground bounce events and provide a reference point to establish a guideline for ground bounce criteria. Simultaneously switched digitally controlled output buffers improve the signal integrity of receivers over seven orders of magnitude when compared to conventional buffers. An algorithm with strong support of measurements has been used to develop a graphical approach to predicting the required power lead count of a packaged CMOS device.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122679592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606608
H. Ainspan, M. Soyuer, J. Plouchart, J. Burghartz
A 6.25-GHz monolithic low-noise amplifier (LNA) with a minimum noise figure of 2.2 dB and an associated gain of 20.4 dB implemented in a standard SiGe bipolar technology is presented. The 50-ohm noise figure is 3.5 dB with S21 of 18.3 dB. The circuit dissipates 9.4 mW from a 2.5-V supply (6.4 mW in the gain stages). The LNA's figure of merit gain/(P/sub DC//spl times/NF) of 0.56 mW/sup -1/ exceeds those of recently published 5 to 6 GHz GaAs MESFET and HBT LNA's.
{"title":"A 6.25-GHz low DC power low-noise amplifier in SiGe","authors":"H. Ainspan, M. Soyuer, J. Plouchart, J. Burghartz","doi":"10.1109/CICC.1997.606608","DOIUrl":"https://doi.org/10.1109/CICC.1997.606608","url":null,"abstract":"A 6.25-GHz monolithic low-noise amplifier (LNA) with a minimum noise figure of 2.2 dB and an associated gain of 20.4 dB implemented in a standard SiGe bipolar technology is presented. The 50-ohm noise figure is 3.5 dB with S21 of 18.3 dB. The circuit dissipates 9.4 mW from a 2.5-V supply (6.4 mW in the gain stages). The LNA's figure of merit gain/(P/sub DC//spl times/NF) of 0.56 mW/sup -1/ exceeds those of recently published 5 to 6 GHz GaAs MESFET and HBT LNA's.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115048096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606586
S. C. Munroe
The sampler is often the limitation in determining how early in the signal chain the conversion to discrete time can be done. We have fabricated a high-speed, wideband sampler based upon a charge-domain gated-gm cell that has a measured SFDR of 72 dB at 160 Ms/s and 320.25-MHz input frequency. This performance is achieved at 2% of the power and 4% of the area of a recently-released high-performance but slower sampler. Simulations indicate that far higher performance is possible in a more optimized circuit.
{"title":"2-/spl mu/m, 1.6-mW gated-g/sub m/ sampler with 72 dB SFDR at 160 Ms/s and 320.25-MHz f/sub in/","authors":"S. C. Munroe","doi":"10.1109/CICC.1997.606586","DOIUrl":"https://doi.org/10.1109/CICC.1997.606586","url":null,"abstract":"The sampler is often the limitation in determining how early in the signal chain the conversion to discrete time can be done. We have fabricated a high-speed, wideband sampler based upon a charge-domain gated-gm cell that has a measured SFDR of 72 dB at 160 Ms/s and 320.25-MHz input frequency. This performance is achieved at 2% of the power and 4% of the area of a recently-released high-performance but slower sampler. Simulations indicate that far higher performance is possible in a more optimized circuit.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116943680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606610
K. Fong, R. Meyer
A class AB downconversion mixer for 2.4 GHz wireless LAN applications is presented. The circuit is implemented in a 13 GHz f/sub T/ BiCMOS process, and consumes 7.9 mA total current from a 3 V supply. A single-balanced design using bond-wire degeneration in the common-emitter driver stage is optimal for power consumption and noise figure. The design has a power gain of 4.5 dB, a single-side band noise figure of 10 dB, an input third-order intercept point of 1 dBm, and an input 1 dB compression point of -7.5 dBm.
{"title":"A 2.4 GHz monolithic mixer for wireless LAN applications","authors":"K. Fong, R. Meyer","doi":"10.1109/CICC.1997.606610","DOIUrl":"https://doi.org/10.1109/CICC.1997.606610","url":null,"abstract":"A class AB downconversion mixer for 2.4 GHz wireless LAN applications is presented. The circuit is implemented in a 13 GHz f/sub T/ BiCMOS process, and consumes 7.9 mA total current from a 3 V supply. A single-balanced design using bond-wire degeneration in the common-emitter driver stage is optimal for power consumption and noise figure. The design has a power gain of 4.5 dB, a single-side band noise figure of 10 dB, an input third-order intercept point of 1 dBm, and an input 1 dB compression point of -7.5 dBm.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132442810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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