Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606618
Koji Miyanohana, G. Fujita, K. Yanagida, T. Onoye, I. Shirakawa
A single chip encoder and decoder dedicated to the low bitrate visual communication is described, with the main theme focused on the object extraction and vector quantization. A new scheme is devised for a detailed edge detector, which is to seek horizontal and vertical edges simultaneously. A new concept is also introduced into a PE (Processing Element) array so as to be commonly used by the vector quantizer and the motion estimator. Owing to a sophisticated architecture, these CODEC facilities have been implemented in 72.24 mm/sup 2/ by a 0.6 /spl mu/m triple-metal CMOS technology, which can enable the visual communication of QCIF (176/spl times/144) 10 fps pictures at a bitrate below 30 K bps. The designed encoder and decoder operate at 10.0 MHz, and dissipate 147 mW from a single 3.3 V supply.
{"title":"VLSI implementation of single chip encoder/decoder for low bitrate visual communication","authors":"Koji Miyanohana, G. Fujita, K. Yanagida, T. Onoye, I. Shirakawa","doi":"10.1109/CICC.1997.606618","DOIUrl":"https://doi.org/10.1109/CICC.1997.606618","url":null,"abstract":"A single chip encoder and decoder dedicated to the low bitrate visual communication is described, with the main theme focused on the object extraction and vector quantization. A new scheme is devised for a detailed edge detector, which is to seek horizontal and vertical edges simultaneously. A new concept is also introduced into a PE (Processing Element) array so as to be commonly used by the vector quantizer and the motion estimator. Owing to a sophisticated architecture, these CODEC facilities have been implemented in 72.24 mm/sup 2/ by a 0.6 /spl mu/m triple-metal CMOS technology, which can enable the visual communication of QCIF (176/spl times/144) 10 fps pictures at a bitrate below 30 K bps. The designed encoder and decoder operate at 10.0 MHz, and dissipate 147 mW from a single 3.3 V supply.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124063628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606680
M. Banu, H. Wang, M. Seidel, M. Tarsia, W. Fischer, J. Glas, A. Dec, V. Boccuzzi
A new down-conversion technique for wireless terminals is proposed. The use of two IF stages at low frequencies eliminates the need for expensive SAW filters while avoiding some of the shortcomings of the direct conversion and single low-IF methods. High selectivity is realized with on-chip filters and inexpensive ceramic filters. A 0.5 /spl mu/m BiCMOS test chip demonstrates the principle via a GSM example.
{"title":"A BiCMOS double-low-IF receiver for GSM","authors":"M. Banu, H. Wang, M. Seidel, M. Tarsia, W. Fischer, J. Glas, A. Dec, V. Boccuzzi","doi":"10.1109/CICC.1997.606680","DOIUrl":"https://doi.org/10.1109/CICC.1997.606680","url":null,"abstract":"A new down-conversion technique for wireless terminals is proposed. The use of two IF stages at low frequencies eliminates the need for expensive SAW filters while avoiding some of the shortcomings of the direct conversion and single low-IF methods. High selectivity is realized with on-chip filters and inexpensive ceramic filters. A 0.5 /spl mu/m BiCMOS test chip demonstrates the principle via a GSM example.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115734886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606657
D. Binkley, J. M. Rochelle, B. K. Swann, L. Clonts, R. N. Goble
A micropower CMOS, direct-conversion VLF receiver is described for receiving low-level magnetic fields from resonant sensors. The single-chip, PLL-synthesized receiver covers a frequency range of 10-100 kHz and provides both analog and digital 9-bit I and Q baseband outputs. Lateral bipolar transistors are utilized for low flicker noise and low DC offsets, and special attention is given to isolating the internal local oscillator signals from the low-level RF input (0.3 /spl mu/V noise floor, 300 Hz BW). The 100% duty-cycle receiver, intended for long-battery life wireless applications, operates at 360 /spl mu/W from a 6-V battery.
{"title":"A micropower CMOS, direct-conversion, VLF receiver chip for magnetic-field wireless applications","authors":"D. Binkley, J. M. Rochelle, B. K. Swann, L. Clonts, R. N. Goble","doi":"10.1109/CICC.1997.606657","DOIUrl":"https://doi.org/10.1109/CICC.1997.606657","url":null,"abstract":"A micropower CMOS, direct-conversion VLF receiver is described for receiving low-level magnetic fields from resonant sensors. The single-chip, PLL-synthesized receiver covers a frequency range of 10-100 kHz and provides both analog and digital 9-bit I and Q baseband outputs. Lateral bipolar transistors are utilized for low flicker noise and low DC offsets, and special attention is given to isolating the internal local oscillator signals from the low-level RF input (0.3 /spl mu/V noise floor, 300 Hz BW). The 100% duty-cycle receiver, intended for long-battery life wireless applications, operates at 360 /spl mu/W from a 6-V battery.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114636269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606666
N. Weste, M. Bickerstaff, T. Arivoli, P. Ryan, J. Dalton, D. Skellern, T. Percival
This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 /spl mu/m TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.
{"title":"A 50 MHz 16-point FFT processor for WLAN applications","authors":"N. Weste, M. Bickerstaff, T. Arivoli, P. Ryan, J. Dalton, D. Skellern, T. Percival","doi":"10.1109/CICC.1997.606666","DOIUrl":"https://doi.org/10.1109/CICC.1997.606666","url":null,"abstract":"This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 /spl mu/m TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"37 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121008816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606667
B. Gyselinckx, L. Rynders, M. Engels, I. Bolsens
This paper reports on a direct sequence spread spectrum (DSSS) ASIC, which integrates all the digital functions of an L-band satellite pager. The ASIC performs digital IQ-downconversion of a carrier up to 10 MHz running from a 40 MHz clock. The maximum chip rate is 4*2.5 Mchip/s. The receiver integrates an ARM6 core, memory, a UART, and flexible DSP hardware. Therefore, it is fully programmable. The use of macrocells and a self timed architecture allowed the design to have an aggressive design time of 7 months from specification to silicon. A low power redesign of the on-chip downconverter and decimator resulted in 45% power savings.
{"title":"A 4*2.5 Mchip/s direct sequence spread spectrum receiver with digital IF and integrated ARM6 core","authors":"B. Gyselinckx, L. Rynders, M. Engels, I. Bolsens","doi":"10.1109/CICC.1997.606667","DOIUrl":"https://doi.org/10.1109/CICC.1997.606667","url":null,"abstract":"This paper reports on a direct sequence spread spectrum (DSSS) ASIC, which integrates all the digital functions of an L-band satellite pager. The ASIC performs digital IQ-downconversion of a carrier up to 10 MHz running from a 40 MHz clock. The maximum chip rate is 4*2.5 Mchip/s. The receiver integrates an ARM6 core, memory, a UART, and flexible DSP hardware. Therefore, it is fully programmable. The use of macrocells and a self timed architecture allowed the design to have an aggressive design time of 7 months from specification to silicon. A low power redesign of the on-chip downconverter and decimator resulted in 45% power savings.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122365945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606628
Y. Nakase, H. Kono, T. Tokuda
This paper describes a dual port cursor RAM operating in real time. Cursor RAMs have been composed of two memory planes. The pixel port requires data from both planes at the same time. However, this has not been realized so far because each port defines its address space differently. A dynamic data alignment architecture coordinates these different requests. This architecture reduces a large amount of control circuits and makes it possible to operate in real time. The RAM is fabricated in a double metal 0.5 /spl mu/m CMOS process technology. The active area is 1.5/spl times/1.6 mm including a couple of shift registers. It operates up to 263 MHz at the supply voltage of 3.3 V.
本文介绍了一种实时工作的双端口游标RAM。游标ram由两个存储平面组成。像素端口需要同时从两个平面获取数据。但是，到目前为止还没有实现这一点，因为每个端口对其地址空间的定义不同。动态数据对齐体系结构协调这些不同的请求。这种结构减少了大量的控制电路，使实时操作成为可能。该RAM采用双金属0.5 /spl μ m CMOS工艺技术制造。活动区域为1.5/spl倍/1.6毫米，包括一对移位寄存器。它在3.3 V的电源电压下工作到263mhz。
{"title":"A 250 MHz dual port cursor RAM using dynamic data alignment architecture","authors":"Y. Nakase, H. Kono, T. Tokuda","doi":"10.1109/CICC.1997.606628","DOIUrl":"https://doi.org/10.1109/CICC.1997.606628","url":null,"abstract":"This paper describes a dual port cursor RAM operating in real time. Cursor RAMs have been composed of two memory planes. The pixel port requires data from both planes at the same time. However, this has not been realized so far because each port defines its address space differently. A dynamic data alignment architecture coordinates these different requests. This architecture reduces a large amount of control circuits and makes it possible to operate in real time. The RAM is fabricated in a double metal 0.5 /spl mu/m CMOS process technology. The active area is 1.5/spl times/1.6 mm including a couple of shift registers. It operates up to 263 MHz at the supply voltage of 3.3 V.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126911731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606689
E. Malavasi, J. L. Ganley, E. Charbon
In this paper an original constraint-driven placement tool targeted at full-custom mixed-signal design is described. One of its main objectives is to quickly obtain feasible layout configurations, and explore efficiently the effect of different sets of constraints in an interactive environment. By using direct-approach algorithms, all feasible constraints are met by construction. Overconstraints are detected, and quick feedback is given to the user about infeasible requirements. Good results have been obtained on a significant set of industrial-strength test cases.
{"title":"Quick placement with geometric constraints","authors":"E. Malavasi, J. L. Ganley, E. Charbon","doi":"10.1109/CICC.1997.606689","DOIUrl":"https://doi.org/10.1109/CICC.1997.606689","url":null,"abstract":"In this paper an original constraint-driven placement tool targeted at full-custom mixed-signal design is described. One of its main objectives is to quickly obtain feasible layout configurations, and explore efficiently the effect of different sets of constraints in an interactive environment. By using direct-approach algorithms, all feasible constraints are met by construction. Overconstraints are detected, and quick feedback is given to the user about infeasible requirements. Good results have been obtained on a significant set of industrial-strength test cases.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127071005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606685
S. Singh, B. Britton, C. Spivak, H. Nguyen, W. Leung, B. Andrews, G. Powell, R. Albu, J. He, R. Stuby, M. Chin, Pin-Lin Chiu, J. Steward, Doug Rabold
This paper describes a new ORCA FPGA that focuses on enhancing the speed and gate density of logic systems implemented using high-level logic synthesis. The new family called ORCA 3C/3T, follows the successful ORCA families: 1C, 2C, 2CA and 2TA. The architecture has been designed for efficiently implementing behavioral-level "functions", in addition to regular digital "logic". It includes Look-Up Tables (LUTs), Flip-Flops (FFs) and a PAL-type decoder block grouped in a twin-nibble fashion. The programmable interconnections are designed to provide fast hierarchical connections. To meet the challenge of implementing larger systems, the architecture supports system-level features such as a Programmable Clock Manager (PCM) and a microprocessor interface that can be used during and after the configuration.
{"title":"A new synthesis efficient, high density and high speed ORCA FPGA","authors":"S. Singh, B. Britton, C. Spivak, H. Nguyen, W. Leung, B. Andrews, G. Powell, R. Albu, J. He, R. Stuby, M. Chin, Pin-Lin Chiu, J. Steward, Doug Rabold","doi":"10.1109/CICC.1997.606685","DOIUrl":"https://doi.org/10.1109/CICC.1997.606685","url":null,"abstract":"This paper describes a new ORCA FPGA that focuses on enhancing the speed and gate density of logic systems implemented using high-level logic synthesis. The new family called ORCA 3C/3T, follows the successful ORCA families: 1C, 2C, 2CA and 2TA. The architecture has been designed for efficiently implementing behavioral-level \"functions\", in addition to regular digital \"logic\". It includes Look-Up Tables (LUTs), Flip-Flops (FFs) and a PAL-type decoder block grouped in a twin-nibble fashion. The programmable interconnections are designed to provide fast hierarchical connections. To meet the challenge of implementing larger systems, the architecture supports system-level features such as a Programmable Clock Manager (PCM) and a microprocessor interface that can be used during and after the configuration.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132903440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606697
N. Tan
For telecommunication applications, the dynamic performance of a digital-to-analog converter such as intermodulation and spurious-free dynamic range is of the greatest importance and the static performance is of minor concern. This paper presents the design of a 1.5 V 10-bit CMOS digital-to-analog converter in a 0.6 /spl mu/m digital CMOS process for telecommunication applications. It features an intermodulation level less than -60 dBc at 10 Ms/s and -55 dBc at 50 Ms/s, and a spurious-free dynamic range of 59 dB at 10 Ms/s and 48 dB at 50 Ms/s. The power dissipation is about 1.5 mW at 10 Ms/s and about 3 mW at 50 Ms/s.
{"title":"A 1.5-V 3-mW 10-bit 50-Ms/s CMOS DAC with low distortion and low intermodulation in standard digital CMOS process","authors":"N. Tan","doi":"10.1109/CICC.1997.606697","DOIUrl":"https://doi.org/10.1109/CICC.1997.606697","url":null,"abstract":"For telecommunication applications, the dynamic performance of a digital-to-analog converter such as intermodulation and spurious-free dynamic range is of the greatest importance and the static performance is of minor concern. This paper presents the design of a 1.5 V 10-bit CMOS digital-to-analog converter in a 0.6 /spl mu/m digital CMOS process for telecommunication applications. It features an intermodulation level less than -60 dBc at 10 Ms/s and -55 dBc at 50 Ms/s, and a spurious-free dynamic range of 59 dB at 10 Ms/s and 48 dB at 50 Ms/s. The power dissipation is about 1.5 mW at 10 Ms/s and about 3 mW at 50 Ms/s.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129095520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606672
M. Nemani, Farid N. Najm
High-level power estimation, when given only a high level design specification such as a functional or RTL description, requires high-level estimation of the circuit average activity and total capacitance. Considering that total capacitance is related to circuit area, this paper addresses the problem of computing the area complexity of single-output Boolean functions given only their functional description, where area complexity is measured in terms of the number of gates required for an optimal implementation of the function. We propose an area model that makes use of a new complexity measure. The model is empirical, and is based on an observed relationship between the proposed complexity measure, which is easily measurable using Monte-Carlo simulation, and its optimal implementation (gate-count). This model has been implemented, and empirical results demonstrating its feasibility and utility are presented.
{"title":"High-level area prediction for power estimation","authors":"M. Nemani, Farid N. Najm","doi":"10.1109/CICC.1997.606672","DOIUrl":"https://doi.org/10.1109/CICC.1997.606672","url":null,"abstract":"High-level power estimation, when given only a high level design specification such as a functional or RTL description, requires high-level estimation of the circuit average activity and total capacitance. Considering that total capacitance is related to circuit area, this paper addresses the problem of computing the area complexity of single-output Boolean functions given only their functional description, where area complexity is measured in terms of the number of gates required for an optimal implementation of the function. We propose an area model that makes use of a new complexity measure. The model is empirical, and is based on an observed relationship between the proposed complexity measure, which is easily measurable using Monte-Carlo simulation, and its optimal implementation (gate-count). This model has been implemented, and empirical results demonstrating its feasibility and utility are presented.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127544179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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