Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606679
M. Borremans, M. Steyaert
This paper describes a 2 V full CMOS 1 GHz upconversion mixer. The circuit has a single-ended output which avoids the use of any balun. The total power consumption in both the mixer and the output stage is only 22 mW. The signal to distortion ratio has been measured to be more than 30 dB. A thorough analysis of the harmonics caused by the nonlinearity of the mixer transistors is performed. The theory is confirmed by the measurements on the presented circuit. The chip has been processed in 0.4 /spl mu/m CMOS technology.
本文介绍了一种2v全CMOS 1ghz上变频混频器。该电路有一个单端输出，避免使用任何平衡器。混合器和输出级的总功耗仅为22 mW。经测量，其信失真比可达30db以上。对混频器晶体管的非线性引起的谐波进行了深入的分析。该理论得到了电路测量结果的验证。芯片采用0.4 /spl μ m CMOS工艺处理。
{"title":"A 2 V, low power, single-ended 1 GHz CMOS direct upconversion mixer","authors":"M. Borremans, M. Steyaert","doi":"10.1109/CICC.1997.606679","DOIUrl":"https://doi.org/10.1109/CICC.1997.606679","url":null,"abstract":"This paper describes a 2 V full CMOS 1 GHz upconversion mixer. The circuit has a single-ended output which avoids the use of any balun. The total power consumption in both the mixer and the output stage is only 22 mW. The signal to distortion ratio has been measured to be more than 30 dB. A thorough analysis of the harmonics caused by the nonlinearity of the mixer transistors is performed. The theory is confirmed by the measurements on the presented circuit. The chip has been processed in 0.4 /spl mu/m CMOS technology.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129692421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606636
K. Lawrence Loh, S. Narayan, A. Kuo, S. Mohapatra
This chip integrates four 32 MHz channels for twisted-pair cable digital communication using a 0.5 um digital CMOS process. The implementation features all major analog signal processing blocks on chip with a minimum number of offchip passive components. A PLL is used to provide transmit clocks as well as to center four pairs of gated VCOs for data synchronization. A 1st-order adaptive equalizer is designed to provide proper high-frequency boosting for different lengths of connecting cables. A current-mode filter with direct current amplification is used to provide output pulse shaping to conform 25.6 Mbps ATM output waveform templates. The power dissipation is measured at 1.3 W (325 mW per channel) during full operation of all 4 channels.
{"title":"A 4-channel analog front end for 25.6 Mbps ATM switches","authors":"K. Lawrence Loh, S. Narayan, A. Kuo, S. Mohapatra","doi":"10.1109/CICC.1997.606636","DOIUrl":"https://doi.org/10.1109/CICC.1997.606636","url":null,"abstract":"This chip integrates four 32 MHz channels for twisted-pair cable digital communication using a 0.5 um digital CMOS process. The implementation features all major analog signal processing blocks on chip with a minimum number of offchip passive components. A PLL is used to provide transmit clocks as well as to center four pairs of gated VCOs for data synchronization. A 1st-order adaptive equalizer is designed to provide proper high-frequency boosting for different lengths of connecting cables. A current-mode filter with direct current amplification is used to provide output pulse shaping to conform 25.6 Mbps ATM output waveform templates. The power dissipation is measured at 1.3 W (325 mW per channel) during full operation of all 4 channels.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130219129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606647
Mohammad Ashraf, Tore Kellgren, Michael Franz
This paper describes the full function model of a phase-locked loop (PLL) in a logic simulator. In contrast to conventional models that bypass the PLL function, this Verilog model accurately represents all major characteristics of a PLL. It allows the simulation of the effect of the actual filter elements. It can accurately model clock deskew of a clock tree as well as synthesize other frequencies from the input clock. It produces a clock detect signal after a realistic lock sequence. The user has the option to add jitter to the PLL output. The model performs three orders of magnitude faster than an equivalent circuit model.
{"title":"A full function Verilog(R) PLL logic model","authors":"Mohammad Ashraf, Tore Kellgren, Michael Franz","doi":"10.1109/CICC.1997.606647","DOIUrl":"https://doi.org/10.1109/CICC.1997.606647","url":null,"abstract":"This paper describes the full function model of a phase-locked loop (PLL) in a logic simulator. In contrast to conventional models that bypass the PLL function, this Verilog model accurately represents all major characteristics of a PLL. It allows the simulation of the effect of the actual filter elements. It can accurately model clock deskew of a clock tree as well as synthesize other frequencies from the input clock. It produces a clock detect signal after a realistic lock sequence. The user has the option to add jitter to the PLL output. The model performs three orders of magnitude faster than an equivalent circuit model.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132450418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606638
T. Masuda, K. Ohhata, K. Imai, R. Takeyari, K. Washio
A wide dynamic range and high transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links is described. A limiting amplifier was introduced after the transimpedance stage to overcome the trade-off between high transimpedance and a wide dynamic range. A high transimpedance of 1 k/spl Omega/ and a wide input current dynamic range up to 2 mApp were achieved with a bandwidth of 10.5 GHz, a low transimpedance fluctuation of 0.5 dB/spl Omega/, and an equivalent input noise current density of 12 pA//spl radic/(Hz), using 35-GHz Si bipolar technology.
{"title":"A wide dynamic range 1-k/spl Omega/ transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links","authors":"T. Masuda, K. Ohhata, K. Imai, R. Takeyari, K. Washio","doi":"10.1109/CICC.1997.606638","DOIUrl":"https://doi.org/10.1109/CICC.1997.606638","url":null,"abstract":"A wide dynamic range and high transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links is described. A limiting amplifier was introduced after the transimpedance stage to overcome the trade-off between high transimpedance and a wide dynamic range. A high transimpedance of 1 k/spl Omega/ and a wide input current dynamic range up to 2 mApp were achieved with a bandwidth of 10.5 GHz, a low transimpedance fluctuation of 0.5 dB/spl Omega/, and an equivalent input noise current density of 12 pA//spl radic/(Hz), using 35-GHz Si bipolar technology.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130904377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606635
L. Wong, C. Kwok, G. Rigby
An ultra low voltage, low power CMOS D/A converter using a simple multi-input floating-gate MOSFET to perform the dual function of current source and current switch is described. The outcome of this approach is very low supply voltage operation and yet maintaining high conversion accuracy. An experimental 6-bit D/A converter has been fabricated in a standard 1.2 /spl mu/m CMOS technology with V/sub th//spl ap/0.9 V and occupies 0.63 mm/sup 2/ active area. Measurement shows a single 0.9 V supply is sufficient to operate this converter, with less than 0.46 LSB linearity error, 5 MS/s conversion rate and 320 /spl mu/W power dissipation.
{"title":"A 0.9 V 5 MS/s CMOS D/A converter with multi-input floating-gate MOS","authors":"L. Wong, C. Kwok, G. Rigby","doi":"10.1109/CICC.1997.606635","DOIUrl":"https://doi.org/10.1109/CICC.1997.606635","url":null,"abstract":"An ultra low voltage, low power CMOS D/A converter using a simple multi-input floating-gate MOSFET to perform the dual function of current source and current switch is described. The outcome of this approach is very low supply voltage operation and yet maintaining high conversion accuracy. An experimental 6-bit D/A converter has been fabricated in a standard 1.2 /spl mu/m CMOS technology with V/sub th//spl ap/0.9 V and occupies 0.63 mm/sup 2/ active area. Measurement shows a single 0.9 V supply is sufficient to operate this converter, with less than 0.46 LSB linearity error, 5 MS/s conversion rate and 320 /spl mu/W power dissipation.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130931016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606617
A. Yamada, T. Yoshida, E. Holmann, T. Matsumura, S. Uramoto
A single chip system for real-time encoding and decoding for MPEG2, except for motion estimation, can be created by integrating two 250 MHz dual issue RISC processor cores with a small dedicated hardware for the variable length encoding/decoding (VLC/VLD) and block loading process. The estimated area for the encoder, 27.7 mm/sup 2/ using a 0.3-micrometer CMOS process, is 20% smaller than that of the dedicated hardware approach. An approach that uses dual issue RISC processors has the advantage of a smaller chip area and also that of being very easy to program for multimedia applications.
{"title":"Real-time MPEG2 encoding and decoding with a dual-issue RISC processor","authors":"A. Yamada, T. Yoshida, E. Holmann, T. Matsumura, S. Uramoto","doi":"10.1109/CICC.1997.606617","DOIUrl":"https://doi.org/10.1109/CICC.1997.606617","url":null,"abstract":"A single chip system for real-time encoding and decoding for MPEG2, except for motion estimation, can be created by integrating two 250 MHz dual issue RISC processor cores with a small dedicated hardware for the variable length encoding/decoding (VLC/VLD) and block loading process. The estimated area for the encoder, 27.7 mm/sup 2/ using a 0.3-micrometer CMOS process, is 20% smaller than that of the dedicated hardware approach. An approach that uses dual issue RISC processors has the advantage of a smaller chip area and also that of being very easy to program for multimedia applications.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132306906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606615
P. Goteti, G. Devarayanadurg, M. Soma
In this work we present a DFT strategy to test embedded Charge-Pump Phase Locked Loops (CP-PLL) in systems incorporating boundary scan, wherein the proposed DFT allows the verification of the operating frequency range of the CP-PLL while the system is in test mode. This is achieved with a minimal degradation in PLL performance, with lock characteristics remaining unchanged. Simulation results with the layout extracted netlist of the CP-PLL are used to illustrate the working of the technique.
{"title":"DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1","authors":"P. Goteti, G. Devarayanadurg, M. Soma","doi":"10.1109/CICC.1997.606615","DOIUrl":"https://doi.org/10.1109/CICC.1997.606615","url":null,"abstract":"In this work we present a DFT strategy to test embedded Charge-Pump Phase Locked Loops (CP-PLL) in systems incorporating boundary scan, wherein the proposed DFT allows the verification of the operating frequency range of the CP-PLL while the system is in test mode. This is achieved with a minimal degradation in PLL performance, with lock characteristics remaining unchanged. Simulation results with the layout extracted netlist of the CP-PLL are used to illustrate the working of the technique.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"32 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113958216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606690
Hsiao-Ping Tseng, C. Sechen
In this paper we present the first multi-layer graph-based router which can handle obstacles on any layer. We show that it improves the performance of a maze router with rip-up and reroute (RR) when obstacles are present. The graph-based router combined with a maze router with RR has yielded the best reported routing results for multi-layer problems with or without obstacles on any layer.
{"title":"Multi-layer over-the-cell routing with obstacles","authors":"Hsiao-Ping Tseng, C. Sechen","doi":"10.1109/CICC.1997.606690","DOIUrl":"https://doi.org/10.1109/CICC.1997.606690","url":null,"abstract":"In this paper we present the first multi-layer graph-based router which can handle obstacles on any layer. We show that it improves the performance of a maze router with rip-up and reroute (RR) when obstacles are present. The graph-based router combined with a maze router with RR has yielded the best reported routing results for multi-layer problems with or without obstacles on any layer.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"125 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114031657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606574
J.S. Ienowski, R. Badyal, A. Brown, C. E. Moore, R. Morling, T. Walley, C. Williams, D. Allstot, H.S. Wallace
A fully analog approach to an adaptive equalizer is designed in 1.0 /spl mu/m CMOS. The 13 tap FIR filter is a key component of a PRML read/write channel mixed signal IC for digital audio tape (DAT) format tape drives. A variety of continuous time, current mode, switched capacitor, and offset cancellation techniques are used to achieve desired performance.
{"title":"A CMOS analog adaptive equalizer for a DDSS tape drive PRML read channel","authors":"J.S. Ienowski, R. Badyal, A. Brown, C. E. Moore, R. Morling, T. Walley, C. Williams, D. Allstot, H.S. Wallace","doi":"10.1109/CICC.1997.606574","DOIUrl":"https://doi.org/10.1109/CICC.1997.606574","url":null,"abstract":"A fully analog approach to an adaptive equalizer is designed in 1.0 /spl mu/m CMOS. The 13 tap FIR filter is a key component of a PRML read/write channel mixed signal IC for digital audio tape (DAT) format tape drives. A variety of continuous time, current mode, switched capacitor, and offset cancellation techniques are used to achieve desired performance.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114584989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-05DOI: 10.1109/CICC.1997.606581
H. Sutoh, K. Yamakoshi, M. Ino
This paper describes a wide frequency range phase-locked-loop (PLL) clock generator embedded in a gate array LSI using 0.25 /spl mu/m CMOS/SIMOX technology. This generator supports internal clock frequency to external clock frequency ratios of 2,4,8, and 16. The PLL has two kinds of voltage-controlled oscillators that are selected automatically according to the frequency so as to widen the operating frequency range while keeping jitter low. Measured results show that the PLL operates with a lock range from 5 to 400 MHz. At 400 MHz, the peak-to-peak jitter is 50 ps. The supply voltage is 2 V and power dissipation is less than 14 mW.
本文介绍了一种采用0.25 /spl μ m CMOS/SIMOX技术嵌入门阵列LSI的宽频率范围锁相环时钟发生器。该发生器支持内部时钟频率与外部时钟频率比为2,4,8和16。锁相环有两种压控振荡器，可根据频率自动选择，从而扩大工作频率范围，同时保持低抖动。测量结果表明，锁相环工作在5 ~ 400mhz的锁相范围内。400mhz时，峰值抖动为50ps，电源电压为2v，功耗小于14mw。
{"title":"A 0.25 /spl mu/m CMOS/SIMOX PLL clock generator embedded in a gate array LSI with 5 to 400 MHz lock range","authors":"H. Sutoh, K. Yamakoshi, M. Ino","doi":"10.1109/CICC.1997.606581","DOIUrl":"https://doi.org/10.1109/CICC.1997.606581","url":null,"abstract":"This paper describes a wide frequency range phase-locked-loop (PLL) clock generator embedded in a gate array LSI using 0.25 /spl mu/m CMOS/SIMOX technology. This generator supports internal clock frequency to external clock frequency ratios of 2,4,8, and 16. The PLL has two kinds of voltage-controlled oscillators that are selected automatically according to the frequency so as to widen the operating frequency range while keeping jitter low. Measured results show that the PLL operates with a lock range from 5 to 400 MHz. At 400 MHz, the peak-to-peak jitter is 50 ps. The supply voltage is 2 V and power dissipation is less than 14 mW.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131841692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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