Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838874
O. P. Dias, J. Semião, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira
The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, emphasis is given to architecture generation, reconfiguration and quality assessment. Quality metrics and criteria, focused on design and test issues, are used for the purpose. At physical level, a Defect-Oriented Test (DOT) approach and test reuse are the basis of the methodology to estimate test effectiveness, or defects coverage. Tools which implement the methodology are presented. Results are shown for a public domain PIC processor, used as a SOC embedded core.
{"title":"Quality of electronic design: from architectural level to test coverage","authors":"O. P. Dias, J. Semião, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira","doi":"10.1109/ISQED.2000.838874","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838874","url":null,"abstract":"The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, emphasis is given to architecture generation, reconfiguration and quality assessment. Quality metrics and criteria, focused on design and test issues, are used for the purpose. At physical level, a Defect-Oriented Test (DOT) approach and test reuse are the basis of the methodology to estimate test effectiveness, or defects coverage. Tools which implement the methodology are presented. Results are shown for a public domain PIC processor, used as a SOC embedded core.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"22 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126079830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838887
M. Ikeda, H. Aoki, K. Asada
This paper proposes a new design method for voltage drop testing using on-chip voltage scan path. Using on-chip voltage monitors with a scan path data transfer architecture, this on-chip voltage scan path can measure voltage-drop on a real chip in real time with a limited number of I/O pins. Preliminary results are presented based on measurement results using a test chip, which demonstrates that this technique can effectively monitor voltage bounce in power supply lines. Quality of power supply lines can be effectively enhanced when this technique is applied to a real chip.
{"title":"DVDT: design for voltage drop test using on-chip voltage scan path","authors":"M. Ikeda, H. Aoki, K. Asada","doi":"10.1109/ISQED.2000.838887","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838887","url":null,"abstract":"This paper proposes a new design method for voltage drop testing using on-chip voltage scan path. Using on-chip voltage monitors with a scan path data transfer architecture, this on-chip voltage scan path can measure voltage-drop on a real chip in real time with a limited number of I/O pins. Preliminary results are presented based on measurement results using a test chip, which demonstrates that this technique can effectively monitor voltage bounce in power supply lines. Quality of power supply lines can be effectively enhanced when this technique is applied to a real chip.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116047624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838911
Xiaodong Zhang, K. Roy
In order to meet the power and reliability constraints, it is important to reduce both average and peak power during BIST operations. In this paper we propose a Low Power Automatic Test Pattern Generator (LPATPG) with peak power. reduction. The technique can be used during on-line testing of large circuits requiring low power consumption. The LPATPG can be implemented using linear cellular automata (CA) with appropriate external weighting logic. While the average power is reduced by finding the optimal signal activities (probabilities of signal switching) at the primary inputs, the peak power is reduced by restricting the number of active primary inputs. Results on ISCAS benchmark circuits show that while achieving high fault coverage, average power reduction up to 90%, peak power reduction up to 37% and energy reduction up to 93% can be achieved (compared to equi-probable random pattern generator by linear cellular automata), and the ratio of the number of high power vectors (vectors violating the power limit) in the LPATPG sequence to the number of high power vectors in the equi-probable random sequence can be as low as 0.44%.
{"title":"Peak power reduction in low power BIST","authors":"Xiaodong Zhang, K. Roy","doi":"10.1109/ISQED.2000.838911","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838911","url":null,"abstract":"In order to meet the power and reliability constraints, it is important to reduce both average and peak power during BIST operations. In this paper we propose a Low Power Automatic Test Pattern Generator (LPATPG) with peak power. reduction. The technique can be used during on-line testing of large circuits requiring low power consumption. The LPATPG can be implemented using linear cellular automata (CA) with appropriate external weighting logic. While the average power is reduced by finding the optimal signal activities (probabilities of signal switching) at the primary inputs, the peak power is reduced by restricting the number of active primary inputs. Results on ISCAS benchmark circuits show that while achieving high fault coverage, average power reduction up to 90%, peak power reduction up to 37% and energy reduction up to 93% can be achieved (compared to equi-probable random pattern generator by linear cellular automata), and the ratio of the number of high power vectors (vectors violating the power limit) in the LPATPG sequence to the number of high power vectors in the equi-probable random sequence can be as low as 0.44%.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116148677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838858
Ji-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, J. Kong, Hyung-Woo Kim, Sunjoo Yoo
The increasing complexity and data volume of VLSI designs demand an efficient optical proximity correction (OPC) technique. In this paper, we address the issues related to the gate bridge, which is serious in sub-quarter micron technology, and the wide range of contact CD (Critical Dimension) variation. We present the efficient gate CD control method by introducing the critical area correction. In addition, the contact CD variation is reduced under the target CD range due to the combination of the contact biasing and the process calibration. The correction time and output data volume are drastically reduced by the hierarchical data manipulation using a DRC (Design Rule Check) tool, which basically exploits the characteristics of the design layers in ASICs. The newly proposed incremental on-line violation filtering method also reduces the correction cycle time significantly.
{"title":"An efficient rule-based OPC approach using a DRC tool for 0.18 /spl mu/m ASIC","authors":"Ji-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, J. Kong, Hyung-Woo Kim, Sunjoo Yoo","doi":"10.1109/ISQED.2000.838858","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838858","url":null,"abstract":"The increasing complexity and data volume of VLSI designs demand an efficient optical proximity correction (OPC) technique. In this paper, we address the issues related to the gate bridge, which is serious in sub-quarter micron technology, and the wide range of contact CD (Critical Dimension) variation. We present the efficient gate CD control method by introducing the critical area correction. In addition, the contact CD variation is reduced under the target CD range due to the combination of the contact biasing and the process calibration. The correction time and output data volume are drastically reduced by the hierarchical data manipulation using a DRC (Design Rule Check) tool, which basically exploits the characteristics of the design layers in ASICs. The newly proposed incremental on-line violation filtering method also reduces the correction cycle time significantly.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115293301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838888
J. Knighten, N. Smith, L. Hoeft, J. T. DiBene
EMI-related common-mode currents in a high speed differential transmission line circuits can be generated by delay imbalance (skew) at a rate almost directly proportional to the amount of skew imbalance. Delay skew was shown to generate common-mode currents at a rate of four times that of slew rate skew. Radiated EMI levels were shown to follow increasing common-mode currents. Attention to delay skew imbalance should be an important design consideration at the chip level, the transmission line level and at the load in order to produce high speed differential circuits with low emission characteristics. While models using identified waveforms predict common-mode waveform harmonics that include only odd harmonics, measurements with real devices indicate the presence of all harmonics due to waveform asymmetries, such as dirty cycle distortion and rise/fall time asymmetries.
{"title":"EMI common-mode current dependence on delay skew imbalance in high speed differential transmission lines operating at 1 gigabit/second data rates","authors":"J. Knighten, N. Smith, L. Hoeft, J. T. DiBene","doi":"10.1109/ISQED.2000.838888","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838888","url":null,"abstract":"EMI-related common-mode currents in a high speed differential transmission line circuits can be generated by delay imbalance (skew) at a rate almost directly proportional to the amount of skew imbalance. Delay skew was shown to generate common-mode currents at a rate of four times that of slew rate skew. Radiated EMI levels were shown to follow increasing common-mode currents. Attention to delay skew imbalance should be an important design consideration at the chip level, the transmission line level and at the load in order to produce high speed differential circuits with low emission characteristics. While models using identified waveforms predict common-mode waveform harmonics that include only odd harmonics, measurements with real devices indicate the presence of all harmonics due to waveform asymmetries, such as dirty cycle distortion and rise/fall time asymmetries.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125093952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838870
T. Williams, R. Kapur
Today's technology allows for the creation of designs that are stressing methodologies from a time to market point of view. The industry is in a transition period where the methodologies and tools are changing to allow for reusing designs as cores. With a promise of large capacity, the miniaturization of the devices brings along new problems and changes the focus of Design for Testability (DFT) and for all the tools used in the successful manufacturing of the design. In this paper, the impact of nanometer technology on the issues associated with testing of system-on-chip (SOC) designs is discussed.
{"title":"Design for testability in nanometer technologies; searching for quality","authors":"T. Williams, R. Kapur","doi":"10.1109/ISQED.2000.838870","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838870","url":null,"abstract":"Today's technology allows for the creation of designs that are stressing methodologies from a time to market point of view. The industry is in a transition period where the methodologies and tools are changing to allow for reusing designs as cores. With a promise of large capacity, the miniaturization of the devices brings along new problems and changes the focus of Design for Testability (DFT) and for all the tools used in the successful manufacturing of the design. In this paper, the impact of nanometer technology on the issues associated with testing of system-on-chip (SOC) designs is discussed.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838867
Zhiping Yu, D. Yergeau, R. Dutton, O. S. Nakagawa, N. Chang, Shen Lin, Weize Xie
A multilayer, full chip thermal analysis is presented. The design of the chip at functional-block level is directly captured by the simulator, allowing the assessment of the chip layout impact on the system performance due to the elevated operational temperature. The heat generation for each block is obtained by running the circuit-level electrical simulation separately on individual functional units. The thermal diffusion equation is then solved based on the actual structure of the chip including substrate and interconnect/insulating layers. Different thermal conductivity can be specified for each material layer. The effect of package on chip temperature distribution is modeled using thermally resistive layers as the boundary between the simulated structure and surrounding environment. Proper adjustment of the boundary thermal resistance results in the correct range of simulated temperature distribution as compared to the measured data. Both physics and implementation for the thermal simulation are described. The code is applied to the analysis of a realistic design of a CPU chip made of SOI technology with up to six metal interconnect layers. A comprehensive review of the simulation results is presented.
{"title":"Full chip thermal simulation","authors":"Zhiping Yu, D. Yergeau, R. Dutton, O. S. Nakagawa, N. Chang, Shen Lin, Weize Xie","doi":"10.1109/ISQED.2000.838867","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838867","url":null,"abstract":"A multilayer, full chip thermal analysis is presented. The design of the chip at functional-block level is directly captured by the simulator, allowing the assessment of the chip layout impact on the system performance due to the elevated operational temperature. The heat generation for each block is obtained by running the circuit-level electrical simulation separately on individual functional units. The thermal diffusion equation is then solved based on the actual structure of the chip including substrate and interconnect/insulating layers. Different thermal conductivity can be specified for each material layer. The effect of package on chip temperature distribution is modeled using thermally resistive layers as the boundary between the simulated structure and surrounding environment. Proper adjustment of the boundary thermal resistance results in the correct range of simulated temperature distribution as compared to the measured data. Both physics and implementation for the thermal simulation are described. The code is applied to the analysis of a realistic design of a CPU chip made of SOI technology with up to six metal interconnect layers. A comprehensive review of the simulation results is presented.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130046092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838900
Jean-Pierre Gukguen, P. Bricaud
Synopsys and Mentor Graphics have announced a new extended OpenMORE hard IP section version 1.0, including added measurability criteria for design and verification of hard cores, and incorporating key hard deliverables specifications from the VSIA industry group. OpenMORE provides the industry's premier methodology to simply and quickly evaluate the reusability of soft and hard IP cores for SoC design. OpenMORE structures the assessment of the reuse quality of IP cores. IP developers enter assessment data into the worksheet following approximately 150 rules and guidelines for soft cores and about 100 rules and guidelines for hard cores. Rules are assigned 5 points and guidelines are assigned 1 point. There are three categories used for the grading process; Macro Design Guidelines, Verification Guidelines, and Deliverable Guidelines.
{"title":"Applying the OpenMORE assessment program for IP cores","authors":"Jean-Pierre Gukguen, P. Bricaud","doi":"10.1109/ISQED.2000.838900","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838900","url":null,"abstract":"Synopsys and Mentor Graphics have announced a new extended OpenMORE hard IP section version 1.0, including added measurability criteria for design and verification of hard cores, and incorporating key hard deliverables specifications from the VSIA industry group. OpenMORE provides the industry's premier methodology to simply and quickly evaluate the reusability of soft and hard IP cores for SoC design. OpenMORE structures the assessment of the reuse quality of IP cores. IP developers enter assessment data into the worksheet following approximately 150 rules and guidelines for soft cores and about 100 rules and guidelines for hard cores. Rules are assigned 5 points and guidelines are assigned 1 point. There are three categories used for the grading process; Macro Design Guidelines, Verification Guidelines, and Deliverable Guidelines.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131555301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838896
Jin Ding, D. Moloney, Xiaojun Wang
Space- and time-oriented compactions are to reduce the output response data width and length of circuits under test for built-in self-test technique. In this paper, the space- and time-oriented compaction techniques are considered together. First, the space-oriented data compaction technique is analyzed. We present a scheme, which can compress the data of k-output circuit into 1-bit signature stream with zero-aliasing and zero-performance-degradation for single stuck-line faults. Based on the investigation of the space's odd-sensitized and space's even-sensitized faults of the circuits under test, we discuss the compact methods of space's odd sensitization and space's even sensitization test responses, respectively. The graph coloring is adopted to decrease space compactor overhead. The coloring complexity is greatly decreased owing to only painting the output notes with respect to the space's even-sensitized faults. Next, we take into account the time-oriented data compaction scheme. We use the property that a test vector detects multiple faults in the time's even sensitization response compaction. In the time-oriented compaction approach developed in this paper, an s-bit long data stream can be compressed to an r-bit signature with zero-aliasing, where s/spl Gt/r. Experimental results are presented to demonstrate the effectiveness of the proposed space- and time-oriented compaction techniques.
{"title":"Aliasing-free space and time compactions with limited overhead","authors":"Jin Ding, D. Moloney, Xiaojun Wang","doi":"10.1109/ISQED.2000.838896","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838896","url":null,"abstract":"Space- and time-oriented compactions are to reduce the output response data width and length of circuits under test for built-in self-test technique. In this paper, the space- and time-oriented compaction techniques are considered together. First, the space-oriented data compaction technique is analyzed. We present a scheme, which can compress the data of k-output circuit into 1-bit signature stream with zero-aliasing and zero-performance-degradation for single stuck-line faults. Based on the investigation of the space's odd-sensitized and space's even-sensitized faults of the circuits under test, we discuss the compact methods of space's odd sensitization and space's even sensitization test responses, respectively. The graph coloring is adopted to decrease space compactor overhead. The coloring complexity is greatly decreased owing to only painting the output notes with respect to the space's even-sensitized faults. Next, we take into account the time-oriented data compaction scheme. We use the property that a test vector detects multiple faults in the time's even sensitization response compaction. In the time-oriented compaction approach developed in this paper, an s-bit long data stream can be compressed to an r-bit signature with zero-aliasing, where s/spl Gt/r. Experimental results are presented to demonstrate the effectiveness of the proposed space- and time-oriented compaction techniques.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132641518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838916
R. Ferreira, Anne-Marie Trullemans-Anckaert, José C. Costa, J. Monteiro
We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and combinational modules of different degrees of complexity. We propose a bottom-up approach to create a simplified high-level model of the block behavior for power estimation, which is described by a symbolic local polynomial. We use an efficient gate-level modeling based on the polynomial simulation method and ZBDDs. We present a set of experimental results that show a large improvement in performance and robustness when compared to previous approaches.
{"title":"Probabilistic bottom-up RTL power estimation","authors":"R. Ferreira, Anne-Marie Trullemans-Anckaert, José C. Costa, J. Monteiro","doi":"10.1109/ISQED.2000.838916","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838916","url":null,"abstract":"We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and combinational modules of different degrees of complexity. We propose a bottom-up approach to create a simplified high-level model of the block behavior for power estimation, which is described by a symbolic local polynomial. We use an efficient gate-level modeling based on the polynomial simulation method and ZBDDs. We present a set of experimental results that show a large improvement in performance and robustness when compared to previous approaches.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128606352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：