Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838919
S. Nassif
Process-induced parameter variations cause performance fluctuations and are an important consideration in the design of high performance digital ICs. Until recently, it was sufficient to model die-to-die shifts in device (active) and wire (passive) parameters, leading to a natural worst-case design methodology. In the deep-submicron era, however, within-die variations in these same device and wire parameters become just as important. In fact, current integrated circuits are large enough that variations within the die are as large as variations from die-to-die. Furthermore, while die-to-die shifts are substantially independent of the design, within-die variations are profoundly influenced by the detailed physical implementation of the IC. This changes the fundamental view of process variability from something that is imposed on the design by the fabrication process to something that is co-generated between the design and the process. This paper starts by examining the sources and historical trends in device and wire variability, distinguishing between inter-die and intra-die variations, and proposes techniques for design for variability (DOV) in the presence of both types of variations.
{"title":"Design for variability in DSM technologies [deep submicron technologies]","authors":"S. Nassif","doi":"10.1109/ISQED.2000.838919","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838919","url":null,"abstract":"Process-induced parameter variations cause performance fluctuations and are an important consideration in the design of high performance digital ICs. Until recently, it was sufficient to model die-to-die shifts in device (active) and wire (passive) parameters, leading to a natural worst-case design methodology. In the deep-submicron era, however, within-die variations in these same device and wire parameters become just as important. In fact, current integrated circuits are large enough that variations within the die are as large as variations from die-to-die. Furthermore, while die-to-die shifts are substantially independent of the design, within-die variations are profoundly influenced by the detailed physical implementation of the IC. This changes the fundamental view of process variability from something that is imposed on the design by the fabrication process to something that is co-generated between the design and the process. This paper starts by examining the sources and historical trends in device and wire variability, distinguishing between inter-die and intra-die variations, and proposes techniques for design for variability (DOV) in the presence of both types of variations.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838851
M. Shur, T. Fjeldly, T. Ytterdal
We review field effect transistor modeling with emphasis on device parameter extraction for testing. We consider the physics-based universal charge control model, which allows us to describe the subthreshold, the weak inversion, and the strong inversion regimes in MOSFETs using a relatively small set of parameters, most of which are related to the device structure or fabrication process. This small parameter set makes the task of parameter extraction easier. The model accounts for velocity saturation, finite output conductance in saturation, drain induced barrier lowering, kink effect, floating body effect, and subthreshold leakage. The model has been applied to MOSFETs, SOI transistors, GaAs MESFETs, GaAs based HEMTs, amorphous, polysilicon and organic TFTs, AlGaN/GaN HEMTs, and to new emerging heterodimensional transistors. For compound semiconductor devices, additional effects, such as frequency dispersion and temperature dependence of model parameters, and gate leakage current, including hot-carrier leakage, have been accounted for.
{"title":"Transistor modeling for the VDSM era","authors":"M. Shur, T. Fjeldly, T. Ytterdal","doi":"10.1109/ISQED.2000.838851","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838851","url":null,"abstract":"We review field effect transistor modeling with emphasis on device parameter extraction for testing. We consider the physics-based universal charge control model, which allows us to describe the subthreshold, the weak inversion, and the strong inversion regimes in MOSFETs using a relatively small set of parameters, most of which are related to the device structure or fabrication process. This small parameter set makes the task of parameter extraction easier. The model accounts for velocity saturation, finite output conductance in saturation, drain induced barrier lowering, kink effect, floating body effect, and subthreshold leakage. The model has been applied to MOSFETs, SOI transistors, GaAs MESFETs, GaAs based HEMTs, amorphous, polysilicon and organic TFTs, AlGaN/GaN HEMTs, and to new emerging heterodimensional transistors. For compound semiconductor devices, additional effects, such as frequency dispersion and temperature dependence of model parameters, and gate leakage current, including hot-carrier leakage, have been accounted for.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129722392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838853
M. Becer, I. Hajj
The impact of interconnect coupling, in the form of delay and crosstalk, in deep submicron integrated circuit design is increasing. In many cases, especially in routing, the coupling capacitance, C/sub c/, between adjacent lines is decoupled and replaced by 2C/sub c/ connected to ground for fast worst-case delay estimation. This is based on the assumption that worst-case delay occurs when two adjacent lines switch simultaneously in opposite directions so that the voltage change across the coupling capacitance is twice that when only one line is switching. Similarly, when two adjacent lines switch simultaneously in the same direction, the coupling capacitance is put to zero based on the fact that the voltage difference across it is zero. However, we show that by replacing the coupling capacitance C/sub c/ with a grounded capacitance of 2C/sub c/ (or by zero) when signals switch simultaneously in opposite (or same) directions may overestimate or even underestimate the actual delay. The variable strengths of the drivers driving the coupled lines bring in an additional level of complexity to the delay estimation when coupling exists. In this paper, we derive a simple analytical model that takes the effect of different driver strengths into account, to accurately estimate the delay and crosstalk of two coupled interconnect lines switching simultaneously. This approach also gives the exact values of the multiplicants that C/sub c/ should be multiplied with, if the lines are to be decoupled, for both worst-case and best-case delay computation; that is when the signals switch in opposite direction and when they switch in the same direction.
{"title":"An analytical model for delay and crosstalk estimation with application to decoupling","authors":"M. Becer, I. Hajj","doi":"10.1109/ISQED.2000.838853","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838853","url":null,"abstract":"The impact of interconnect coupling, in the form of delay and crosstalk, in deep submicron integrated circuit design is increasing. In many cases, especially in routing, the coupling capacitance, C/sub c/, between adjacent lines is decoupled and replaced by 2C/sub c/ connected to ground for fast worst-case delay estimation. This is based on the assumption that worst-case delay occurs when two adjacent lines switch simultaneously in opposite directions so that the voltage change across the coupling capacitance is twice that when only one line is switching. Similarly, when two adjacent lines switch simultaneously in the same direction, the coupling capacitance is put to zero based on the fact that the voltage difference across it is zero. However, we show that by replacing the coupling capacitance C/sub c/ with a grounded capacitance of 2C/sub c/ (or by zero) when signals switch simultaneously in opposite (or same) directions may overestimate or even underestimate the actual delay. The variable strengths of the drivers driving the coupled lines bring in an additional level of complexity to the delay estimation when coupling exists. In this paper, we derive a simple analytical model that takes the effect of different driver strengths into account, to accurately estimate the delay and crosstalk of two coupled interconnect lines switching simultaneously. This approach also gives the exact values of the multiplicants that C/sub c/ should be multiplied with, if the lines are to be decoupled, for both worst-case and best-case delay computation; that is when the signals switch in opposite direction and when they switch in the same direction.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117207408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838859
Kwan-Do Kim, Young-Kwan Park, Jun-Ha Lee, J. Kong, Hee-Sung Kang, Young-Wug Kim, Seok-Jin Kim
Fully Depleted Silicon-on-Insulator (SOI) devices have led to better electrical characteristics (e.g., reduced junction depth, increased channel mobility, suppressed short channel effect, excellent latchup immunity, and improved subthreshold characteristics) than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO/sub 2/ layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three dimensional (3D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller than a critical value in a finger-type layout. The current degradation for the 3D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.
{"title":"Three dimensional analysis of thermal degradation effects in FDSOI MOSFETs","authors":"Kwan-Do Kim, Young-Kwan Park, Jun-Ha Lee, J. Kong, Hee-Sung Kang, Young-Wug Kim, Seok-Jin Kim","doi":"10.1109/ISQED.2000.838859","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838859","url":null,"abstract":"Fully Depleted Silicon-on-Insulator (SOI) devices have led to better electrical characteristics (e.g., reduced junction depth, increased channel mobility, suppressed short channel effect, excellent latchup immunity, and improved subthreshold characteristics) than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO/sub 2/ layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three dimensional (3D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller than a critical value in a finger-type layout. The current degradation for the 3D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130353489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838894
E. McShane, K. Shenai
The monolithic integration of mixed-signal and RF microelectronics is straining the capabilities of present CAD roots for predictive analysis. In particular, the effects of di/dt, crosstalk, high-frequency impedance matching, and substrate noise pose challenges to reliable circuit operation. This is especially true as supply rail voltages continue to shrink below 2.5 V. Although PCB CAD tools have successfully addressed these issues, similar. tools have yet to penetrate the VLSIC/RFIC market due to the even greater signal frequencies and far greater network density. We describe an ongoing research effort to introduce models of these effects into a commercial CAD tool. The goal is to develop a correct-by-design CAD system in which constraints on signal crosstalk and EMI are considered along with signal delay and power restrictions in performing automated floor-planning and routing. To permit top-down synthesis of reliable systems, we are also expanding the HDL coding of digital systems to include two additional parameters: EMI victim status and EMl point-source contributions.
{"title":"Correct-by-design CAD enhancement for EMI and signal integrity","authors":"E. McShane, K. Shenai","doi":"10.1109/ISQED.2000.838894","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838894","url":null,"abstract":"The monolithic integration of mixed-signal and RF microelectronics is straining the capabilities of present CAD roots for predictive analysis. In particular, the effects of di/dt, crosstalk, high-frequency impedance matching, and substrate noise pose challenges to reliable circuit operation. This is especially true as supply rail voltages continue to shrink below 2.5 V. Although PCB CAD tools have successfully addressed these issues, similar. tools have yet to penetrate the VLSIC/RFIC market due to the even greater signal frequencies and far greater network density. We describe an ongoing research effort to introduce models of these effects into a commercial CAD tool. The goal is to develop a correct-by-design CAD system in which constraints on signal crosstalk and EMI are considered along with signal delay and power restrictions in performing automated floor-planning and routing. To permit top-down synthesis of reliable systems, we are also expanding the HDL coding of digital systems to include two additional parameters: EMI victim status and EMl point-source contributions.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115217824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838886
T. Haniotakis, Y. Tsiatouhas, D. Nikolos, C. Efstathiou
Domino circuits are increasingly popular because they offer a significant performance boost over static ones. An inherent problem with domino CMOS gates is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of the circuit can destroy the noise margin and cause glitches at the output of a domino gate. Among the dominant solutions proposed, in the open literature, to overcome this problem is the technique of internal nodes multiple precharging. However the added precharge transistors are not testable for stuck-open and stuck-on faults. Undetectable stuck-open faults on these transistors cause reduction of the noise margins of the gate. Then the operation of the circuit in the field is sensitive to environmental factors, such as noise. In this paper we propose a new internal nodes multiple precharging scheme that leads to testable designs for stuck-open and stuck-on faults.
{"title":"On testability of multiple precharged domino logic","authors":"T. Haniotakis, Y. Tsiatouhas, D. Nikolos, C. Efstathiou","doi":"10.1109/ISQED.2000.838886","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838886","url":null,"abstract":"Domino circuits are increasingly popular because they offer a significant performance boost over static ones. An inherent problem with domino CMOS gates is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of the circuit can destroy the noise margin and cause glitches at the output of a domino gate. Among the dominant solutions proposed, in the open literature, to overcome this problem is the technique of internal nodes multiple precharging. However the added precharge transistors are not testable for stuck-open and stuck-on faults. Undetectable stuck-open faults on these transistors cause reduction of the noise margins of the gate. Then the operation of the circuit in the field is sensitive to environmental factors, such as noise. In this paper we propose a new internal nodes multiple precharging scheme that leads to testable designs for stuck-open and stuck-on faults.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115455418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838906
R. Goldman, K. Bartleson
Deep submicron processes are driving silicon complexity, time-to-market windows continue to shrink and experienced design engineers are at a premium. The system-on-a-chip era is approaching and pushing technology at every turn. As a result, companies are looking for ways to get the most out of their design resources. High quality design systems, developed from powerful EDA tools and interface software, ensure more efficient use of resources and ultimately, high quality designs. Unfortunately, many engineers are spending time wrestling new tools into their design systems instead of designing or verifying their designs. The need for EDA tool interoperability has never been greater. Fortunately, some progressive EDA companies are spearheading efforts to improve tool interoperability. This paper will explore the benefits of tool interoperability and define several ways that it can be achieved.
{"title":"Tool interoperability is key to improved design quality","authors":"R. Goldman, K. Bartleson","doi":"10.1109/ISQED.2000.838906","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838906","url":null,"abstract":"Deep submicron processes are driving silicon complexity, time-to-market windows continue to shrink and experienced design engineers are at a premium. The system-on-a-chip era is approaching and pushing technology at every turn. As a result, companies are looking for ways to get the most out of their design resources. High quality design systems, developed from powerful EDA tools and interface software, ensure more efficient use of resources and ultimately, high quality designs. Unfortunately, many engineers are spending time wrestling new tools into their design systems instead of designing or verifying their designs. The need for EDA tool interoperability has never been greater. Fortunately, some progressive EDA companies are spearheading efforts to improve tool interoperability. This paper will explore the benefits of tool interoperability and define several ways that it can be achieved.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121413987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838903
A. Farrahi, D. J. Hathaway, Maogang Wang, M. Sarrafzadeh
In this paper we survey major problems faced by EDA tools in tackling deep submicron (DSM) design challenges like: crosstalk, reliability, power and interconnect dominated delay. We discuss the need for rethinking quality models used in EDA tools to allow early and reliable planning, estimation, analysis, and optimization. Key design quality metrics from a CAD tool perspective are surveyed, and methodologies and directions are proposed for the next generation design automation tools, intended to meet the challenges ahead. Ideas such as forward synthesis, incremental synthesis, system-level interconnect prediction and planning, and their implications on design quality design tool architecture, and design methodology are explored.
{"title":"Quality of EDA CAD tools: definitions, metrics and directions","authors":"A. Farrahi, D. J. Hathaway, Maogang Wang, M. Sarrafzadeh","doi":"10.1109/ISQED.2000.838903","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838903","url":null,"abstract":"In this paper we survey major problems faced by EDA tools in tackling deep submicron (DSM) design challenges like: crosstalk, reliability, power and interconnect dominated delay. We discuss the need for rethinking quality models used in EDA tools to allow early and reliable planning, estimation, analysis, and optimization. Key design quality metrics from a CAD tool perspective are surveyed, and methodologies and directions are proposed for the next generation design automation tools, intended to meet the challenges ahead. Ideas such as forward synthesis, incremental synthesis, system-level interconnect prediction and planning, and their implications on design quality design tool architecture, and design methodology are explored.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838885
M. Dessouky, M. Louërat
This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural layout approach is shown to be best suited for this kind of methodology. Once captured, the procedural description can be used several times to calculate both rapidly and accurately all parasitics that appear during physical realizations without layout generation. Efficient algorithms are developed to take into account analog layout constraints such as matching, parasitic control, shape and reliability considerations. This allows one to account for these effects early in the design which guarantees the fulfilment of the required performance specifications, permits one to optimize various design aspects in the presence of parasitics and shortens the overall design time by avoiding laborious sizing-layout iterations. An example of a high performance OTA is presented at the end to illustrate the effectiveness of the approach.
{"title":"A layout approach for electrical and physical design integration of high-performance analog circuits","authors":"M. Dessouky, M. Louërat","doi":"10.1109/ISQED.2000.838885","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838885","url":null,"abstract":"This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural layout approach is shown to be best suited for this kind of methodology. Once captured, the procedural description can be used several times to calculate both rapidly and accurately all parasitics that appear during physical realizations without layout generation. Efficient algorithms are developed to take into account analog layout constraints such as matching, parasitic control, shape and reliability considerations. This allows one to account for these effects early in the design which guarantees the fulfilment of the required performance specifications, permits one to optimize various design aspects in the presence of parasitics and shortens the overall design time by avoiding laborious sizing-layout iterations. An example of a high performance OTA is presented at the end to illustrate the effectiveness of the approach.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123375984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838871
P. Girard
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to the circuit reliability. Moreover, it may be responsible for cost, performance verification as well as technology related problems and can dramatically shorten the battery life when on-line testing is considered. In this paper, we present a survey of the low power testing techniques that can be used to test VLSI systems. In the first part, the paper explains the problems induced by the increased power consumed during functional testing of a circuit, in either external testing or built-in self-test (BIST). Next, we survey state-of-the-art techniques that exist to reduce this power/energy consumption during test mode and allow non-destructive testing of the device under test.
{"title":"Low power testing of VLSI circuits: problems and solutions","authors":"P. Girard","doi":"10.1109/ISQED.2000.838871","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838871","url":null,"abstract":"Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to the circuit reliability. Moreover, it may be responsible for cost, performance verification as well as technology related problems and can dramatically shorten the battery life when on-line testing is considered. In this paper, we present a survey of the low power testing techniques that can be used to test VLSI systems. In the first part, the paper explains the problems induced by the increased power consumed during functional testing of a circuit, in either external testing or built-in self-test (BIST). Next, we survey state-of-the-art techniques that exist to reduce this power/energy consumption during test mode and allow non-destructive testing of the device under test.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114534373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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