Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838870
T. Williams, R. Kapur
Today's technology allows for the creation of designs that are stressing methodologies from a time to market point of view. The industry is in a transition period where the methodologies and tools are changing to allow for reusing designs as cores. With a promise of large capacity, the miniaturization of the devices brings along new problems and changes the focus of Design for Testability (DFT) and for all the tools used in the successful manufacturing of the design. In this paper, the impact of nanometer technology on the issues associated with testing of system-on-chip (SOC) designs is discussed.
{"title":"Design for testability in nanometer technologies; searching for quality","authors":"T. Williams, R. Kapur","doi":"10.1109/ISQED.2000.838870","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838870","url":null,"abstract":"Today's technology allows for the creation of designs that are stressing methodologies from a time to market point of view. The industry is in a transition period where the methodologies and tools are changing to allow for reusing designs as cores. With a promise of large capacity, the miniaturization of the devices brings along new problems and changes the focus of Design for Testability (DFT) and for all the tools used in the successful manufacturing of the design. In this paper, the impact of nanometer technology on the issues associated with testing of system-on-chip (SOC) designs is discussed.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838916
R. Ferreira, Anne-Marie Trullemans-Anckaert, José C. Costa, J. Monteiro
We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and combinational modules of different degrees of complexity. We propose a bottom-up approach to create a simplified high-level model of the block behavior for power estimation, which is described by a symbolic local polynomial. We use an efficient gate-level modeling based on the polynomial simulation method and ZBDDs. We present a set of experimental results that show a large improvement in performance and robustness when compared to previous approaches.
{"title":"Probabilistic bottom-up RTL power estimation","authors":"R. Ferreira, Anne-Marie Trullemans-Anckaert, José C. Costa, J. Monteiro","doi":"10.1109/ISQED.2000.838916","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838916","url":null,"abstract":"We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and combinational modules of different degrees of complexity. We propose a bottom-up approach to create a simplified high-level model of the block behavior for power estimation, which is described by a symbolic local polynomial. We use an efficient gate-level modeling based on the polynomial simulation method and ZBDDs. We present a set of experimental results that show a large improvement in performance and robustness when compared to previous approaches.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128606352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838867
Zhiping Yu, D. Yergeau, R. Dutton, O. S. Nakagawa, N. Chang, Shen Lin, Weize Xie
A multilayer, full chip thermal analysis is presented. The design of the chip at functional-block level is directly captured by the simulator, allowing the assessment of the chip layout impact on the system performance due to the elevated operational temperature. The heat generation for each block is obtained by running the circuit-level electrical simulation separately on individual functional units. The thermal diffusion equation is then solved based on the actual structure of the chip including substrate and interconnect/insulating layers. Different thermal conductivity can be specified for each material layer. The effect of package on chip temperature distribution is modeled using thermally resistive layers as the boundary between the simulated structure and surrounding environment. Proper adjustment of the boundary thermal resistance results in the correct range of simulated temperature distribution as compared to the measured data. Both physics and implementation for the thermal simulation are described. The code is applied to the analysis of a realistic design of a CPU chip made of SOI technology with up to six metal interconnect layers. A comprehensive review of the simulation results is presented.
{"title":"Full chip thermal simulation","authors":"Zhiping Yu, D. Yergeau, R. Dutton, O. S. Nakagawa, N. Chang, Shen Lin, Weize Xie","doi":"10.1109/ISQED.2000.838867","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838867","url":null,"abstract":"A multilayer, full chip thermal analysis is presented. The design of the chip at functional-block level is directly captured by the simulator, allowing the assessment of the chip layout impact on the system performance due to the elevated operational temperature. The heat generation for each block is obtained by running the circuit-level electrical simulation separately on individual functional units. The thermal diffusion equation is then solved based on the actual structure of the chip including substrate and interconnect/insulating layers. Different thermal conductivity can be specified for each material layer. The effect of package on chip temperature distribution is modeled using thermally resistive layers as the boundary between the simulated structure and surrounding environment. Proper adjustment of the boundary thermal resistance results in the correct range of simulated temperature distribution as compared to the measured data. Both physics and implementation for the thermal simulation are described. The code is applied to the analysis of a realistic design of a CPU chip made of SOI technology with up to six metal interconnect layers. A comprehensive review of the simulation results is presented.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130046092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838872
Zhanping Chen, Liqiong Wei, K. Roy
The use of low threshold devices in low voltage CMOS circuits leads to an exponential increase in the intrinsic leakage current. This threatens the effectiveness of I/sub DDQ/ testing for such low voltage circuits because it is difficult to differentiate a defect-free circuit from defective circuits. Recently, several leakage control techniques have been proposed to reduce intrinsic leakage current, which may benefit I/sub DDQ/ testing. In this paper we investigate the possibilities of applying different leakage control techniques to improve the fault coverage of I/sub DDQ/ testing. Results on a large number of benchmarks indicate that dual threshold and vector control techniques are very effective in improving fault coverage for I/sub DDQ/ testing.
{"title":"On effective I/sub DDQ/ testing of low voltage CMOS circuits using leakage control techniques","authors":"Zhanping Chen, Liqiong Wei, K. Roy","doi":"10.1109/ISQED.2000.838872","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838872","url":null,"abstract":"The use of low threshold devices in low voltage CMOS circuits leads to an exponential increase in the intrinsic leakage current. This threatens the effectiveness of I/sub DDQ/ testing for such low voltage circuits because it is difficult to differentiate a defect-free circuit from defective circuits. Recently, several leakage control techniques have been proposed to reduce intrinsic leakage current, which may benefit I/sub DDQ/ testing. In this paper we investigate the possibilities of applying different leakage control techniques to improve the fault coverage of I/sub DDQ/ testing. Results on a large number of benchmarks indicate that dual threshold and vector control techniques are very effective in improving fault coverage for I/sub DDQ/ testing.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129258691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838884
D. Dent
Multi-Chip Module (MCM) projects are complex, in terms of the technology used, and are expensive, typically in excess of $50,000. MCM technology is very unforgiving in that mistakes cannot be easily rectified or the device easily re-worked. The Mosaic Earth Sensor Mutli-Chip Module (MESMCM) project, which was the subject of a case study, was a high speed, first-of-a-kind development that ran into some difficulties in spite of rigorous project management. It is intended to compare the project management structure used for a technology demonstrator with the new structure used on subsequent MCM designs. One of the outcomes of this case study was that the management of an MCM project is just as crucial as the technical aspects and resulted in several guidelines about the nature and composition of the design team. The lessons learned from the MESMCM project were applied very effectively to further MCM designs.
{"title":"Project management for system-on-chip using multi-chip modules","authors":"D. Dent","doi":"10.1109/ISQED.2000.838884","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838884","url":null,"abstract":"Multi-Chip Module (MCM) projects are complex, in terms of the technology used, and are expensive, typically in excess of $50,000. MCM technology is very unforgiving in that mistakes cannot be easily rectified or the device easily re-worked. The Mosaic Earth Sensor Mutli-Chip Module (MESMCM) project, which was the subject of a case study, was a high speed, first-of-a-kind development that ran into some difficulties in spite of rigorous project management. It is intended to compare the project management structure used for a technology demonstrator with the new structure used on subsequent MCM designs. One of the outcomes of this case study was that the management of an MCM project is just as crucial as the technical aspects and resulted in several guidelines about the nature and composition of the design team. The lessons learned from the MESMCM project were applied very effectively to further MCM designs.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124372789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838937
P. Tehrani, S. Chyou, U. Ekambaram
A complete and accurate method for static timing analysis of deep sub-micron devices in presence of crosstalk is introduced. This scheme provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. This paper presents the solution to the crosstalk problem implemented in the static timing tool PathMill as its crosstalk extension (CTX). A comparison of simulation results between this approach and SPICE is also provided.
{"title":"Deep sub-micron static timing analysis in presence of crosstalk","authors":"P. Tehrani, S. Chyou, U. Ekambaram","doi":"10.1109/ISQED.2000.838937","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838937","url":null,"abstract":"A complete and accurate method for static timing analysis of deep sub-micron devices in presence of crosstalk is introduced. This scheme provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. This paper presents the solution to the crosstalk problem implemented in the static timing tool PathMill as its crosstalk extension (CTX). A comparison of simulation results between this approach and SPICE is also provided.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116627673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838891
R. Lin
A novel reconfigurable low-power high-performance matrix multiplier architecture and its component circuits are presented. The processor can be easily reconfigured to compute the product of matrices X/sub nK/ and Y/sub km/ for any integers n, k, m and any item precision b (ranging from 4 to 64 bits) thus maximizing the utilization of the hardware available. As a typical example, the hardware equivalent to one 64/spl times/64 bit high precision multiplier in the system can be directly reconfigured to produce the product of two matrices X/sub 8/spl times/8/ and Y/sub 8/spl times/8/ of 8-bit items in 9 pipeline cycles, which would require 512 multiplications (done by large multipliers) in a non-reconfigurable high precision system. Given an input stream of h/spl times/h matrix pairs with b-bit items, the processor, called matrix multiplier of size s (note s=hb), may consist of an array of (s/m)/sup 2/ of m/spl times/m small multipliers (m=4 case is illustrated), a few arrays of adders each adding three numbers, an array of accumulators and corresponding simple reconfiguration switches. To compute the product of X/sub nK/ and Y/sub km/, of item precision b on the proposed processor of size s we only need to partition X/sub nK/ and Y/sub km/ into s/b X s/b sub-matrices, reconfigure the processor according to the values of s (fixed) and b (input parameter), compute the products of submatrices, and accumulate them for the desired result in pipelined fashion. A recently proposed shift switch logic, a nonbinary logic for arithmetic circuits, is utilized in the design. The novel logic operates 4-bit state signals where no more than half of the signal bits are subject to value-change at any logic stage, which, verified by SPICE simulation, significantly reduces the large circuit power dissipation while keeping high performance in speed and small VLSI area.
{"title":"A reconfigurable low-power high-performance matrix multiplier design","authors":"R. Lin","doi":"10.1109/ISQED.2000.838891","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838891","url":null,"abstract":"A novel reconfigurable low-power high-performance matrix multiplier architecture and its component circuits are presented. The processor can be easily reconfigured to compute the product of matrices X/sub nK/ and Y/sub km/ for any integers n, k, m and any item precision b (ranging from 4 to 64 bits) thus maximizing the utilization of the hardware available. As a typical example, the hardware equivalent to one 64/spl times/64 bit high precision multiplier in the system can be directly reconfigured to produce the product of two matrices X/sub 8/spl times/8/ and Y/sub 8/spl times/8/ of 8-bit items in 9 pipeline cycles, which would require 512 multiplications (done by large multipliers) in a non-reconfigurable high precision system. Given an input stream of h/spl times/h matrix pairs with b-bit items, the processor, called matrix multiplier of size s (note s=hb), may consist of an array of (s/m)/sup 2/ of m/spl times/m small multipliers (m=4 case is illustrated), a few arrays of adders each adding three numbers, an array of accumulators and corresponding simple reconfiguration switches. To compute the product of X/sub nK/ and Y/sub km/, of item precision b on the proposed processor of size s we only need to partition X/sub nK/ and Y/sub km/ into s/b X s/b sub-matrices, reconfigure the processor according to the values of s (fixed) and b (input parameter), compute the products of submatrices, and accumulate them for the desired result in pipelined fashion. A recently proposed shift switch logic, a nonbinary logic for arithmetic circuits, is utilized in the design. The novel logic operates 4-bit state signals where no more than half of the signal bits are subject to value-change at any logic stage, which, verified by SPICE simulation, significantly reduces the large circuit power dissipation while keeping high performance in speed and small VLSI area.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123119613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838878
A. Sinha
Summary form only given, as follows. After more than thirty years of effectiveness, associated benefits to the electronics industry and several false alarms, it appears that Moore's Law is again threatened with derailment. These threats are in the form of a convergence of three waves which requires major necessary changes relating to: a) lithography below 0.13 /spl mu/m, which involves printing and aligning at submicron wavelength dimensions with new unproven lasers/lens systems; b) Cu/low-/spl kappa/ interconnect technology, which is facing major challenges in achieving commercially viable yields; and c) 300 mm wafer size conversion, which requires an extensive retooling of the entire industry. These enabling changes are overlaid on increasingly aggressive cost/quality requirements on the semiconductor fabs as the electronics industry evolves into the post-PC, Internet era. The author reviews some of the cutting edge work being done in the semiconductor manufacturing equipment area, including extendability/reuse of existing installed base for multiple generations, improved BKM's (Best Known Methodologies) and integrated process modules.
{"title":"Extending Moore's Law through advances in semiconductor manufacturing equipment","authors":"A. Sinha","doi":"10.1109/ISQED.2000.838878","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838878","url":null,"abstract":"Summary form only given, as follows. After more than thirty years of effectiveness, associated benefits to the electronics industry and several false alarms, it appears that Moore's Law is again threatened with derailment. These threats are in the form of a convergence of three waves which requires major necessary changes relating to: a) lithography below 0.13 /spl mu/m, which involves printing and aligning at submicron wavelength dimensions with new unproven lasers/lens systems; b) Cu/low-/spl kappa/ interconnect technology, which is facing major challenges in achieving commercially viable yields; and c) 300 mm wafer size conversion, which requires an extensive retooling of the entire industry. These enabling changes are overlaid on increasingly aggressive cost/quality requirements on the semiconductor fabs as the electronics industry evolves into the post-PC, Internet era. The author reviews some of the cutting edge work being done in the semiconductor manufacturing equipment area, including extendability/reuse of existing installed base for multiple generations, improved BKM's (Best Known Methodologies) and integrated process modules.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134110175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838924
G. Maier, Shawn Smith
Today's industry is expanding the high performance microprocessor market into the consumer market place. This market requires very low cost, high reliability, stricter SPQL levels, and very high yields. A New Diagnostic Methodology is required to meet these new demands. This paper addresses a broad scope of issues from Product Design and Manufacturing Test, to Diagnostic and Data Analysis Tools. It describes a beta test case currently in operation on IBM's latest PowerPC products in their copper and SOI technologies.
{"title":"Electronic process limited yield","authors":"G. Maier, Shawn Smith","doi":"10.1109/ISQED.2000.838924","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838924","url":null,"abstract":"Today's industry is expanding the high performance microprocessor market into the consumer market place. This market requires very low cost, high reliability, stricter SPQL levels, and very high yields. A New Diagnostic Methodology is required to meet these new demands. This paper addresses a broad scope of issues from Product Design and Manufacturing Test, to Diagnostic and Data Analysis Tools. It describes a beta test case currently in operation on IBM's latest PowerPC products in their copper and SOI technologies.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123848199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838852
Gilbert Yoh, F. Najm
The lognormal has been traditionally used to model the failure time distribution of electromigration failures. However, when used to estimate the failure of large metal layers, it leads to a clear disagreement with established empirical data. To resolve this problem, we propose to use a shifted lognormal (SLN) as a better model of the failure time of individual wires. We will show that the SLN is well justified because it matches other more detailed and more physical models, such as the multilognormal. We will also show that the SLN exhibits the right behavior for long wires. Finally, we will provide an estimation methodology by which the parameters of the SLN can be estimated from failure data. Finally, the analysis will be extended to large metal layers where the advantages of using SLN over LN will be clearly demonstrated.
{"title":"A statistical model for electromigration failures","authors":"Gilbert Yoh, F. Najm","doi":"10.1109/ISQED.2000.838852","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838852","url":null,"abstract":"The lognormal has been traditionally used to model the failure time distribution of electromigration failures. However, when used to estimate the failure of large metal layers, it leads to a clear disagreement with established empirical data. To resolve this problem, we propose to use a shifted lognormal (SLN) as a better model of the failure time of individual wires. We will show that the SLN is well justified because it matches other more detailed and more physical models, such as the multilognormal. We will also show that the SLN exhibits the right behavior for long wires. Finally, we will provide an estimation methodology by which the parameters of the SLN can be estimated from failure data. Finally, the analysis will be extended to large metal layers where the advantages of using SLN over LN will be clearly demonstrated.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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