Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838856
J. Yuan
Advances in wireless communications and information processing systems require implementation of very high performance electronic systems. In recent years, SiGe heterojunction bipolar transistors (HBTs) have emerged as one of the leading contenders to satisfy these demands. The low emitter-base turn-on voltage and device scaling significantly reduce power consumption in circuit operation, while maintaining high speed. With the increasing demand placed on voice and data communications, transmitting, receiving and processing information at high frequencies and high speeds, the use of SiGe bipolar transistors becomes increasingly important.
{"title":"Overview of SiGe technology modeling and application","authors":"J. Yuan","doi":"10.1109/ISQED.2000.838856","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838856","url":null,"abstract":"Advances in wireless communications and information processing systems require implementation of very high performance electronic systems. In recent years, SiGe heterojunction bipolar transistors (HBTs) have emerged as one of the leading contenders to satisfy these demands. The low emitter-base turn-on voltage and device scaling significantly reduce power consumption in circuit operation, while maintaining high speed. With the increasing demand placed on voice and data communications, transmitting, receiving and processing information at high frequencies and high speeds, the use of SiGe bipolar transistors becomes increasingly important.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132529993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838864
A. Fontanelli, L. Arnone, R. Branca, Giorgio Mastrorocco
Trends in silicon process and packaging technologies require a tighter integration among manufacturing steps historically well distinct. It is becoming increasingly difficult to design and manufacture the most complex systems-on-a-chip (SOC) without a unified approach which allows taking into account the relationship between the package and the integrated circuits (IC) design flows. We present a new methodology, able to convey board- and package-related information into the classical IC design flow and vice versa. This is the key to ensure the physical implementation is correct the first time, meeting high-density and high-speed design challenges. ICPack (IC & Package Design Integration) is a flexible and adaptable EDA environment, Java- and Web-based, which aims at reducing the number of iterations required to meet the design objectives in terms of quality, reliability, productivity and time to qualification.
{"title":"Early addressing IC and package relationship allows an overall better quality of complex SOC","authors":"A. Fontanelli, L. Arnone, R. Branca, Giorgio Mastrorocco","doi":"10.1109/ISQED.2000.838864","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838864","url":null,"abstract":"Trends in silicon process and packaging technologies require a tighter integration among manufacturing steps historically well distinct. It is becoming increasingly difficult to design and manufacture the most complex systems-on-a-chip (SOC) without a unified approach which allows taking into account the relationship between the package and the integrated circuits (IC) design flows. We present a new methodology, able to convey board- and package-related information into the classical IC design flow and vice versa. This is the key to ensure the physical implementation is correct the first time, meeting high-density and high-speed design challenges. ICPack (IC & Package Design Integration) is a flexible and adaptable EDA environment, Java- and Web-based, which aims at reducing the number of iterations required to meet the design objectives in terms of quality, reliability, productivity and time to qualification.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124710952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838865
K. Shimazaki, H. Tsujikawa, Seijiro Kojima, Shouzou Hirano
EMI (electromagnetic interference) noise has become a more significant problem in high-speed electronic systems. To analyze EMI problems, LSIs should be analysed carefully as the source of EMI noise. However, as the circuit size of the LSIs becomes larger, it becomes more difficult to analyze the noise of these circuits by using a transistor-level simulator. Thus designers need a simulator that covers full-chip size for noise analysis. In this paper, we propose a new EMI noise simulation methodology that uses a gate-level representation for the first time. The noise from the logic gates is simply modeled by a FFT process based on the superimposed triangular current waveform. Because of the compactness of the model, we can reduce the computation dramatically and accomplish a large simulation. Furthermore, we developed a prototype simulator 'LEMINGS' to demonstrate the proposed method for conventional ASIC design flows. The experimental results show that our new EMI analysis method has achieved an outstanding performance, a high capacity to simulate the whole design and a high accuracy that is equivalent to the transistor-level simulator. Information obtained from LEMINGS can also help designers to improve the LSI and electronic systems' design quality.
{"title":"LEMINGS: LSI's EMI-noise analysis with gate level simulator","authors":"K. Shimazaki, H. Tsujikawa, Seijiro Kojima, Shouzou Hirano","doi":"10.1109/ISQED.2000.838865","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838865","url":null,"abstract":"EMI (electromagnetic interference) noise has become a more significant problem in high-speed electronic systems. To analyze EMI problems, LSIs should be analysed carefully as the source of EMI noise. However, as the circuit size of the LSIs becomes larger, it becomes more difficult to analyze the noise of these circuits by using a transistor-level simulator. Thus designers need a simulator that covers full-chip size for noise analysis. In this paper, we propose a new EMI noise simulation methodology that uses a gate-level representation for the first time. The noise from the logic gates is simply modeled by a FFT process based on the superimposed triangular current waveform. Because of the compactness of the model, we can reduce the computation dramatically and accomplish a large simulation. Furthermore, we developed a prototype simulator 'LEMINGS' to demonstrate the proposed method for conventional ASIC design flows. The experimental results show that our new EMI analysis method has achieved an outstanding performance, a high capacity to simulate the whole design and a high accuracy that is equivalent to the transistor-level simulator. Information obtained from LEMINGS can also help designers to improve the LSI and electronic systems' design quality.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129238408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838882
Mely Chen Chi, Shih-Hsu Huang
In the deep submicron era, an ASIC chip may contain millions of gates and have the requirements of low power and high performance. The ability to construct multiple clock trees effectively is very important. A clock tree design methodology is presented. Firstly, we conducted many clock tree synthesis experiments, which explored various configurations of clock tree structure and layouts. A guide for clock tree synthesis is then generated. By applying this guidance, the clock tree design procedure in ASIC design is simplified and the design time is shortened. The clock skews are within the expected range. This methodology has been used to implement clock trees on the chips designed in the Computer and Communications Research Laboratories. Our experience shows that for single clock trees the intra-clock skew is confined within 0.1 ns in one design pass for 0.35 /spl mu/m CMOS technology chips. For multiple clock trees, which are originated from the same clock source, the inter-clock skew may also be controlled easily. This design methodology is proven to be a reliable method to implement clock trees on ASIC chips.
{"title":"A reliable clock tree design methodology for ASIC designs","authors":"Mely Chen Chi, Shih-Hsu Huang","doi":"10.1109/ISQED.2000.838882","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838882","url":null,"abstract":"In the deep submicron era, an ASIC chip may contain millions of gates and have the requirements of low power and high performance. The ability to construct multiple clock trees effectively is very important. A clock tree design methodology is presented. Firstly, we conducted many clock tree synthesis experiments, which explored various configurations of clock tree structure and layouts. A guide for clock tree synthesis is then generated. By applying this guidance, the clock tree design procedure in ASIC design is simplified and the design time is shortened. The clock skews are within the expected range. This methodology has been used to implement clock trees on the chips designed in the Computer and Communications Research Laboratories. Our experience shows that for single clock trees the intra-clock skew is confined within 0.1 ns in one design pass for 0.35 /spl mu/m CMOS technology chips. For multiple clock trees, which are originated from the same clock source, the inter-clock skew may also be controlled easily. This design methodology is proven to be a reliable method to implement clock trees on ASIC chips.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116788383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISQED.2000.838881
G. Bai, S. Bobba, I. Hajj
This paper presents a new input-independent method for finding the maximum voltage drop of the power bus in digital VLSI circuits. The method relies on expressing the voltage at the power bus nodes in terms of gate currents using sensitivity analysis. Circuit timing information and circuit functionality are used to find maximum simultaneous switching and upper bounds on maximum voltage drop at a given node over a clock cycle. The effects of primary inputs misalignment and statistical variation in the circuit delays on maximum voltage drop are automatically included in our method. HSPICE exhaustive simulation results on 3 by 3 and 4 by 4 multipliers are used to validate our work.
{"title":"Power bus maximum voltage drop in digital VLSI circuits","authors":"G. Bai, S. Bobba, I. Hajj","doi":"10.1109/ISQED.2000.838881","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838881","url":null,"abstract":"This paper presents a new input-independent method for finding the maximum voltage drop of the power bus in digital VLSI circuits. The method relies on expressing the voltage at the power bus nodes in terms of gate currents using sensitivity analysis. Circuit timing information and circuit functionality are used to find maximum simultaneous switching and upper bounds on maximum voltage drop at a given node over a clock cycle. The effects of primary inputs misalignment and statistical variation in the circuit delays on maximum voltage drop are automatically included in our method. HSPICE exhaustive simulation results on 3 by 3 and 4 by 4 multipliers are used to validate our work.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125715421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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