Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838898
G. Yee, T. Thorp, Ron Christopherson, Ban P. Wang, C. Sechen
This paper describes an algorithm and automated physical design methodology for noise sensitive dynamic circuits using a systematic shielding strategy to reduce capacitive coupling. As process technology, scales, the wire width and spacing become smaller, while wire thickness is proportionately higher. This results in increasing capacitive coupling between neighboring wires, which increases wire propagation delay and crosstalk of neighboring the wires. More importantly, coupled noise or crosstalk can affect the functionality of noise sensitive receivers. Thus, for noise sensitive datapath and control blocks, shielding signals from each other has become a necessary for implementing reliable circuits. The methodology and tool described in this paper were used to reduce the design time of domino logic control blocks in the UltraSparcIII/sup TM/ microprocessor. The two blocks reported here had delays half that of their static CMOS counterparts, the same area as the static design, capacitive coupling noise of less than 5% of VDD, and were designed in record time using the tools.
{"title":"An automated shielding algorithm and tool for dynamic circuits","authors":"G. Yee, T. Thorp, Ron Christopherson, Ban P. Wang, C. Sechen","doi":"10.1109/ISQED.2000.838898","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838898","url":null,"abstract":"This paper describes an algorithm and automated physical design methodology for noise sensitive dynamic circuits using a systematic shielding strategy to reduce capacitive coupling. As process technology, scales, the wire width and spacing become smaller, while wire thickness is proportionately higher. This results in increasing capacitive coupling between neighboring wires, which increases wire propagation delay and crosstalk of neighboring the wires. More importantly, coupled noise or crosstalk can affect the functionality of noise sensitive receivers. Thus, for noise sensitive datapath and control blocks, shielding signals from each other has become a necessary for implementing reliable circuits. The methodology and tool described in this paper were used to reduce the design time of domino logic control blocks in the UltraSparcIII/sup TM/ microprocessor. The two blocks reported here had delays half that of their static CMOS counterparts, the same area as the static design, capacitive coupling noise of less than 5% of VDD, and were designed in record time using the tools.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127724756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838869
M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni
The increasing densities in growing size circuits leads us to consider as an issue noise problems such as crosstalk, switching noise, electromigration and substrate injection. Noise safety must be a clear objective in design tools, whose development must then include circuit models for the analysis of noise phenomena. This paper points out a proposed methodology in the development of new models and related tools that focus on the noise immunity of circuit design.
{"title":"Noise safety design methodologies","authors":"M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, M. Zamboni","doi":"10.1109/ISQED.2000.838869","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838869","url":null,"abstract":"The increasing densities in growing size circuits leads us to consider as an issue noise problems such as crosstalk, switching noise, electromigration and substrate injection. Noise safety must be a clear objective in design tools, whose development must then include circuit models for the analysis of noise phenomena. This paper points out a proposed methodology in the development of new models and related tools that focus on the noise immunity of circuit design.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130266844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838892
M. Mechaik
Electrical characterization and performance of signal routing layers is analyzed for ceramic pin grid array (CPGA) packages. Numerical values are tabulated for crosstalk, and attenuation for signal The implications of layer routability, signal width, and signal thickness are also analyzed. A table of numerical values for the differential impedance of a dual microstrip line is also obtained.
{"title":"Electrical characterization of signal routability and performance [CPGAs]","authors":"M. Mechaik","doi":"10.1109/ISQED.2000.838892","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838892","url":null,"abstract":"Electrical characterization and performance of signal routing layers is analyzed for ceramic pin grid array (CPGA) packages. Numerical values are tabulated for crosstalk, and attenuation for signal The implications of layer routability, signal width, and signal thickness are also analyzed. A table of numerical values for the differential impedance of a dual microstrip line is also obtained.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134325463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838854
R. Zafalon, M. Rossello, E. Macii, M. Poncino
Several approaches that address early power estimation in digital design have been published in the last few years. Most of them are based on a fast (coarse) logic synthesis step, in order to analyze power on the mapped gate-level netlist. In this paper we present a summary of RTPow, a proprietary tool dealing with the RT-level power estimation, relying on a top-down estimation engine that does not perform any type of on-the-fly logic synthesis when analyzing the HDL description. In addition, a set of power macromodeling capabilities have been developed as well, to enable an effective power budgeting and automatic bottom-up power characterization methodology.
{"title":"Power macromodeling for a high quality RT-level power estimation","authors":"R. Zafalon, M. Rossello, E. Macii, M. Poncino","doi":"10.1109/ISQED.2000.838854","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838854","url":null,"abstract":"Several approaches that address early power estimation in digital design have been published in the last few years. Most of them are based on a fast (coarse) logic synthesis step, in order to analyze power on the mapped gate-level netlist. In this paper we present a summary of RTPow, a proprietary tool dealing with the RT-level power estimation, relying on a top-down estimation engine that does not perform any type of on-the-fly logic synthesis when analyzing the HDL description. In addition, a set of power macromodeling capabilities have been developed as well, to enable an effective power budgeting and automatic bottom-up power characterization methodology.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132911166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838883
P. H. Chen, S. Malkani, C. Peng, James Lin
This paper describes three ways to fix antenna problems: (1) diode dropping, (2) jumper insertion, and (3) diode dropping with extension wires. Basic principles of these methods are compared and results are presented. Diode structures, SPIC simulation, and diode slicing are also discussed in this paper.
{"title":"Fixing antenna problem by dynamic diode dropping and jumper insertion","authors":"P. H. Chen, S. Malkani, C. Peng, James Lin","doi":"10.1109/ISQED.2000.838883","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838883","url":null,"abstract":"This paper describes three ways to fix antenna problems: (1) diode dropping, (2) jumper insertion, and (3) diode dropping with extension wires. Basic principles of these methods are compared and results are presented. Diode structures, SPIC simulation, and diode slicing are also discussed in this paper.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122790301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838940
Shen Lin, N. Chang, Sam Nakagawa
In this paper, based on simulations of top-level interconnects and CMOS devices of industrial 0.18 /spl mu/m technology, the rules to screen out those inductive interconnects requiring more accurate RLC considerations, and the victim wires potentially having significant inductive noises are developed. The presented criteria constitute a tighter self-inductance screening rule than those found in previously published work. The 2/spl times/mutual inductance screening rule is presented and verified. The differences in on-chip inductance consideration, the significant frequency of a trapezoidal pulse, and the circuit modeling of on-chip inductance are also discussed.
{"title":"Quick on-chip self- and mutual-inductance screen","authors":"Shen Lin, N. Chang, Sam Nakagawa","doi":"10.1109/ISQED.2000.838940","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838940","url":null,"abstract":"In this paper, based on simulations of top-level interconnects and CMOS devices of industrial 0.18 /spl mu/m technology, the rules to screen out those inductive interconnects requiring more accurate RLC considerations, and the victim wires potentially having significant inductive noises are developed. The presented criteria constitute a tighter self-inductance screening rule than those found in previously published work. The 2/spl times/mutual inductance screening rule is presented and verified. The differences in on-chip inductance consideration, the significant frequency of a trapezoidal pulse, and the circuit modeling of on-chip inductance are also discussed.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115161576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838876
D. Protheroe, F. Pessolano
This paper proposes a method for defining the quality of a digital system in terms of measurable parameters of both the specification and a subsequent implementation of the design. Initially, software quality metrics are reviewed together with their application to hardware description languages. Metrics relating to circuit implementations are then discussed, such as device and testing costs, reliability, etc. A set of metrics are then proposed and evaluated for a range of VHDL specifications and the circuits resulting from logic synthesis. Initial results indicate that there is a strong correlation between specification and circuit metrics, so that their ratio may be used as a measure of design quality. Further work is proposed in order to validate the measure over a larger number of examples.
{"title":"An objective measure of digital system design quality","authors":"D. Protheroe, F. Pessolano","doi":"10.1109/ISQED.2000.838876","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838876","url":null,"abstract":"This paper proposes a method for defining the quality of a digital system in terms of measurable parameters of both the specification and a subsequent implementation of the design. Initially, software quality metrics are reviewed together with their application to hardware description languages. Metrics relating to circuit implementations are then discussed, such as device and testing costs, reliability, etc. A set of metrics are then proposed and evaluated for a range of VHDL specifications and the circuits resulting from logic synthesis. Initial results indicate that there is a strong correlation between specification and circuit metrics, so that their ratio may be used as a measure of design quality. Further work is proposed in order to validate the measure over a larger number of examples.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116052784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838873
R. Ubar, J. Raik
A new hierarchical approach to test generation for digital systems is proposed. Three levels of modeling are exploited: high-level Decision Diagrams (DD) for module test planning and system constraints generation, low-level Boolean differential equations for fault constraints generation, and medium-level Binary DDs for local test pattern generation for modules under the derived set of constraints. The proposed method of generating fault constraints the first time allows us to handle faults which increase the number of states in sequential circuits. Combining the high-level efficiency of solving complex deterministic search problems and medium-level accuracy of fault "transportation" analysis with low-level exact fault activation allows us to reach high efficiency in test generation, and high test quality on the other hand. Experimental results compared to the known test generators are provided for demonstrating the high efficiency of test generation achieved by the proposed approach.
{"title":"Efficient hierarchical approach to test generation for digital systems","authors":"R. Ubar, J. Raik","doi":"10.1109/ISQED.2000.838873","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838873","url":null,"abstract":"A new hierarchical approach to test generation for digital systems is proposed. Three levels of modeling are exploited: high-level Decision Diagrams (DD) for module test planning and system constraints generation, low-level Boolean differential equations for fault constraints generation, and medium-level Binary DDs for local test pattern generation for modules under the derived set of constraints. The proposed method of generating fault constraints the first time allows us to handle faults which increase the number of states in sequential circuits. Combining the high-level efficiency of solving complex deterministic search problems and medium-level accuracy of fault \"transportation\" analysis with low-level exact fault activation allows us to reach high efficiency in test generation, and high test quality on the other hand. Experimental results compared to the known test generators are provided for demonstrating the high efficiency of test generation achieved by the proposed approach.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133706944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838860
L. Józwiak
Modern microelectronic technology enables implementation of a complete complex information processing system on a single chip. Progress in microelectronic technology is extremely fast and it is outstripping the system designers' abilities to make use of the created opportunities. The complexity and quality of the microelectronics-based systems as well as their design and production cost and time tend to be more limited by the design methods and tools than by the microelectronic technology. Substantial improvement can only be achieved through development and application of a new generation of more suitable design paradigms, methods and tools. In this paper, some new opportunities and difficulties related to the system-on-a-chip technology are overviewed, the nature of the complex system design problems is analyzed and an appropriate quality-driven system design methodology is proposed and discussed. Some important implications of the modern quality concepts for design modeling, design exploration techniques and tools, design decision making, design reuse and design validation are also discussed.
{"title":"Quality-driven system-on-a-chip design","authors":"L. Józwiak","doi":"10.1109/ISQED.2000.838860","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838860","url":null,"abstract":"Modern microelectronic technology enables implementation of a complete complex information processing system on a single chip. Progress in microelectronic technology is extremely fast and it is outstripping the system designers' abilities to make use of the created opportunities. The complexity and quality of the microelectronics-based systems as well as their design and production cost and time tend to be more limited by the design methods and tools than by the microelectronic technology. Substantial improvement can only be achieved through development and application of a new generation of more suitable design paradigms, methods and tools. In this paper, some new opportunities and difficulties related to the system-on-a-chip technology are overviewed, the nature of the complex system design problems is analyzed and an appropriate quality-driven system design methodology is proposed and discussed. Some important implications of the modern quality concepts for design modeling, design exploration techniques and tools, design decision making, design reuse and design validation are also discussed.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132918759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838897
M. Worsman, M. Wong, Yim-Shu Lee
Equivalent faults inhibit fault diagnosis by producing indistinguishable test metric measurements. Removal of conditions causing the equivalence in response exhibited by such faults is necessary, if fault diagnosis quality is to be improved. As Design for-Testability (DFT) methodology aims to deliver a degree of fault diagnosis substantially greater than that obtainable testing unassisted by on-chip test specific hardware, designing a DFT scheme with minimal fault equivalence is an issue to be addressed. Presented is a set of simple and inexpensive tests, applied pre-simulation, for identifying catastrophic resistive component faults that cause numerical equivalent d.c. test model responses. Using a biquadratic notch filter modified with a novel DFT scheme, we demonstrate that equivalent fault information is a useful initial measure for assessing the potential increase in fault diagnosis quality obtainable with a DFT scheme.
{"title":"A pre-simulation measure of d.c. design-for-testability fault diagnosis quality","authors":"M. Worsman, M. Wong, Yim-Shu Lee","doi":"10.1109/ISQED.2000.838897","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838897","url":null,"abstract":"Equivalent faults inhibit fault diagnosis by producing indistinguishable test metric measurements. Removal of conditions causing the equivalence in response exhibited by such faults is necessary, if fault diagnosis quality is to be improved. As Design for-Testability (DFT) methodology aims to deliver a degree of fault diagnosis substantially greater than that obtainable testing unassisted by on-chip test specific hardware, designing a DFT scheme with minimal fault equivalence is an issue to be addressed. Presented is a set of simple and inexpensive tests, applied pre-simulation, for identifying catastrophic resistive component faults that cause numerical equivalent d.c. test model responses. Using a biquadratic notch filter modified with a novel DFT scheme, we demonstrate that equivalent fault information is a useful initial measure for assessing the potential increase in fault diagnosis quality obtainable with a DFT scheme.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133188031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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