Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838930
K. Aingaran, F. Klass, Chin-Man Kim, C. Amir, Joydeep Mitra, E. You, Jamil Mohd, Sai-keung Dong
Although digital circuits are inherently immune to most sources of noise, the scaling of supply voltages and MOSFET threshold voltages has resulted in lowered noise margins. Most CMOS circuits continue to have considerable immunity to power supply and substrate noise even with the aggressive scaling used today. However, the effect of capacitive coupling noise has become a major concern for designers of deep sub-micron circuits. Compounding these problems is the fact that there are very few, if any, reliable tools for detecting coupling noise on large and complex digital circuits. This paper discusses the coupling noise analysis method used during the development of the UltraSPARC-III microprocessor. A good noise analysis strategy should not only pick out the noise violations in a design but also be robust enough to run a sensitivity analysis, with the aim of recommending solutions to the problems found. The model presented places emphasis on its scalability to large datasets, such as the design database of modern high performance microprocessors, comprising of several million transistors. A hierarchical approach to achieve this is proposed and the capacity achieved is illustrated with results on real circuits.
{"title":"Coupling noise analysis for VLSI and ULSI circuits","authors":"K. Aingaran, F. Klass, Chin-Man Kim, C. Amir, Joydeep Mitra, E. You, Jamil Mohd, Sai-keung Dong","doi":"10.1109/ISQED.2000.838930","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838930","url":null,"abstract":"Although digital circuits are inherently immune to most sources of noise, the scaling of supply voltages and MOSFET threshold voltages has resulted in lowered noise margins. Most CMOS circuits continue to have considerable immunity to power supply and substrate noise even with the aggressive scaling used today. However, the effect of capacitive coupling noise has become a major concern for designers of deep sub-micron circuits. Compounding these problems is the fact that there are very few, if any, reliable tools for detecting coupling noise on large and complex digital circuits. This paper discusses the coupling noise analysis method used during the development of the UltraSPARC-III microprocessor. A good noise analysis strategy should not only pick out the noise violations in a design but also be robust enough to run a sensitivity analysis, with the aim of recommending solutions to the problems found. The model presented places emphasis on its scalability to large datasets, such as the design database of modern high performance microprocessors, comprising of several million transistors. A hierarchical approach to achieve this is proposed and the capacity achieved is illustrated with results on real circuits.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116514049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838908
G. Ben-Yaacov, Larry Bjork, Edward P. Stone
This paper describes the initial efforts of two quality groups, one representing EDA software suppliers, and the other representing their major customers, to understand and systematically improve EDA industry quality, as perceived by the customers. The groups continue to work toward this goal, and have reached agreement on several issues, including a defect classification system by severity, eight quality metrics, and a plan for reporting and publishing industry average quality trends using these metrics.
{"title":"Advancing customer-perceived quality in the EDA industry","authors":"G. Ben-Yaacov, Larry Bjork, Edward P. Stone","doi":"10.1109/ISQED.2000.838908","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838908","url":null,"abstract":"This paper describes the initial efforts of two quality groups, one representing EDA software suppliers, and the other representing their major customers, to understand and systematically improve EDA industry quality, as perceived by the customers. The groups continue to work toward this goal, and have reached agreement on several issues, including a defect classification system by severity, eight quality metrics, and a plan for reporting and publishing industry average quality trends using these metrics.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122670383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838863
I. Koren
The objectives of good chip design have traditionally included issues like performance, power and reliability. Yield is rarely considered during the design process, except in the design of memory ICs, where specific defect-tolerance techniques are incorporated into the architecture for yield enhancement. In order to make the case for establishing yield as another design objective we must first prove that a chip's yield cannot only be affected, but consistently improved, by decisions made during the design process.
{"title":"Should yield be a design objective?","authors":"I. Koren","doi":"10.1109/ISQED.2000.838863","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838863","url":null,"abstract":"The objectives of good chip design have traditionally included issues like performance, power and reliability. Yield is rarely considered during the design process, except in the design of memory ICs, where specific defect-tolerance techniques are incorporated into the architecture for yield enhancement. In order to make the case for establishing yield as another design objective we must first prove that a chip's yield cannot only be affected, but consistently improved, by decisions made during the design process.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121389778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838926
M. Mechaik
Three multi-layer stackups are analyzed for ceramic packages with solid planes and thin substrates. The advantages and disadvantages of using decoupling capacitors for high performance applications are also analyzed. This paper shows how different package stackups, number of power and ground planes, and the number of routing layers affect the performance of the packaging device and subsequently the current consumption demanded by the simultaneously switching drivers and core logic on the microprocessor. A multi-layer ceramic package with solid planes and thin substrates is analyzed to provide a complete characterization of the system made of drivers, core logic, package, and motherboard. Such analysis serves as a basic building block for setting a criteria on different package designs.
{"title":"Effects of package stackups on microprocessor performance","authors":"M. Mechaik","doi":"10.1109/ISQED.2000.838926","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838926","url":null,"abstract":"Three multi-layer stackups are analyzed for ceramic packages with solid planes and thin substrates. The advantages and disadvantages of using decoupling capacitors for high performance applications are also analyzed. This paper shows how different package stackups, number of power and ground planes, and the number of routing layers affect the performance of the packaging device and subsequently the current consumption demanded by the simultaneously switching drivers and core logic on the microprocessor. A multi-layer ceramic package with solid planes and thin substrates is analyzed to provide a complete characterization of the system made of drivers, core logic, package, and motherboard. Such analysis serves as a basic building block for setting a criteria on different package designs.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"9 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125683737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838893
S. Rochel, N. Nagaraj
Metal electromigration affects the functionality and lifetime of integrated circuits. This problem has so far been addressed by imposing simple design rules and current density limits during the design and validation of ICs, but a barrier has been reached in UDSM. State-of-the-art, high-speed circuit designs require current densities in signal nets close to the material limits to meet timing budgets. The validation of electromigration reliability becomes imperative. This paper introduces analysis techniques specifically for signal net electromigration validation at the full-chip level. Results of this analysis provide feedback to the designer to permit engineering decisions between opposing design constraints with consideration to electromigration reliability.
{"title":"Full-chip signal interconnect analysis for electromigration reliability","authors":"S. Rochel, N. Nagaraj","doi":"10.1109/ISQED.2000.838893","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838893","url":null,"abstract":"Metal electromigration affects the functionality and lifetime of integrated circuits. This problem has so far been addressed by imposing simple design rules and current density limits during the design and validation of ICs, but a barrier has been reached in UDSM. State-of-the-art, high-speed circuit designs require current densities in signal nets close to the material limits to meet timing budgets. The validation of electromigration reliability becomes imperative. This paper introduces analysis techniques specifically for signal net electromigration validation at the full-chip level. Results of this analysis provide feedback to the designer to permit engineering decisions between opposing design constraints with consideration to electromigration reliability.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132062714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838862
B. Prince
Memory blocks have the basic quality requirements shared by all IP blocks. These include transferability between manufacturing areas, transferability from the original technology to the next generation technology, compatibility with available design tools, and qualified manufacturability in available wafer fabs. In addition to these general quality requirements, issues specific to memory blocks need to be considered. These include: memory type and cell for the specific implementation; memory technology generation to be used; cost issues such as requirements for special process modules; design issues such as choice of array compiler or use of predefined memory blocks; yield improvement issues such as redundancy type and implementation; test issues including BIST or direct memory access, special memory test requirements such as bit mapping, and availability of memory testers; reliability issues such as disturb problems, burn-in requirements and soft error considerations; architectural issues such as on-chip bandwidth access, pitch matching of array logic, and refresh implementation. This paper discusses these memory specific quality issues and the trade-offs involved.
{"title":"Quality memory blocks-balancing the trade-offs","authors":"B. Prince","doi":"10.1109/ISQED.2000.838862","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838862","url":null,"abstract":"Memory blocks have the basic quality requirements shared by all IP blocks. These include transferability between manufacturing areas, transferability from the original technology to the next generation technology, compatibility with available design tools, and qualified manufacturability in available wafer fabs. In addition to these general quality requirements, issues specific to memory blocks need to be considered. These include: memory type and cell for the specific implementation; memory technology generation to be used; cost issues such as requirements for special process modules; design issues such as choice of array compiler or use of predefined memory blocks; yield improvement issues such as redundancy type and implementation; test issues including BIST or direct memory access, special memory test requirements such as bit mapping, and availability of memory testers; reliability issues such as disturb problems, burn-in requirements and soft error considerations; architectural issues such as on-chip bandwidth access, pitch matching of array logic, and refresh implementation. This paper discusses these memory specific quality issues and the trade-offs involved.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117319749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838902
E. Aas
Design quality metrics will be defined in terms of the probability that a completed design satisfies its specifications The definition rests on the concept of atomic design operations, and is by nature canonical. It is shown that this definition is truly analogous to test quality, leading to a unified model of test and design quality. Another important aspect of the design is its efficiency, related to design parameters. The metrics of design efficiency may be expressed as a cost function, and different design proposals may be evaluated against estimated design efficiency. Examples from several years of graduate level student design experiments will be given in order to demonstrate the usefulness of these metrics.
{"title":"Design quality and design efficiency; definitions, metrics and relevant design experiences","authors":"E. Aas","doi":"10.1109/ISQED.2000.838902","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838902","url":null,"abstract":"Design quality metrics will be defined in terms of the probability that a completed design satisfies its specifications The definition rests on the concept of atomic design operations, and is by nature canonical. It is shown that this definition is truly analogous to test quality, leading to a unified model of test and design quality. Another important aspect of the design is its efficiency, related to design parameters. The metrics of design efficiency may be expressed as a cost function, and different design proposals may be evaluated against estimated design efficiency. Examples from several years of graduate level student design experiments will be given in order to demonstrate the usefulness of these metrics.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"6 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133912845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838868
W. Kang, B. Potts, R. Hokinson, J. Riley, D. Doman, F. Cano, N. Nagaraj, Noel Durrant
Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team's primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-by-construction such as reliability-constraint place-and-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented.
{"title":"Enabling DIR (Designing-In-Reliability) through CAD capabilities","authors":"W. Kang, B. Potts, R. Hokinson, J. Riley, D. Doman, F. Cano, N. Nagaraj, Noel Durrant","doi":"10.1109/ISQED.2000.838868","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838868","url":null,"abstract":"Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team's primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-by-construction such as reliability-constraint place-and-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124501772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838889
W. Kurmicz
This work is the first step toward the Internet-based "virtual manufacturing". The problem of statistical design of IC cells, with special emphasis on analog IC design and device mismatch is addressed. A statistical CMOS process/device simulator accessible via user friendly Web interface has been developed. The process is simulated in a statistical (Monte Carlo-type) loop with all kinds of variations, inter-die and intra-die, random and deterministic, taken into account. The input data includes device channel dimensions, orientations and positions on the chip. A statistical sample of chips is simulated. The outputs include SPICE model files with individual models for all simulated devices and a statistical file. A statistical post processor provides statistics of model parameters including correlations and mismatch. These data can be used for verification of manufacturability and optimization of IC designs. The user does not need to know the processing details and has no access to confidential manufacturing-related information.
{"title":"Internet-based virtual manufacturing: a verification tool for IC designs","authors":"W. Kurmicz","doi":"10.1109/ISQED.2000.838889","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838889","url":null,"abstract":"This work is the first step toward the Internet-based \"virtual manufacturing\". The problem of statistical design of IC cells, with special emphasis on analog IC design and device mismatch is addressed. A statistical CMOS process/device simulator accessible via user friendly Web interface has been developed. The process is simulated in a statistical (Monte Carlo-type) loop with all kinds of variations, inter-die and intra-die, random and deterministic, taken into account. The input data includes device channel dimensions, orientations and positions on the chip. A statistical sample of chips is simulated. The outputs include SPICE model files with individual models for all simulated devices and a statistical file. A statistical post processor provides statistics of model parameters including correlations and mismatch. These data can be used for verification of manufacturability and optimization of IC designs. The user does not need to know the processing details and has no access to confidential manufacturing-related information.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127834988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838910
T. Sakurai
Lowering operating voltage, V/sub DD/, is a key to low-power CMOS digital VLSIs. In order to complete a certain task in a required time and in order to keep leakage current within a tolerable level in the low V/sub DD/ designs, V/sub DD/ and V/sub TH/ control is obligatory. This paper covers several of the schemes including multi-V/sub TH/, variable V/sub TH/, multi-V/sub DD/ and variable V/sub DD/ to achieve low-power systems. Circuit level ideas for software related research are described.
{"title":"Reducing power consumption of CMOS VLSI's through V/sub DD/ and V/sub TH/ control","authors":"T. Sakurai","doi":"10.1109/ISQED.2000.838910","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838910","url":null,"abstract":"Lowering operating voltage, V/sub DD/, is a key to low-power CMOS digital VLSIs. In order to complete a certain task in a required time and in order to keep leakage current within a tolerable level in the low V/sub DD/ designs, V/sub DD/ and V/sub TH/ control is obligatory. This paper covers several of the schemes including multi-V/sub TH/, variable V/sub TH/, multi-V/sub DD/ and variable V/sub DD/ to achieve low-power systems. Circuit level ideas for software related research are described.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132170161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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