In today’s day and age, power electronic components are found in all areas of an electric vehicle, from power train to motors and from battery to ancillary loads. Power converters are used to optimize energy management in an automobile. While doing the electrical design of a power converter, the thermal aspects are usually neglected causing a vast difference in the simulation and real-life application. This paper aims to show how taking thermal characteristics into account for a power converter is beneficial and how it influences the results.
{"title":"Design of Buck Converter With Control System for Electric Vehicle Using SiC Device With Thermal Loss Model","authors":"Utsav Gupta, A. Vass-Várnai","doi":"10.1115/ipack2022-97669","DOIUrl":"https://doi.org/10.1115/ipack2022-97669","url":null,"abstract":"\u0000 In today’s day and age, power electronic components are found in all areas of an electric vehicle, from power train to motors and from battery to ancillary loads. Power converters are used to optimize energy management in an automobile. While doing the electrical design of a power converter, the thermal aspects are usually neglected causing a vast difference in the simulation and real-life application. This paper aims to show how taking thermal characteristics into account for a power converter is beneficial and how it influences the results.","PeriodicalId":117260,"journal":{"name":"ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125312755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rabin Bhandari, A. Lakshminarayana, K. Sivaraju, Pratik V. Bansode, Ephrem Kejela, D. Agonafer
Detailed study of material compatibility of the various electronics packaging materials for immersion cooling is essential to understand their failure modes and reliability. The modulus and thermal expansion are critical material properties for electronics mechanical design. Substrate is a critical component of electronic package and heavily influences failure mechanism and reliability of electronics both at the package and board level. This study mainly focuses on two major challenges. The first part of the study focuses on the impact of thermal aging in dielectric fluid for single-phase immersion cooling on the non-halogenate substrate’s thermo-mechanical properties. The second part of the study is the impact of thermal aging on thermo-mechanical properties of substrate in the air. The non-halogenated low Coefficient of Thermal Expansion (CTE) bismaleimide triazine (BT) resin laminate is used for its ultra-low CTE which in turn reduce the warpage of substrate. Moreover, the substrate has high glass transition temperature and high stiffness suitable for the application which requires high heat resistance. The substrate is aged in ElectroCool EC100 dielectric fluid, and air for 720 hours at three different temperatures: 22°C, 50°C, and 75°C. The complex modulus is characterized before and after aging for both parts and compared.
{"title":"Impact of Immersion Cooling on Thermomechanical Properties of Non-Halogenated Substrate","authors":"Rabin Bhandari, A. Lakshminarayana, K. Sivaraju, Pratik V. Bansode, Ephrem Kejela, D. Agonafer","doi":"10.1115/ipack2022-97423","DOIUrl":"https://doi.org/10.1115/ipack2022-97423","url":null,"abstract":"\u0000 Detailed study of material compatibility of the various electronics packaging materials for immersion cooling is essential to understand their failure modes and reliability. The modulus and thermal expansion are critical material properties for electronics mechanical design. Substrate is a critical component of electronic package and heavily influences failure mechanism and reliability of electronics both at the package and board level. This study mainly focuses on two major challenges. The first part of the study focuses on the impact of thermal aging in dielectric fluid for single-phase immersion cooling on the non-halogenate substrate’s thermo-mechanical properties. The second part of the study is the impact of thermal aging on thermo-mechanical properties of substrate in the air. The non-halogenated low Coefficient of Thermal Expansion (CTE) bismaleimide triazine (BT) resin laminate is used for its ultra-low CTE which in turn reduce the warpage of substrate. Moreover, the substrate has high glass transition temperature and high stiffness suitable for the application which requires high heat resistance. The substrate is aged in ElectroCool EC100 dielectric fluid, and air for 720 hours at three different temperatures: 22°C, 50°C, and 75°C. The complex modulus is characterized before and after aging for both parts and compared.","PeriodicalId":117260,"journal":{"name":"ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116333083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vibin Shalom Simon, Himanshu Modi, K. Sivaraju, Pratik V. Bansode, S. Saini, Pradeep Shahi, S. Karajgikar, V. Mulay, D. Agonafer
Due to increased use of high-performance computing in datacenters to cater to huge workloads, old low-performance compute servers must be replaced endlessly with high-performance compute servers. Traditional air-cooling systems are insufficient to provision and run the servers in optimal conditions as the datacenter thermal footprint or rack density grows, resulting in thermal throttling. To sustain the growing needs, Rear Door Heat Exchangers (RDHx) are deployed in existing datacenters along with peripheral Computer Room Air Handling/Conditioning (CRAH/CRAC) units. RDHx transfers heat from the rear end of the racks and rejects it into the facility’s chilled water. This study will demonstrate the suitability of RDHx for low density as well as high density rack applications. A baseline CFD model had a generic datacenter layout with peripheral CRAH/CRAC units and RDHx. Several case studies were conducted by varying the air and liquid inlet temperatures for rack and RDHx, respectively. We also compared active and passive modes of operating RDHx while server fans provide flowrate based on the IT inlet temperature. The paper will also discuss the feasibility of designing a datacenter with only RDHx and no peripheral CRAC/CRAH units while maintaining the thermal envelop. The research will also provide a guideline in implementing RDHx based on the heat load and server design.
{"title":"Feasibility Study of Rear Door Heat Exchanger for a High Capacity Data Center","authors":"Vibin Shalom Simon, Himanshu Modi, K. Sivaraju, Pratik V. Bansode, S. Saini, Pradeep Shahi, S. Karajgikar, V. Mulay, D. Agonafer","doi":"10.1115/ipack2022-97494","DOIUrl":"https://doi.org/10.1115/ipack2022-97494","url":null,"abstract":"Due to increased use of high-performance computing in datacenters to cater to huge workloads, old low-performance compute servers must be replaced endlessly with high-performance compute servers. Traditional air-cooling systems are insufficient to provision and run the servers in optimal conditions as the datacenter thermal footprint or rack density grows, resulting in thermal throttling. To sustain the growing needs, Rear Door Heat Exchangers (RDHx) are deployed in existing datacenters along with peripheral Computer Room Air Handling/Conditioning (CRAH/CRAC) units. RDHx transfers heat from the rear end of the racks and rejects it into the facility’s chilled water. This study will demonstrate the suitability of RDHx for low density as well as high density rack applications. A baseline CFD model had a generic datacenter layout with peripheral CRAH/CRAC units and RDHx. Several case studies were conducted by varying the air and liquid inlet temperatures for rack and RDHx, respectively. We also compared active and passive modes of operating RDHx while server fans provide flowrate based on the IT inlet temperature. The paper will also discuss the feasibility of designing a datacenter with only RDHx and no peripheral CRAC/CRAH units while maintaining the thermal envelop. The research will also provide a guideline in implementing RDHx based on the heat load and server design.","PeriodicalId":117260,"journal":{"name":"ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134235823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micro-scale Sn-Ag-Cu (SAC) solder interconnects have oligocrystalline grain structure with one to few grains in each solder joint. As well documented in the literature, SAC solder joint consisting of 96.5% β-Sn is highly anisotropic due to the inherently anisotropic mechanical behavior of β-Sn. Therefore, each joint exhibits a unique mechanical response. However, due to the complexities in the quantification of microstructure and finite element (FE) modeling methodology, engineers typically model solder joints as homogenous isotropic structures with directionally averaged mechanical properties. These approximations cause inaccurate prediction of strain levels in the solder and in turn leads to uncertainties in lifetime predictions. A key challenge in grain-scale anisotropic modeling of solder joints, is the lack of widely accepted anisotropic inelastic mechanical properties of solder grains in the literature. The goal of this paper is to determine rate-independent plastic constitutive behavior of Anisotropic SAC305 single grains. Monotonic tensile and shear tests are conducted at room temperature on a set of single-grain SAC305 solder joints. The grain structure for each test specimen is characterized with EBSD and finite element modeling is used to iteratively extract model constants for Hill-Holloman continuum plasticity model, which utilizes Hill’s anisotropic yield criterion along with a Holloman Power-Law plasticity model to represent each grain. Plastic deformation in the grain boundaries is ignored.
{"title":"Anisotropic Plastic Constitutive Properties of SAC305 Single Crystal Solder Joints","authors":"A. Deshpande, Q. Jiang, A. Dasgupta","doi":"10.1115/ipack2022-94505","DOIUrl":"https://doi.org/10.1115/ipack2022-94505","url":null,"abstract":"\u0000 Micro-scale Sn-Ag-Cu (SAC) solder interconnects have oligocrystalline grain structure with one to few grains in each solder joint. As well documented in the literature, SAC solder joint consisting of 96.5% β-Sn is highly anisotropic due to the inherently anisotropic mechanical behavior of β-Sn. Therefore, each joint exhibits a unique mechanical response. However, due to the complexities in the quantification of microstructure and finite element (FE) modeling methodology, engineers typically model solder joints as homogenous isotropic structures with directionally averaged mechanical properties. These approximations cause inaccurate prediction of strain levels in the solder and in turn leads to uncertainties in lifetime predictions. A key challenge in grain-scale anisotropic modeling of solder joints, is the lack of widely accepted anisotropic inelastic mechanical properties of solder grains in the literature.\u0000 The goal of this paper is to determine rate-independent plastic constitutive behavior of Anisotropic SAC305 single grains. Monotonic tensile and shear tests are conducted at room temperature on a set of single-grain SAC305 solder joints. The grain structure for each test specimen is characterized with EBSD and finite element modeling is used to iteratively extract model constants for Hill-Holloman continuum plasticity model, which utilizes Hill’s anisotropic yield criterion along with a Holloman Power-Law plasticity model to represent each grain. Plastic deformation in the grain boundaries is ignored.","PeriodicalId":117260,"journal":{"name":"ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134471145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Ortega, Carol Caceres, U. Uras, Deogratius Kisitu, Uschas Chowdhury, Vahideh Radmard, A. Heydari
Cold plates are at the heart of pumped liquid cooling systems. In this paper, we report on combined experimental, analytical, and computational efforts to characterize and model the thermal performance of advanced cold plates in order to establish their performance limits. A novel effectiveness-NTU formulation is introduced that models the fin array as a secondary “pseudo-fluid” such that accurate crossflow effectiveness models can be utilized to model the cold plates using well-known formulations. Experimental measurements and conjugate CFD simulations were made on cold plates with fin and channel features of order 100 um with water-propylene glycol (PG) mixtures as coolants. We show that for a fixed fin geometry, the best thermal performance, regardless of the pressure drop, is achieved when the flow rate is high enough to approach the low NTU convective limit which occurs for NTU approaching zero. For the model cold plate evaluated in this study, the lowest thermal resistance achieved at a flow rate of 4 LPM was 0.01 C/W, and the convective limit was 0.005 C/W. However, for a fixed pressure drop, the optimal cold plate should be designed to meet its TDP at the highest possible effectiveness in which the lower limit of thermal resistance is the advective limit achieved for NTU > 7. For the tested cold plate the advective limit for the thermal resistance is 0.003 C/W, but this limit can only be achieved if it is practically feasible to increase the surface area and heat transfer coefficient to maximize NTU for a targeted TDP.
{"title":"Determination of the Thermal Performance Limits for Single Phase Liquid Cooling Using an Improved Effectiveness-NTU Cold Plate Model","authors":"A. Ortega, Carol Caceres, U. Uras, Deogratius Kisitu, Uschas Chowdhury, Vahideh Radmard, A. Heydari","doi":"10.1115/ipack2022-97421","DOIUrl":"https://doi.org/10.1115/ipack2022-97421","url":null,"abstract":"\u0000 Cold plates are at the heart of pumped liquid cooling systems. In this paper, we report on combined experimental, analytical, and computational efforts to characterize and model the thermal performance of advanced cold plates in order to establish their performance limits. A novel effectiveness-NTU formulation is introduced that models the fin array as a secondary “pseudo-fluid” such that accurate crossflow effectiveness models can be utilized to model the cold plates using well-known formulations. Experimental measurements and conjugate CFD simulations were made on cold plates with fin and channel features of order 100 um with water-propylene glycol (PG) mixtures as coolants. We show that for a fixed fin geometry, the best thermal performance, regardless of the pressure drop, is achieved when the flow rate is high enough to approach the low NTU convective limit which occurs for NTU approaching zero. For the model cold plate evaluated in this study, the lowest thermal resistance achieved at a flow rate of 4 LPM was 0.01 C/W, and the convective limit was 0.005 C/W. However, for a fixed pressure drop, the optimal cold plate should be designed to meet its TDP at the highest possible effectiveness in which the lower limit of thermal resistance is the advective limit achieved for NTU > 7. For the tested cold plate the advective limit for the thermal resistance is 0.003 C/W, but this limit can only be achieved if it is practically feasible to increase the surface area and heat transfer coefficient to maximize NTU for a targeted TDP.","PeriodicalId":117260,"journal":{"name":"ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124121386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jet impingement cooling is an advanced thermal management technique for high heat flux applications. Standard configurations include single, axisymmetric jets with orifice, slot, or pipe nozzles. This choice in nozzle shape, number of jets and jet inclination greatly influences the turbulence generated caused by fluid entrainment due to differences in initial velocity profiles and location of secondary stagnation points. Regarding high power electronics with integrated jet impingement schemes, turbulence and heat transfer rates must be optimized to meet the extreme cooling requirements. In this study, the heat transfer rates of dual inclined converging jets are investigated experimentally. Emphasis is placed on the comparison of different jet schemes with respect to geometrical parameters including nozzle pitch, incline angle, and nozzle-to-targe plate spacing. A parametric experimental investigation is performed as a point of comparison using a modular, additively manufactured jet setup. Thermal energy is applied to an aluminum base plate using a 200 W resistive heater to emulate a hot spot generated in high-power electronics. It is observed that the introduction of inclined and parallel jets can have the simultaneous effect of increasing heat transfer and creating more predictable heat transfer.
{"title":"Dual Converging Jets for Enhanced Liquid Impingement Cooling","authors":"Reece Whitt, R. Estrella, D. Huitink","doi":"10.1115/ipack2022-96635","DOIUrl":"https://doi.org/10.1115/ipack2022-96635","url":null,"abstract":"\u0000 Jet impingement cooling is an advanced thermal management technique for high heat flux applications. Standard configurations include single, axisymmetric jets with orifice, slot, or pipe nozzles. This choice in nozzle shape, number of jets and jet inclination greatly influences the turbulence generated caused by fluid entrainment due to differences in initial velocity profiles and location of secondary stagnation points. Regarding high power electronics with integrated jet impingement schemes, turbulence and heat transfer rates must be optimized to meet the extreme cooling requirements. In this study, the heat transfer rates of dual inclined converging jets are investigated experimentally. Emphasis is placed on the comparison of different jet schemes with respect to geometrical parameters including nozzle pitch, incline angle, and nozzle-to-targe plate spacing. A parametric experimental investigation is performed as a point of comparison using a modular, additively manufactured jet setup. Thermal energy is applied to an aluminum base plate using a 200 W resistive heater to emulate a hot spot generated in high-power electronics. It is observed that the introduction of inclined and parallel jets can have the simultaneous effect of increasing heat transfer and creating more predictable heat transfer.","PeriodicalId":117260,"journal":{"name":"ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129213285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Developing component attachment techniques with low-temperature processing is required to implement flexible hybrid electronics utilizing additively printed circuits. Additive electronics may be made on several substrates such as Polyimide, PET, and PEN. While polyimide may be processed at standard reflow temperatures, thermally stabilized PET and PEN require a peak processing temperature of less than 150 °C. A variety of novel solder materials have emerged that can be worked at temperatures lower than 150 degrees Celsius. The low temperature also provides the added benefits of less warpage, less energy use, and a reduced carbon footprint. The process-performance-reliability relationships for the printed magnetically oriented conductive adhesive on the printed conductive metallization have been investigated in this work. Young’s modulus of the bonding material has been evaluated using the nanoindentation technique. Characterization of the frequency-performance of surface mount component attachments on additively printed metallization was used to study electrical and mechanical performance. The performance of the interconnects was compared to the COTS predefined tolerance limits. In flex-to-install applications, the reliability and performance deterioration of additively printed circuits have been measured. The interconnection reliability is also tested for dynamic flexing conditions for cycles to failure. Optical imaging has also been used to investigate the intermetallics at the interface of conductive adhesive and additively printed circuits.
{"title":"Mechanical and Electrical Properties of Additively Printed Circuits With Magnetically Orientated Anisotropic Conductive Adhesive Attachment for FHE Applications","authors":"P. Lall, Jinesh Narangaparambil, Scott Miller","doi":"10.1115/ipack2022-97456","DOIUrl":"https://doi.org/10.1115/ipack2022-97456","url":null,"abstract":"\u0000 Developing component attachment techniques with low-temperature processing is required to implement flexible hybrid electronics utilizing additively printed circuits. Additive electronics may be made on several substrates such as Polyimide, PET, and PEN. While polyimide may be processed at standard reflow temperatures, thermally stabilized PET and PEN require a peak processing temperature of less than 150 °C. A variety of novel solder materials have emerged that can be worked at temperatures lower than 150 degrees Celsius. The low temperature also provides the added benefits of less warpage, less energy use, and a reduced carbon footprint. The process-performance-reliability relationships for the printed magnetically oriented conductive adhesive on the printed conductive metallization have been investigated in this work. Young’s modulus of the bonding material has been evaluated using the nanoindentation technique. Characterization of the frequency-performance of surface mount component attachments on additively printed metallization was used to study electrical and mechanical performance. The performance of the interconnects was compared to the COTS predefined tolerance limits. In flex-to-install applications, the reliability and performance deterioration of additively printed circuits have been measured. The interconnection reliability is also tested for dynamic flexing conditions for cycles to failure. Optical imaging has also been used to investigate the intermetallics at the interface of conductive adhesive and additively printed circuits.","PeriodicalId":117260,"journal":{"name":"ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126722210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Emerging thermal management policies for high-power processors often rely on the temperature readings from on-chip digital thermal sensors. However, thermal sensors may not accurately measure the maximum temperature on chip. This is because thermal hot spots are typically located near important CPU components, limiting the power and physical space available for thermal sensors. As a result, sensors usually need to be placed some distance away from the hot spots. Additionally, on-chip thermal sensors also operate within an error margin, which could under/over-estimate the temperature readings. Prior methods introduced machine learning algorithms for predicting chip temperatures trained with Infrared (IR) camera measurements of the physical chip to construct accurate on-chip thermal profiles. While such methods produce an accurate model, the thermal imaging setup is expensive, and it can be time-consuming to collect and process the temperature data for a physical chip. This paper proposes a simulation-based method of using a machine learning regression model to predict a chip’s full temperature map based solely on the current power usage, core utilization, and measured sensor temperatures. The proposed model is trained and evaluated based on data generated from performance, power, and thermal simulations for the Intel i7 6950× Extreme Edition processor. When running a set of realistic benchmarks, this model is able to accurately predict temperatures within a root mean squared error (RMSE) of less than 0.25°C. The proposed model’s accuracy is not affected by the placement of the thermal sensors, and the maximum error resulting from the placement of thermal sensors is less than 0.12° C. For a real-world application, the proposed model can be trained based on realistic simulation or measured temperature data, then be applied to predict a chip’s temperature map in real-time. Using actual temperature data measured from an IR camera is more accurate, but the IR camera setup itself is expensive. Using simulation data to train the machine learning model is low-cost and more practical than temperature prediction based on an expensive IR camera.
{"title":"Machine Learning and Simulation Based Temperature Prediction on High-Performance Processors","authors":"Carlton Knox, Zihao Yuan, A. Coskun","doi":"10.1115/ipack2022-96751","DOIUrl":"https://doi.org/10.1115/ipack2022-96751","url":null,"abstract":"\u0000 Emerging thermal management policies for high-power processors often rely on the temperature readings from on-chip digital thermal sensors. However, thermal sensors may not accurately measure the maximum temperature on chip. This is because thermal hot spots are typically located near important CPU components, limiting the power and physical space available for thermal sensors. As a result, sensors usually need to be placed some distance away from the hot spots. Additionally, on-chip thermal sensors also operate within an error margin, which could under/over-estimate the temperature readings. Prior methods introduced machine learning algorithms for predicting chip temperatures trained with Infrared (IR) camera measurements of the physical chip to construct accurate on-chip thermal profiles. While such methods produce an accurate model, the thermal imaging setup is expensive, and it can be time-consuming to collect and process the temperature data for a physical chip. This paper proposes a simulation-based method of using a machine learning regression model to predict a chip’s full temperature map based solely on the current power usage, core utilization, and measured sensor temperatures. The proposed model is trained and evaluated based on data generated from performance, power, and thermal simulations for the Intel i7 6950× Extreme Edition processor. When running a set of realistic benchmarks, this model is able to accurately predict temperatures within a root mean squared error (RMSE) of less than 0.25°C. The proposed model’s accuracy is not affected by the placement of the thermal sensors, and the maximum error resulting from the placement of thermal sensors is less than 0.12° C. For a real-world application, the proposed model can be trained based on realistic simulation or measured temperature data, then be applied to predict a chip’s temperature map in real-time. Using actual temperature data measured from an IR camera is more accurate, but the IR camera setup itself is expensive. Using simulation data to train the machine learning model is low-cost and more practical than temperature prediction based on an expensive IR camera.","PeriodicalId":117260,"journal":{"name":"ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"37 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130261179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In electronic packaging, lead-free solders often experience fatigue failures due to thermal-mechanical cyclic stress and strain caused by changing temperatures and mismatches in thermal expansion coefficients. As a result, damage accumulates in the solder joints including plastic deformation, crack initiation, crack propagation, and finally failure occur. In our previous work, changes in the mechanical behavior of SAC305 lead free solder due to prior damage accumulation was investigated. Circular cross-section solder specimens were first reflowed, and these samples were then mechanically cycled for various durations using a Micro-Mechanical tester. Monotonic stress-strain tests were subsequently conducted on the prior cycled samples to characterize the change in mechanical behavior occurring in the solder due to damage accumulation. Using the data from these tests, we were able to characterize and quantify the cycling induced damage through the observed degradations of several mechanical properties (initial elastic modulus, yield stress, and ultimate tensile strength) with the amount of prior cycling. In the current work, we have extended the experimental work in our prior studies on SAC305 to examine the evolution of the creep response due to prior damage accumulation. In the experimental testing, small uniaxial cylindrical samples of SAC305 solder were prepared and reflowed in a reflow oven. These specimens were then mechanically cycled under several different sets of conditions to induce various levels of damage in the samples. In particular, four levels of initial damage per cycle were considered (ΔW = 0.25, 0.50, 0.75 and 1.00 MJ/m3), as well as three cycling temperatures (T = 25, 100, and 125 °C). For each of these damage levels per cycle, various durations of cycling were applied (e.g., 0, 50, 100, 300, and 600 cycles). This test matrix generated a large set of prior damaged samples, where the damage had been accumulated at different rates (different damage amounts per cycle), different cycling temperatures, and for different durations. In this paper, selected results obtained for isothermal mechanical cycling at T = 25 °C will be presented in detail. Creep tests were performed on the prior damage samples at room temperature and several stress levels including σ = 10.0, 12.0, and 15.0 MPa. The changes in the steady state secondary creep rate were then evaluated and plotted versus the duration of cycling for the various applied levels of damage per cycle. Exponential empirical models were found to fit the material property degradations well for any one set of conditions. More importantly, it was found that the total energy dissipation that had occurred in the sample (sum of ΔW for all cycles) could be used as a governing failure variable independent of the damage level applied during each cycle. In particular, all of the creep rate data for a selected stress level were modeled well using a single degradation curve independent of that ra
{"title":"Effects of Mechanical Cycling Induced Damage on the Creep Response of SAC305 Solder","authors":"G. R. Mazumder, M. A. Haq, J. Suhling, P. Lall","doi":"10.1115/ipack2022-93878","DOIUrl":"https://doi.org/10.1115/ipack2022-93878","url":null,"abstract":"\u0000 In electronic packaging, lead-free solders often experience fatigue failures due to thermal-mechanical cyclic stress and strain caused by changing temperatures and mismatches in thermal expansion coefficients. As a result, damage accumulates in the solder joints including plastic deformation, crack initiation, crack propagation, and finally failure occur. In our previous work, changes in the mechanical behavior of SAC305 lead free solder due to prior damage accumulation was investigated. Circular cross-section solder specimens were first reflowed, and these samples were then mechanically cycled for various durations using a Micro-Mechanical tester. Monotonic stress-strain tests were subsequently conducted on the prior cycled samples to characterize the change in mechanical behavior occurring in the solder due to damage accumulation. Using the data from these tests, we were able to characterize and quantify the cycling induced damage through the observed degradations of several mechanical properties (initial elastic modulus, yield stress, and ultimate tensile strength) with the amount of prior cycling.\u0000 In the current work, we have extended the experimental work in our prior studies on SAC305 to examine the evolution of the creep response due to prior damage accumulation. In the experimental testing, small uniaxial cylindrical samples of SAC305 solder were prepared and reflowed in a reflow oven. These specimens were then mechanically cycled under several different sets of conditions to induce various levels of damage in the samples. In particular, four levels of initial damage per cycle were considered (ΔW = 0.25, 0.50, 0.75 and 1.00 MJ/m3), as well as three cycling temperatures (T = 25, 100, and 125 °C). For each of these damage levels per cycle, various durations of cycling were applied (e.g., 0, 50, 100, 300, and 600 cycles). This test matrix generated a large set of prior damaged samples, where the damage had been accumulated at different rates (different damage amounts per cycle), different cycling temperatures, and for different durations. In this paper, selected results obtained for isothermal mechanical cycling at T = 25 °C will be presented in detail.\u0000 Creep tests were performed on the prior damage samples at room temperature and several stress levels including σ = 10.0, 12.0, and 15.0 MPa. The changes in the steady state secondary creep rate were then evaluated and plotted versus the duration of cycling for the various applied levels of damage per cycle. Exponential empirical models were found to fit the material property degradations well for any one set of conditions. More importantly, it was found that the total energy dissipation that had occurred in the sample (sum of ΔW for all cycles) could be used as a governing failure variable independent of the damage level applied during each cycle. In particular, all of the creep rate data for a selected stress level were modeled well using a single degradation curve independent of that ra","PeriodicalId":117260,"journal":{"name":"ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114678380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Lall, Madhu L. Kasturi, Haotian Wu, Edward Davis
The automotive underhood electronics are subjected to temperatures in the range of 150 to 200°C for prolonged periods. The coefficient of thermal expansion mismatch between the chip and the substrate results in the fatigue-failure of solder joints when operating at high temperatures. Underfills provide extra support to the flip-chip bumps, enhancing the fatigue life and reducing the solder joint strains. Models and material degradation data are needed for the underfills exposed to high temperatures. The effect of the evolution of non-linear constitutive behavior of underfills on the solder balls and the study of the evolution of viscoelastic behavior of underfills have not been studied. In this paper, the evolution of underfill properties over 1-year has been measured for two underfills at sustained high-temperature operation. The aging data has been reported at 30, 60, 120, 240, and 360 days at 100°C, 125°C, and 150°C. The effect of non-linear property (Prony series) evolution of underfills on the FCBGA (Flip Chip Ball Grid Array) package reliability has been evaluated. The quarter FCBGA package is modeled from −40°C to 125°C. The results show that the flip-chip plastic work per unit volume of pristine-linear-elastic constitute model underfill FCBGA was much lower compared to pristine-viscoelastic underfill model FCBGA. Results show the importance of considering the non-linear underfill properties instead of linear properties.
{"title":"Modeling Underfill Degradation and Its Effect on FCBGA Package Reliability Under High-Temperature Operation","authors":"P. Lall, Madhu L. Kasturi, Haotian Wu, Edward Davis","doi":"10.1115/ipack2022-97433","DOIUrl":"https://doi.org/10.1115/ipack2022-97433","url":null,"abstract":"\u0000 The automotive underhood electronics are subjected to temperatures in the range of 150 to 200°C for prolonged periods. The coefficient of thermal expansion mismatch between the chip and the substrate results in the fatigue-failure of solder joints when operating at high temperatures. Underfills provide extra support to the flip-chip bumps, enhancing the fatigue life and reducing the solder joint strains. Models and material degradation data are needed for the underfills exposed to high temperatures. The effect of the evolution of non-linear constitutive behavior of underfills on the solder balls and the study of the evolution of viscoelastic behavior of underfills have not been studied. In this paper, the evolution of underfill properties over 1-year has been measured for two underfills at sustained high-temperature operation. The aging data has been reported at 30, 60, 120, 240, and 360 days at 100°C, 125°C, and 150°C. The effect of non-linear property (Prony series) evolution of underfills on the FCBGA (Flip Chip Ball Grid Array) package reliability has been evaluated. The quarter FCBGA package is modeled from −40°C to 125°C. The results show that the flip-chip plastic work per unit volume of pristine-linear-elastic constitute model underfill FCBGA was much lower compared to pristine-viscoelastic underfill model FCBGA. Results show the importance of considering the non-linear underfill properties instead of linear properties.","PeriodicalId":117260,"journal":{"name":"ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128265593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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