Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815443
Jannah Al-Hashimi, Seepsa Tomoq, K. Abugharbieh, Yazan Al-Qudah, Mustafa Shihadeh
This work presents a methodology to analyze defects in an SRAM cell based on electrical testing which can help improve yield of semiconductor ICs. It uses an algorithm that utilizes fuzzy logic techniques to post process electrical measurements to analyze the point(s) of failure. To model the impact of opens and shorts in the SRAM cell, a number of resistors were added in various locations in the schematic of a cell where a defect can occur. Simulations were run where these resistors were shorted or opened according to their location(s) and the defect(s) they represent. The work was conducted using 28 nm technology device models. Design and simulations were done using Synopsys transistor level Custom Designer software that includes HSPICE. MATLAB was used to implement the fuzzy logic based algorithm to post process the electrical simulations' results. The algorithm presented in this paper can be modified for different technology nodes and can be used by design and yield engineers in industry.
{"title":"An SRAM based testing methodology for yield analysis of semiconductor ICs","authors":"Jannah Al-Hashimi, Seepsa Tomoq, K. Abugharbieh, Yazan Al-Qudah, Mustafa Shihadeh","doi":"10.1109/ICECS.2013.6815443","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815443","url":null,"abstract":"This work presents a methodology to analyze defects in an SRAM cell based on electrical testing which can help improve yield of semiconductor ICs. It uses an algorithm that utilizes fuzzy logic techniques to post process electrical measurements to analyze the point(s) of failure. To model the impact of opens and shorts in the SRAM cell, a number of resistors were added in various locations in the schematic of a cell where a defect can occur. Simulations were run where these resistors were shorted or opened according to their location(s) and the defect(s) they represent. The work was conducted using 28 nm technology device models. Design and simulations were done using Synopsys transistor level Custom Designer software that includes HSPICE. MATLAB was used to implement the fuzzy logic based algorithm to post process the electrical simulations' results. The algorithm presented in this paper can be modified for different technology nodes and can be used by design and yield engineers in industry.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114217714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815365
Amna Al Dahak, L. Seneviratne, J. Dias
Autonomous robot exploration and map building for unknown environments is essential in a wide range of applications such as search and rescue, surveillance, military and other high risk scenarios. As the robot starts exploring its surroundings, it accumulatively builds a partial map of the environment composing of the areas that are currently known by the robot. In this work we present a new exploration and mapping solution that will capture the environment structure geometrically. The proposed Triangulation-Based exploration maps the environment using the Dynamic Triangulation Tree structure (DTT) developed in this study. Using triangles to store the geometry of the environment will significantly reduce the storage space required when compared to the occupancy grids used in many exploration and map building solutions. The efficiency of the proposed mapping structure is validated experimentally through simulations.
{"title":"Mapping for unknown environment using incremental triangulation","authors":"Amna Al Dahak, L. Seneviratne, J. Dias","doi":"10.1109/ICECS.2013.6815365","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815365","url":null,"abstract":"Autonomous robot exploration and map building for unknown environments is essential in a wide range of applications such as search and rescue, surveillance, military and other high risk scenarios. As the robot starts exploring its surroundings, it accumulatively builds a partial map of the environment composing of the areas that are currently known by the robot. In this work we present a new exploration and mapping solution that will capture the environment structure geometrically. The proposed Triangulation-Based exploration maps the environment using the Dynamic Triangulation Tree structure (DTT) developed in this study. Using triangles to store the geometry of the environment will significantly reduce the storage space required when compared to the occupancy grids used in many exploration and map building solutions. The efficiency of the proposed mapping structure is validated experimentally through simulations.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117190050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815493
S. Chouhan, K. Halonen
The RF rectifier is a key component in wireless sensor networks and RFID applications. It converts the input RF signal into DC voltage to power up a system. Low settling time is important for efficiently acquiring DC voltage in an RFID system. The settling time is defined as the time required by the rectifier to reach the maximum stable DC voltage for a given load condition. The main focus of this work is to reduce the settling time required by the rectifier. Settling time is one of the performance limitations of a rectifier due to the threshold voltage of the transistor. In this work, we are proposing the use of DTMOS (Dynamic Threshold MOSFET) architecture in the design of RF to DC rectifier. In DTMOS, gate and body are tied together, which dynamically alters the threshold voltage to suit the operating state of the circuit. We implemented the DTMOS architecture in a self Vth cancellation (SVC) scheme based rectifier. Settling time is considered as the performance parameter. Results demonstrate that settling time of the modified SVC rectifier is less than 50%, as compared to that of the conventional BTMOS(body terminal tied to source terminal) based SVC rectifier structure. The rectifiers have been implemented using the 180nm standard CMOS technology and the simulations were performed using spectre simulator.
{"title":"The DTMOS based UHF RF to DC conversion","authors":"S. Chouhan, K. Halonen","doi":"10.1109/ICECS.2013.6815493","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815493","url":null,"abstract":"The RF rectifier is a key component in wireless sensor networks and RFID applications. It converts the input RF signal into DC voltage to power up a system. Low settling time is important for efficiently acquiring DC voltage in an RFID system. The settling time is defined as the time required by the rectifier to reach the maximum stable DC voltage for a given load condition. The main focus of this work is to reduce the settling time required by the rectifier. Settling time is one of the performance limitations of a rectifier due to the threshold voltage of the transistor. In this work, we are proposing the use of DTMOS (Dynamic Threshold MOSFET) architecture in the design of RF to DC rectifier. In DTMOS, gate and body are tied together, which dynamically alters the threshold voltage to suit the operating state of the circuit. We implemented the DTMOS architecture in a self Vth cancellation (SVC) scheme based rectifier. Settling time is considered as the performance parameter. Results demonstrate that settling time of the modified SVC rectifier is less than 50%, as compared to that of the conventional BTMOS(body terminal tied to source terminal) based SVC rectifier structure. The rectifiers have been implemented using the 180nm standard CMOS technology and the simulations were performed using spectre simulator.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815487
E. Ashenafi, M. Chowdhury
Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator comprises of a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes very large chip area hampering the scaling down process. These limitations make passive inductor based on-chip regulator very unattractive for system-on-a-chip (SOC) and multi-/many-core environments. To facilitate complete on-chip integration of a voltage regulator this paper presents an active circuit technique to replace the passive inductor and emulate the inductive behavior required in a buck convertor. The proposed scheme combines a linear and a switching voltage regulator together in single active circuit. The amalgamation of the two regulators will obviate the need to use a physical inductor, instead utilize a second-generation current conveyor based active filter along with an inverter switch and a voltage follower current source. Design of the circuit is demonstrated using 0.5μm technology on Cadence Virtuoso tools. Simulation results and MATLAB plots are provided to verify the proposed design.
{"title":"Active on-chip voltage regulator based on second generation current conveyor","authors":"E. Ashenafi, M. Chowdhury","doi":"10.1109/ICECS.2013.6815487","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815487","url":null,"abstract":"Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator comprises of a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes very large chip area hampering the scaling down process. These limitations make passive inductor based on-chip regulator very unattractive for system-on-a-chip (SOC) and multi-/many-core environments. To facilitate complete on-chip integration of a voltage regulator this paper presents an active circuit technique to replace the passive inductor and emulate the inductive behavior required in a buck convertor. The proposed scheme combines a linear and a switching voltage regulator together in single active circuit. The amalgamation of the two regulators will obviate the need to use a physical inductor, instead utilize a second-generation current conveyor based active filter along with an inverter switch and a voltage follower current source. Design of the circuit is demonstrated using 0.5μm technology on Cadence Virtuoso tools. Simulation results and MATLAB plots are provided to verify the proposed design.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"381 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124693815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815336
S. Salahuddin, V. Kursun
The degraded data stability, write ability, and increased leakage power consumption of static random-access memory (SRAM) cells have become primary design concerns with CMOS technology scaling into the sub-22nm channel lengths. A new gate-underlap-engineered eight-transistor SRAM cell is proposed in this paper for stronger data stability, enhanced write ability, and suppressed leakage power consumption in FinFET memory circuits. Gate-underlap lengths of the pull-up and pull-down transistors in cross-coupled inverters of the proposed SRAM cell are elongated and tuned for providing superior electrical characteristics in FinFET memory circuits. With the proposed gate-underlap engineered eight-FinFET SRAM cell, the read static noise margin is enhanced by up to 71.1%, the write voltage margin is increased by up to 29.7%, and the leakage power consumption is reduced by up to 91.8% while maintaining similar layout area as compared to the conventional eight-FinFET SRAM cells in a 15nm FinFET technology.
{"title":"Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption","authors":"S. Salahuddin, V. Kursun","doi":"10.1109/ICECS.2013.6815336","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815336","url":null,"abstract":"The degraded data stability, write ability, and increased leakage power consumption of static random-access memory (SRAM) cells have become primary design concerns with CMOS technology scaling into the sub-22nm channel lengths. A new gate-underlap-engineered eight-transistor SRAM cell is proposed in this paper for stronger data stability, enhanced write ability, and suppressed leakage power consumption in FinFET memory circuits. Gate-underlap lengths of the pull-up and pull-down transistors in cross-coupled inverters of the proposed SRAM cell are elongated and tuned for providing superior electrical characteristics in FinFET memory circuits. With the proposed gate-underlap engineered eight-FinFET SRAM cell, the read static noise margin is enhanced by up to 71.1%, the write voltage margin is increased by up to 29.7%, and the leakage power consumption is reduced by up to 91.8% while maintaining similar layout area as compared to the conventional eight-FinFET SRAM cells in a 15nm FinFET technology.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125032803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815571
D. Schinianakis, T. Stouraitis
An RNS implementation of Barrett's modular multiplication algorithm is presented in this paper. Existing algorithms for RNS modular multiplication employ Montgomery's technique. An algorithmic comparison with such state-of-the-art solutions shows that the proposed algorithm may reduce the total number of modular multiplications per RNS modular multiplication by 33%-50%.
{"title":"An RNS modular multiplication algorithm","authors":"D. Schinianakis, T. Stouraitis","doi":"10.1109/ICECS.2013.6815571","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815571","url":null,"abstract":"An RNS implementation of Barrett's modular multiplication algorithm is presented in this paper. Existing algorithms for RNS modular multiplication employ Montgomery's technique. An algorithmic comparison with such state-of-the-art solutions shows that the proposed algorithm may reduce the total number of modular multiplications per RNS modular multiplication by 33%-50%.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123478745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815529
F. Hassan, S. Khorbotly
A family of recursive exponential linear phase FIR filters was proposed in a previous work. The switching and reset method was subsequently used to create a stable implementation of an otherwise unstable pole-zero cancelation in those filters. In this work, we propose an improved switching and reset architecture that delivers the same results at a reduced hardware cost. The main advantage of this architecture lies in its ability to implement an exponential filter, of an arbitrary order N using only six adders, four multipliers, four multiplexers, and N +3 registers. Various order Exponential filters are synthesized on FPGA devices in both the improved and the traditional architectures. The results show that the improved architecture provides significant savings in both logic elements and register count, especially for higher values of N. Simulation results show that the impulse and step responses of the presented implementation accurately approximate the responses of a traditional, non-recursive exponential filter.
{"title":"An improved switching and reset architecture for linear phase recursive filters","authors":"F. Hassan, S. Khorbotly","doi":"10.1109/ICECS.2013.6815529","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815529","url":null,"abstract":"A family of recursive exponential linear phase FIR filters was proposed in a previous work. The switching and reset method was subsequently used to create a stable implementation of an otherwise unstable pole-zero cancelation in those filters. In this work, we propose an improved switching and reset architecture that delivers the same results at a reduced hardware cost. The main advantage of this architecture lies in its ability to implement an exponential filter, of an arbitrary order N using only six adders, four multipliers, four multiplexers, and N +3 registers. Various order Exponential filters are synthesized on FPGA devices in both the improved and the traditional architectures. The results show that the improved architecture provides significant savings in both logic elements and register count, especially for higher values of N. Simulation results show that the impulse and step responses of the presented implementation accurately approximate the responses of a traditional, non-recursive exponential filter.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122128886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815359
Sara Al Maeeni, S. Muhaidat, I. Abualhaol
Research on non-coherent detection for cooperative communications is at an early stage and many fundamental problems are still open. We will be working on an important open problems in broadband cooperative wireless communications. A novel non-coherent detection scheme for a multi-relay cooperative orthogonal frequency division multiplexing (OFDM) wireless system is investigated. We consider a distributed space-time block code (STBC) system over time-varying fading channels, in which source-relay, relay-destination, and source-destination links experience different Doppler spreads. Simulation results demonstrate that the recursive decoder achieves sufficient results even under quasi-static fading assumption.
{"title":"Efficient non-coherent detection techniques for broadband cooperative networks","authors":"Sara Al Maeeni, S. Muhaidat, I. Abualhaol","doi":"10.1109/ICECS.2013.6815359","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815359","url":null,"abstract":"Research on non-coherent detection for cooperative communications is at an early stage and many fundamental problems are still open. We will be working on an important open problems in broadband cooperative wireless communications. A novel non-coherent detection scheme for a multi-relay cooperative orthogonal frequency division multiplexing (OFDM) wireless system is investigated. We consider a distributed space-time block code (STBC) system over time-varying fading channels, in which source-relay, relay-destination, and source-destination links experience different Doppler spreads. Simulation results demonstrate that the recursive decoder achieves sufficient results even under quasi-static fading assumption.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126138326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815485
D. Gan, G. Cai, J. Dias, L. Seneviratne
This paper presents the work on attitude control of quad-rotor UAVs applying an intuitive kinematics representation, called rotation vector. There are three elements in the rotation vector which has clear physical meaning of the rotations and avoids the singularity problem of Euler angles and the unity norm constraint problem of quaternions. Basic definition of the rotation vector and its relation with the object body angle velocity is introduced and used in the 6DOF quadrotor dynamics. Based on the property that the rotation vector rate is equivalent to the body angle velocity when the rotation is small, a simple and intuitive attitude reference is proposed. A proportional-derivative (PD) law is used by integrating the new attitude reference for the attitude control of quad-rotor UAVs. Simulation results prove the efficiency of the new method which provides a new model with intuitive physical meaning for quadrotor UAVs.
{"title":"Attitude control of quad-rotor UAVs using an intuitive kinematics model","authors":"D. Gan, G. Cai, J. Dias, L. Seneviratne","doi":"10.1109/ICECS.2013.6815485","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815485","url":null,"abstract":"This paper presents the work on attitude control of quad-rotor UAVs applying an intuitive kinematics representation, called rotation vector. There are three elements in the rotation vector which has clear physical meaning of the rotations and avoids the singularity problem of Euler angles and the unity norm constraint problem of quaternions. Basic definition of the rotation vector and its relation with the object body angle velocity is introduced and used in the 6DOF quadrotor dynamics. Based on the property that the rotation vector rate is equivalent to the body angle velocity when the rotation is small, a simple and intuitive attitude reference is proposed. A proportional-derivative (PD) law is used by integrating the new attitude reference for the attitude control of quad-rotor UAVs. Simulation results prove the efficiency of the new method which provides a new model with intuitive physical meaning for quadrotor UAVs.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"os-34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127693866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815432
A. Radwan, A. S. Mansingka, Mohammed Affan Zidan, K. Salama
This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Short-term predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%.
{"title":"On the short-term predictability of fully digital chaotic oscillators for pseudo-random number generation","authors":"A. Radwan, A. S. Mansingka, Mohammed Affan Zidan, K. Salama","doi":"10.1109/ICECS.2013.6815432","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815432","url":null,"abstract":"This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Short-term predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115817846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：