Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815529
F. Hassan, S. Khorbotly
A family of recursive exponential linear phase FIR filters was proposed in a previous work. The switching and reset method was subsequently used to create a stable implementation of an otherwise unstable pole-zero cancelation in those filters. In this work, we propose an improved switching and reset architecture that delivers the same results at a reduced hardware cost. The main advantage of this architecture lies in its ability to implement an exponential filter, of an arbitrary order N using only six adders, four multipliers, four multiplexers, and N +3 registers. Various order Exponential filters are synthesized on FPGA devices in both the improved and the traditional architectures. The results show that the improved architecture provides significant savings in both logic elements and register count, especially for higher values of N. Simulation results show that the impulse and step responses of the presented implementation accurately approximate the responses of a traditional, non-recursive exponential filter.
{"title":"An improved switching and reset architecture for linear phase recursive filters","authors":"F. Hassan, S. Khorbotly","doi":"10.1109/ICECS.2013.6815529","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815529","url":null,"abstract":"A family of recursive exponential linear phase FIR filters was proposed in a previous work. The switching and reset method was subsequently used to create a stable implementation of an otherwise unstable pole-zero cancelation in those filters. In this work, we propose an improved switching and reset architecture that delivers the same results at a reduced hardware cost. The main advantage of this architecture lies in its ability to implement an exponential filter, of an arbitrary order N using only six adders, four multipliers, four multiplexers, and N +3 registers. Various order Exponential filters are synthesized on FPGA devices in both the improved and the traditional architectures. The results show that the improved architecture provides significant savings in both logic elements and register count, especially for higher values of N. Simulation results show that the impulse and step responses of the presented implementation accurately approximate the responses of a traditional, non-recursive exponential filter.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122128886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815432
A. Radwan, A. S. Mansingka, Mohammed Affan Zidan, K. Salama
This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Short-term predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%.
{"title":"On the short-term predictability of fully digital chaotic oscillators for pseudo-random number generation","authors":"A. Radwan, A. S. Mansingka, Mohammed Affan Zidan, K. Salama","doi":"10.1109/ICECS.2013.6815432","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815432","url":null,"abstract":"This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Short-term predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115817846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815563
Chu-Hsiang Chia, Pui-Sun Lei, R. Chang, Tzu-Ying Kao
This paper presents a high-speed DC-DC converter with the adaptive DCM controller and the switch-scaling circuit using TSMC 0.18μm CMOS process. The input voltage is 1.8V and the output voltage is 1.2V. The maximum loading is 300mA and the required passive components are at nano-scale. The proposed DC-DC converter has over 80% efficiency at loading range from 50mA to 300mA. The output ripple is below 10% of the output voltage at all loadings. To minimize the power consumption, a low-power and adaptive DCM controller is proposed to increase the efficiency and also reduce the output ripple when the loading is below 150mA. When the loading is over 200mA, the switch-scaling circuit will turn on the extra power MOS to keep the efficiency. The switching frequency of the proposed converter changes from 200kHz to 50MHz, depending on the loading. The loading boundary between proposed DCM and CCM control is 150mA.
{"title":"A high-speed DC-DC converter with high efficiency at wide loading range","authors":"Chu-Hsiang Chia, Pui-Sun Lei, R. Chang, Tzu-Ying Kao","doi":"10.1109/ICECS.2013.6815563","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815563","url":null,"abstract":"This paper presents a high-speed DC-DC converter with the adaptive DCM controller and the switch-scaling circuit using TSMC 0.18μm CMOS process. The input voltage is 1.8V and the output voltage is 1.2V. The maximum loading is 300mA and the required passive components are at nano-scale. The proposed DC-DC converter has over 80% efficiency at loading range from 50mA to 300mA. The output ripple is below 10% of the output voltage at all loadings. To minimize the power consumption, a low-power and adaptive DCM controller is proposed to increase the efficiency and also reduce the output ripple when the loading is below 150mA. When the loading is over 200mA, the switch-scaling circuit will turn on the extra power MOS to keep the efficiency. The switching frequency of the proposed converter changes from 200kHz to 50MHz, depending on the loading. The loading boundary between proposed DCM and CCM control is 150mA.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127761103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815336
S. Salahuddin, V. Kursun
The degraded data stability, write ability, and increased leakage power consumption of static random-access memory (SRAM) cells have become primary design concerns with CMOS technology scaling into the sub-22nm channel lengths. A new gate-underlap-engineered eight-transistor SRAM cell is proposed in this paper for stronger data stability, enhanced write ability, and suppressed leakage power consumption in FinFET memory circuits. Gate-underlap lengths of the pull-up and pull-down transistors in cross-coupled inverters of the proposed SRAM cell are elongated and tuned for providing superior electrical characteristics in FinFET memory circuits. With the proposed gate-underlap engineered eight-FinFET SRAM cell, the read static noise margin is enhanced by up to 71.1%, the write voltage margin is increased by up to 29.7%, and the leakage power consumption is reduced by up to 91.8% while maintaining similar layout area as compared to the conventional eight-FinFET SRAM cells in a 15nm FinFET technology.
{"title":"Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption","authors":"S. Salahuddin, V. Kursun","doi":"10.1109/ICECS.2013.6815336","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815336","url":null,"abstract":"The degraded data stability, write ability, and increased leakage power consumption of static random-access memory (SRAM) cells have become primary design concerns with CMOS technology scaling into the sub-22nm channel lengths. A new gate-underlap-engineered eight-transistor SRAM cell is proposed in this paper for stronger data stability, enhanced write ability, and suppressed leakage power consumption in FinFET memory circuits. Gate-underlap lengths of the pull-up and pull-down transistors in cross-coupled inverters of the proposed SRAM cell are elongated and tuned for providing superior electrical characteristics in FinFET memory circuits. With the proposed gate-underlap engineered eight-FinFET SRAM cell, the read static noise margin is enhanced by up to 71.1%, the write voltage margin is increased by up to 29.7%, and the leakage power consumption is reduced by up to 91.8% while maintaining similar layout area as compared to the conventional eight-FinFET SRAM cells in a 15nm FinFET technology.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125032803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815453
V. Rieger, C. Brendler, Naser Pour Aryan, A. Rothermel
A compact 10-bit current-steering D/A converter in a 0.35 μm CMOS technology is presented. The DAC is designed for active pixel sensor control of a retinal implant. A new current cell has been used to minimize power consumption and reduce glitching. To guarantee monotonicity and to achieve good dynamic and static performance a segmentation level of 4-6 has been used. A triple common-centroid layout technique has been applied and an active area of 0.7 mm2 has been used. The measured differential and integral linearity errors are less than ± 0.2 LSB and ± 0.3 LSB, respectively.
{"title":"A 10-bit current-steering D/A converter for active pixel sensor control","authors":"V. Rieger, C. Brendler, Naser Pour Aryan, A. Rothermel","doi":"10.1109/ICECS.2013.6815453","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815453","url":null,"abstract":"A compact 10-bit current-steering D/A converter in a 0.35 μm CMOS technology is presented. The DAC is designed for active pixel sensor control of a retinal implant. A new current cell has been used to minimize power consumption and reduce glitching. To guarantee monotonicity and to achieve good dynamic and static performance a segmentation level of 4-6 has been used. A triple common-centroid layout technique has been applied and an active area of 0.7 mm2 has been used. The measured differential and integral linearity errors are less than ± 0.2 LSB and ± 0.3 LSB, respectively.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134419653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815548
Yogesh Dilip Save, R. Rakhi, N. D. Shambhulingayya, A. Srivastava, M. R. Das, Saket Choudhary, K. Moudgalya
In this paper, we discuss the implementation of Open Source CAD (Oscad) [1], a complete EDA tool for Electronics and Electrical engineers. The paper illustrates the use of Oscad for circuit design, simulation and PCB design. It also gives implementation details of an in-house developed circuit simulator, Scilab based Mini Circuit Simulator (SMCSim), available in Oscad. The simulator can provide the system of equations for the circuit under test. This feature is unique to Oscad. The paper presents two examples to show the capabilities of Oscad.
{"title":"Oscad: An open source EDA tool for circuit design, simulation, analysis and PCB design","authors":"Yogesh Dilip Save, R. Rakhi, N. D. Shambhulingayya, A. Srivastava, M. R. Das, Saket Choudhary, K. Moudgalya","doi":"10.1109/ICECS.2013.6815548","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815548","url":null,"abstract":"In this paper, we discuss the implementation of Open Source CAD (Oscad) [1], a complete EDA tool for Electronics and Electrical engineers. The paper illustrates the use of Oscad for circuit design, simulation and PCB design. It also gives implementation details of an in-house developed circuit simulator, Scilab based Mini Circuit Simulator (SMCSim), available in Oscad. The simulator can provide the system of equations for the circuit under test. This feature is unique to Oscad. The paper presents two examples to show the capabilities of Oscad.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134599429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815541
Kerem Kapucu, C. Dehollain
This work discusses the remote powering link of a passive UHF RFID tag for sensor applications. The design, implementation, and measurements of the base-station antenna, tag antenna, and the rectifier are presented. The base-station antenna is a 50 Ω rectangular patch antenna with a measured far-field gain of 3.6 dBi. The tag antenna is an inductively coupled meandered dipole antenna impedance matched to the tag chip. The measured far-field gain of the tag antenna is 1.2 dBi. The three-stage, differential-input rectifier is measured to deliver 1 mW to a 5 kΩ load with a power conversion efficiency of 65% at a distance of 1.5 meters from the base station. The rectifier is implemented in 0.18 μm UMC CMOS process.
{"title":"Remote powering link for a passive UHF RFID tag for capacitive sensor applications","authors":"Kerem Kapucu, C. Dehollain","doi":"10.1109/ICECS.2013.6815541","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815541","url":null,"abstract":"This work discusses the remote powering link of a passive UHF RFID tag for sensor applications. The design, implementation, and measurements of the base-station antenna, tag antenna, and the rectifier are presented. The base-station antenna is a 50 Ω rectangular patch antenna with a measured far-field gain of 3.6 dBi. The tag antenna is an inductively coupled meandered dipole antenna impedance matched to the tag chip. The measured far-field gain of the tag antenna is 1.2 dBi. The three-stage, differential-input rectifier is measured to deliver 1 mW to a 5 kΩ load with a power conversion efficiency of 65% at a distance of 1.5 meters from the base station. The rectifier is implemented in 0.18 μm UMC CMOS process.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134529223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815482
A. H. Yüzer, S. Bassam, F. Ghannouchi, S. Demir
This paper presents a proposal for a new memory polynomial modeling technique with non-uniform delay taps to capture the thermal memory effects in power amplifiers. In the proposed modeling structure, each order of the memory polynomial is assigned a different memory delay. The delay profile is an exponentially shaped function, instead of equal unit delays for all memory polynomial branches. Three different metrics, the memory effect modeling ratio (MEMR) and the normalized mean square error (NMSE) and spectrum error (SE) are used to benchmark the proposed exponentially shaped delay profile memorial polynomial model performance against previously published models, namely the memoryless, the unit delay and sparse delay memory based polynomial models. The model coefficients of four models are extracted for three different excitation signals, which were selected as a 64-QAM signal around 2.14 GHz with 20 kHz, 30 kHz and 40 kHz bandwidths, ensuring that the thermal memory effects dominate the electrical memory effects. It is shown that the proposed model outperforms all the previously published models for all three excitation signals used in the experiment.
{"title":"Memory polynomial with shaped memory delay profile and modeling the thermal memory effect","authors":"A. H. Yüzer, S. Bassam, F. Ghannouchi, S. Demir","doi":"10.1109/ICECS.2013.6815482","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815482","url":null,"abstract":"This paper presents a proposal for a new memory polynomial modeling technique with non-uniform delay taps to capture the thermal memory effects in power amplifiers. In the proposed modeling structure, each order of the memory polynomial is assigned a different memory delay. The delay profile is an exponentially shaped function, instead of equal unit delays for all memory polynomial branches. Three different metrics, the memory effect modeling ratio (MEMR) and the normalized mean square error (NMSE) and spectrum error (SE) are used to benchmark the proposed exponentially shaped delay profile memorial polynomial model performance against previously published models, namely the memoryless, the unit delay and sparse delay memory based polynomial models. The model coefficients of four models are extracted for three different excitation signals, which were selected as a 64-QAM signal around 2.14 GHz with 20 kHz, 30 kHz and 40 kHz bandwidths, ensuring that the thermal memory effects dominate the electrical memory effects. It is shown that the proposed model outperforms all the previously published models for all three excitation signals used in the experiment.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133277142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815443
Jannah Al-Hashimi, Seepsa Tomoq, K. Abugharbieh, Yazan Al-Qudah, Mustafa Shihadeh
This work presents a methodology to analyze defects in an SRAM cell based on electrical testing which can help improve yield of semiconductor ICs. It uses an algorithm that utilizes fuzzy logic techniques to post process electrical measurements to analyze the point(s) of failure. To model the impact of opens and shorts in the SRAM cell, a number of resistors were added in various locations in the schematic of a cell where a defect can occur. Simulations were run where these resistors were shorted or opened according to their location(s) and the defect(s) they represent. The work was conducted using 28 nm technology device models. Design and simulations were done using Synopsys transistor level Custom Designer software that includes HSPICE. MATLAB was used to implement the fuzzy logic based algorithm to post process the electrical simulations' results. The algorithm presented in this paper can be modified for different technology nodes and can be used by design and yield engineers in industry.
{"title":"An SRAM based testing methodology for yield analysis of semiconductor ICs","authors":"Jannah Al-Hashimi, Seepsa Tomoq, K. Abugharbieh, Yazan Al-Qudah, Mustafa Shihadeh","doi":"10.1109/ICECS.2013.6815443","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815443","url":null,"abstract":"This work presents a methodology to analyze defects in an SRAM cell based on electrical testing which can help improve yield of semiconductor ICs. It uses an algorithm that utilizes fuzzy logic techniques to post process electrical measurements to analyze the point(s) of failure. To model the impact of opens and shorts in the SRAM cell, a number of resistors were added in various locations in the schematic of a cell where a defect can occur. Simulations were run where these resistors were shorted or opened according to their location(s) and the defect(s) they represent. The work was conducted using 28 nm technology device models. Design and simulations were done using Synopsys transistor level Custom Designer software that includes HSPICE. MATLAB was used to implement the fuzzy logic based algorithm to post process the electrical simulations' results. The algorithm presented in this paper can be modified for different technology nodes and can be used by design and yield engineers in industry.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114217714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815493
S. Chouhan, K. Halonen
The RF rectifier is a key component in wireless sensor networks and RFID applications. It converts the input RF signal into DC voltage to power up a system. Low settling time is important for efficiently acquiring DC voltage in an RFID system. The settling time is defined as the time required by the rectifier to reach the maximum stable DC voltage for a given load condition. The main focus of this work is to reduce the settling time required by the rectifier. Settling time is one of the performance limitations of a rectifier due to the threshold voltage of the transistor. In this work, we are proposing the use of DTMOS (Dynamic Threshold MOSFET) architecture in the design of RF to DC rectifier. In DTMOS, gate and body are tied together, which dynamically alters the threshold voltage to suit the operating state of the circuit. We implemented the DTMOS architecture in a self Vth cancellation (SVC) scheme based rectifier. Settling time is considered as the performance parameter. Results demonstrate that settling time of the modified SVC rectifier is less than 50%, as compared to that of the conventional BTMOS(body terminal tied to source terminal) based SVC rectifier structure. The rectifiers have been implemented using the 180nm standard CMOS technology and the simulations were performed using spectre simulator.
{"title":"The DTMOS based UHF RF to DC conversion","authors":"S. Chouhan, K. Halonen","doi":"10.1109/ICECS.2013.6815493","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815493","url":null,"abstract":"The RF rectifier is a key component in wireless sensor networks and RFID applications. It converts the input RF signal into DC voltage to power up a system. Low settling time is important for efficiently acquiring DC voltage in an RFID system. The settling time is defined as the time required by the rectifier to reach the maximum stable DC voltage for a given load condition. The main focus of this work is to reduce the settling time required by the rectifier. Settling time is one of the performance limitations of a rectifier due to the threshold voltage of the transistor. In this work, we are proposing the use of DTMOS (Dynamic Threshold MOSFET) architecture in the design of RF to DC rectifier. In DTMOS, gate and body are tied together, which dynamically alters the threshold voltage to suit the operating state of the circuit. We implemented the DTMOS architecture in a self Vth cancellation (SVC) scheme based rectifier. Settling time is considered as the performance parameter. Results demonstrate that settling time of the modified SVC rectifier is less than 50%, as compared to that of the conventional BTMOS(body terminal tied to source terminal) based SVC rectifier structure. The rectifiers have been implemented using the 180nm standard CMOS technology and the simulations were performed using spectre simulator.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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