Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815437
V. Brea, Manuel Suárez-Cambre, J. Illade-Quinteiro, Paula López, D. Cabello, G. Doménech-Asensi
This paper addresses voltage boosters for on-chip solar cells on a standard 0.18 μm CMOS technology. Voltage boosters, also referred to as DC/DC converters or charge pumps, are needed to make the open voltage of micro solar cells compatible with the power supply of current standard CMOS technologies. This paper is oriented to on-chip solar cells for focal-plane processors, where the photodiode array can be configured along time for both image acquisition and energy harvesting. The large area occupied by the focal-plane processor itself constrains the design of the charge pumps, as there is small room for them, forcing the use of relatively small capacitors too. This paper assesses the main performance metrics through electrical simulations of three charge pumps, namely, the Dickson, the Fibonacci and the heap charge pump. The paper has a clear practical orientation, outlining how to configure the photodiode array of a focal-plane processor along time to increase the power efficiency.
{"title":"Voltage boosters for on-chip solar cells on focal-plane processors","authors":"V. Brea, Manuel Suárez-Cambre, J. Illade-Quinteiro, Paula López, D. Cabello, G. Doménech-Asensi","doi":"10.1109/ICECS.2013.6815437","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815437","url":null,"abstract":"This paper addresses voltage boosters for on-chip solar cells on a standard 0.18 μm CMOS technology. Voltage boosters, also referred to as DC/DC converters or charge pumps, are needed to make the open voltage of micro solar cells compatible with the power supply of current standard CMOS technologies. This paper is oriented to on-chip solar cells for focal-plane processors, where the photodiode array can be configured along time for both image acquisition and energy harvesting. The large area occupied by the focal-plane processor itself constrains the design of the charge pumps, as there is small room for them, forcing the use of relatively small capacitors too. This paper assesses the main performance metrics through electrical simulations of three charge pumps, namely, the Dickson, the Fibonacci and the heap charge pump. The paper has a clear practical orientation, outlining how to configure the photodiode array of a focal-plane processor along time to increase the power efficiency.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130620958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815477
A. Thanos, H. T. Vergos
Ling-carry adders that use a Ladner-Fischer parallel-prefix algorithm for carry computation are explored for quantum-dot cellular automata (QCA) nanotechnology implementations. The results derived from drawn layouts, indicate that the proposed adders outperform in terms of delay all previously reported architectures explored for QCA implementations. The delay difference is becoming bigger in favor of the proposed adders as we move to larger wordlengths.
{"title":"Fast parallel-prefix Ling-carry adders in QCA nanotechnology","authors":"A. Thanos, H. T. Vergos","doi":"10.1109/ICECS.2013.6815477","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815477","url":null,"abstract":"Ling-carry adders that use a Ladner-Fischer parallel-prefix algorithm for carry computation are explored for quantum-dot cellular automata (QCA) nanotechnology implementations. The results derived from drawn layouts, indicate that the proposed adders outperform in terms of delay all previously reported architectures explored for QCA implementations. The delay difference is becoming bigger in favor of the proposed adders as we move to larger wordlengths.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130285213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815361
Temesghen Tekeste, H. Saleh, B. Mohammad, M. Al-Qutayri, M. Ismail
Recent developments in biomedical sensors has led to wearable medical devices which made energy efficiency a prime factor to consider. Hardware accelerators offer signal-processing capability with energy consumption lower than general-purpose CPUs/DSPs. Hence, great interest has risen recently in dedicated biomedical systems on chips that target extremely low levels of power consumption. Many power reduction techniques have been used, such as: multiple supply voltages (voltage islands), power gating, clock gating and voltage scaling, these techniques provided means for optimum energy efficiency operation. This paper attempts to briefly review the current research in biomedical SoCs.
{"title":"Survey of wireless baseband SoC for biomedical application","authors":"Temesghen Tekeste, H. Saleh, B. Mohammad, M. Al-Qutayri, M. Ismail","doi":"10.1109/ICECS.2013.6815361","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815361","url":null,"abstract":"Recent developments in biomedical sensors has led to wearable medical devices which made energy efficiency a prime factor to consider. Hardware accelerators offer signal-processing capability with energy consumption lower than general-purpose CPUs/DSPs. Hence, great interest has risen recently in dedicated biomedical systems on chips that target extremely low levels of power consumption. Many power reduction techniques have been used, such as: multiple supply voltages (voltage islands), power gating, clock gating and voltage scaling, these techniques provided means for optimum energy efficiency operation. This paper attempts to briefly review the current research in biomedical SoCs.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131298799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815505
Yesim Hekim Tanc, A. Akan
The problem of identifying the modulation types of the signals at the receiver is an intermediate step between signal detection and demodulation. In this paper, Hilbert-Huang Transform is proposed for identifying the modulation level of M-ary Quadrature Amplitude Modulation (QAM) signals in the presence of the Additive White Gaussian Noise. Hilbert-Huang Transform decomposes the non-stationary signal into sum of oscillatory signals with different frequency and obtains the instantaneous features of the signals, like time-frequency and time-amplitude information. The statistical properties of instantaneous data sets are used to determine the modulation levels of M-ary QAM signals. The most important feature of the proposed method is that, the algorithm does not utilize any a priori knowledge about the signal. Computer simulations demonstrate the accuracy of the proposed algorithm.
{"title":"Modulation identification of digital M-ary QAM signals by Hilbert-Huang Transform","authors":"Yesim Hekim Tanc, A. Akan","doi":"10.1109/ICECS.2013.6815505","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815505","url":null,"abstract":"The problem of identifying the modulation types of the signals at the receiver is an intermediate step between signal detection and demodulation. In this paper, Hilbert-Huang Transform is proposed for identifying the modulation level of M-ary Quadrature Amplitude Modulation (QAM) signals in the presence of the Additive White Gaussian Noise. Hilbert-Huang Transform decomposes the non-stationary signal into sum of oscillatory signals with different frequency and obtains the instantaneous features of the signals, like time-frequency and time-amplitude information. The statistical properties of instantaneous data sets are used to determine the modulation levels of M-ary QAM signals. The most important feature of the proposed method is that, the algorithm does not utilize any a priori knowledge about the signal. Computer simulations demonstrate the accuracy of the proposed algorithm.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126758294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815550
Bahram N. Uchevler, K. Svarstad
Verification is a challenge that consumes an increasing part of the design time in the design flow of modern hardware systems. We propose an Assertion Based Verification (ABV) method with embedding synthesizable clock-accurate assertion checkers in higher levels of abstraction in the design flow. Both the Design Under Verification (DUV) and its synthesizable assertion checkers are described using the same language which leads to an easier integration of the checkers. Using this approach on a case study confirms its feasibility without any penalty in the working frequency with less than 5% increased area consumption on a Kintex7 FPGA.
{"title":"Synthesizable assertion checkers in high levels of abstraction","authors":"Bahram N. Uchevler, K. Svarstad","doi":"10.1109/ICECS.2013.6815550","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815550","url":null,"abstract":"Verification is a challenge that consumes an increasing part of the design time in the design flow of modern hardware systems. We propose an Assertion Based Verification (ABV) method with embedding synthesizable clock-accurate assertion checkers in higher levels of abstraction in the design flow. Both the Design Under Verification (DUV) and its synthesizable assertion checkers are described using the same language which leads to an easier integration of the checkers. Using this approach on a case study confirms its feasibility without any penalty in the working frequency with less than 5% increased area consumption on a Kintex7 FPGA.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121627738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815470
A. Vivekanand, N. Werghi, H. Al-Ahmad
Posterior Capsule Opacification (PCO) remains to be the most common complication of cataract surgery after intraocular lens implantation. Though several strategies have been suggested for the prevention of PCO, a standard PCO quantification system is required to reliably assess the effectiveness of these strategies. This paper proposes a method based on computation of Hölder exponents to quantify the amount of PCO in the digital image. PCO areas are effectively detected and classified according to their severity using histogram-based thresholding on Hölder exponent image. This method is implemented in Matlab and verified on real PCO images. The results show a high correlation of 83% between the computed PCO scores and the clinical grades, as well as demonstrate the robustness of the proposed system to monotonic illumination variations.
{"title":"Automated image assessment of posterior capsule opacification using Hölder exponents","authors":"A. Vivekanand, N. Werghi, H. Al-Ahmad","doi":"10.1109/ICECS.2013.6815470","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815470","url":null,"abstract":"Posterior Capsule Opacification (PCO) remains to be the most common complication of cataract surgery after intraocular lens implantation. Though several strategies have been suggested for the prevention of PCO, a standard PCO quantification system is required to reliably assess the effectiveness of these strategies. This paper proposes a method based on computation of Hölder exponents to quantify the amount of PCO in the digital image. PCO areas are effectively detected and classified according to their severity using histogram-based thresholding on Hölder exponent image. This method is implemented in Matlab and verified on real PCO images. The results show a high correlation of 83% between the computed PCO scores and the clinical grades, as well as demonstrate the robustness of the proposed system to monotonic illumination variations.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132358618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815421
E. Dabellani, H. Rabah, N. Marques, Y. Berviller, S. Jovanovic, S. Weber
Video adaption is one of the main solutions to offer access to the large array of existing multimedia contents and the variety of terminals and networks. This adaptation can be achieved efficiently using transcoding techniques. The implementation of the various adaptation possibilities and techniques in embedded systems such as home gateway requires flexible and efficient architectures. This paper presents a hardware reconfigurable architecture for the real time adaptation of video contents for different terminals and available bandwidth. This architecture is designed to adapt a compressed stream in advanced video coding standard (H264/AVC) and/or MPEG-2. A system level model of reconfigurable transcoder is developed for IP integration and architectural exploration by taking into account dynamic and partial reconfiguration. The developed simulation model of dynamic partial reconfiguration allowed the early estimation of performances and the design of the suitable solution for the considered transcoding scenarios.
{"title":"Modeling and FPGA implementation of reconfigurable transcoder for real time video adaptation","authors":"E. Dabellani, H. Rabah, N. Marques, Y. Berviller, S. Jovanovic, S. Weber","doi":"10.1109/ICECS.2013.6815421","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815421","url":null,"abstract":"Video adaption is one of the main solutions to offer access to the large array of existing multimedia contents and the variety of terminals and networks. This adaptation can be achieved efficiently using transcoding techniques. The implementation of the various adaptation possibilities and techniques in embedded systems such as home gateway requires flexible and efficient architectures. This paper presents a hardware reconfigurable architecture for the real time adaptation of video contents for different terminals and available bandwidth. This architecture is designed to adapt a compressed stream in advanced video coding standard (H264/AVC) and/or MPEG-2. A system level model of reconfigurable transcoder is developed for IP integration and architectural exploration by taking into account dynamic and partial reconfiguration. The developed simulation model of dynamic partial reconfiguration allowed the early estimation of performances and the design of the suitable solution for the considered transcoding scenarios.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121861017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815462
Tao Jin, Shuai Wang
To alleviate the complex communication problems arising in the network-on-chip (NoC) architectures as the number of on-chip components increases, wireless network-on-chip (WiNoC) is among the most promising scalable interconnection architectures for future generation NoCs. Since 1-to-many and many-to-1 communications caused by the cache coherence protocol in the multiprocessor system have high demands on the network, we propose several optimization schemes to improve both 1-to-many and many-to-1 communications in the hybrid WiNoC. Experimental results show that our optimized hybrid WiNoC can reduce the network latency by ~50% on average.
{"title":"1-to-Many and many-to-1 communication in hybrid wireless network-on-chip","authors":"Tao Jin, Shuai Wang","doi":"10.1109/ICECS.2013.6815462","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815462","url":null,"abstract":"To alleviate the complex communication problems arising in the network-on-chip (NoC) architectures as the number of on-chip components increases, wireless network-on-chip (WiNoC) is among the most promising scalable interconnection architectures for future generation NoCs. Since 1-to-many and many-to-1 communications caused by the cache coherence protocol in the multiprocessor system have high demands on the network, we propose several optimization schemes to improve both 1-to-many and many-to-1 communications in the hybrid WiNoC. Experimental results show that our optimized hybrid WiNoC can reduce the network latency by ~50% on average.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132806463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815514
M. Terres, C. Meinhardt, G. Bontorin, R. Reis
Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically turn off idle LS, using an alternative path to current flows, according to the power mode of the regions that the nets are connected. The main advantages of this technique are when the nets connect regions with the same power mode. In this cases, this technique permits to save more than 35% power consumption and reduce the delay on 30% for NAND2 circuits.
{"title":"A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage","authors":"M. Terres, C. Meinhardt, G. Bontorin, R. Reis","doi":"10.1109/ICECS.2013.6815514","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815514","url":null,"abstract":"Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically turn off idle LS, using an alternative path to current flows, according to the power mode of the regions that the nets are connected. The main advantages of this technique are when the nets connect regions with the same power mode. In this cases, this technique permits to save more than 35% power consumption and reduce the delay on 30% for NAND2 circuits.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815427
Jordi Cosp-Vilella, H. Martínez
This article shows the design of an on-chip CMOS linear-assisted DC-DC regulator. It results a good alternative topology to classic switching DC-DC power converters. In the presented technique, an auxiliary linear regulator is used to cancel the output voltage ripple and provides fast responses for load and line variations. On the other hand, a switching converter, connected in parallel, allows supplying almost the whole output current demanded by the load. The objective of this linear-assisted regulator or hybrid topology is to achieve a high efficiency of switching converters, with suitable load and line regulation features, typical of linear regulators. In this kind of on-chip applications, CMOS is the current prevailing technology. Thus, in order to implement on-chip power supply systems and on-chip power management systems with low-to-medium current consumption, this structure has good features.
{"title":"Design of an on-chip linear-assisted DC-DC voltage regulator","authors":"Jordi Cosp-Vilella, H. Martínez","doi":"10.1109/ICECS.2013.6815427","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815427","url":null,"abstract":"This article shows the design of an on-chip CMOS linear-assisted DC-DC regulator. It results a good alternative topology to classic switching DC-DC power converters. In the presented technique, an auxiliary linear regulator is used to cancel the output voltage ripple and provides fast responses for load and line variations. On the other hand, a switching converter, connected in parallel, allows supplying almost the whole output current demanded by the load. The objective of this linear-assisted regulator or hybrid topology is to achieve a high efficiency of switching converters, with suitable load and line regulation features, typical of linear regulators. In this kind of on-chip applications, CMOS is the current prevailing technology. Thus, in order to implement on-chip power supply systems and on-chip power management systems with low-to-medium current consumption, this structure has good features.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134149842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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