Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815526
H. Madureira, N. Deltimple, E. Kerhervé, S. Haddad
A power oscillator based on a class EF2 power amplifier is presented. The class EF2 power amplifier uses a short circuit to the second harmonic across the switch to lower it's voltage stress and delivers a more sinusoidal power waveform than the class E counterpart. The presented circuit was designed in standard ST Microelectronics CMOS 130nm and is able to deliver 20.6dBm RF power from a 2V supply voltage with a 42% DC-RF efficiency at 2.5GHz and present 12.5% tuning range. The drain efficiency of the class EF2 core is 49.4%. The phase noise is as low as -118.8dBc/Hz @ 1MHz. The output power spectrum presents 30.7dB power difference between the fundamental frequency and the strongest upper harmonic. The total used area is 1550um × 1280um.
{"title":"Design of a class EF2 power oscillator for RF communication application","authors":"H. Madureira, N. Deltimple, E. Kerhervé, S. Haddad","doi":"10.1109/ICECS.2013.6815526","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815526","url":null,"abstract":"A power oscillator based on a class EF2 power amplifier is presented. The class EF2 power amplifier uses a short circuit to the second harmonic across the switch to lower it's voltage stress and delivers a more sinusoidal power waveform than the class E counterpart. The presented circuit was designed in standard ST Microelectronics CMOS 130nm and is able to deliver 20.6dBm RF power from a 2V supply voltage with a 42% DC-RF efficiency at 2.5GHz and present 12.5% tuning range. The drain efficiency of the class EF2 core is 49.4%. The phase noise is as low as -118.8dBc/Hz @ 1MHz. The output power spectrum presents 30.7dB power difference between the fundamental frequency and the strongest upper harmonic. The total used area is 1550um × 1280um.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128235718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815414
P. Georgiou, Mauricio Barahona, S. Yaliraki, E. Drakakis
This work discusses the conditions under which two identical and ideal memristors behave as reciprocal elements. In particular, it is shown that when the output of an ideal memristor is used to drive another identical device, then the output of the second device is identical to the signal originally fed as an input to the first one.
{"title":"Ideal memristors as reciprocal elements","authors":"P. Georgiou, Mauricio Barahona, S. Yaliraki, E. Drakakis","doi":"10.1109/ICECS.2013.6815414","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815414","url":null,"abstract":"This work discusses the conditions under which two identical and ideal memristors behave as reciprocal elements. In particular, it is shown that when the output of an ideal memristor is used to drive another identical device, then the output of the second device is identical to the signal originally fed as an input to the first one.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132962571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815516
Temesghen Tekeste, A. Shabra, D. Boning, I. Elfadel
An important synchronous circuit element in low-power digital circuit design is the voltage level shifter at the boundary between voltage domains. In this paper, we present a full variability analysis of an optimized, synchronous pulsed half-latch level converter (PHLC) in the GLOBALFOUNDRIES 28nm technology. The variability analysis clearly illustrates the impact of ultra-low-power design on delay, energy and the energy-delay product (EDP). In particular, the normalized standard deviation for EDP in near-threshold operation is more than twice its value for nominal-supply operation. The analysis also illustrates the impact of variability on the architectural and topological decisions a designer has to make in ultra-low power design.
{"title":"Variability analysis of a 28nm near-threshold synchronous voltage converter","authors":"Temesghen Tekeste, A. Shabra, D. Boning, I. Elfadel","doi":"10.1109/ICECS.2013.6815516","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815516","url":null,"abstract":"An important synchronous circuit element in low-power digital circuit design is the voltage level shifter at the boundary between voltage domains. In this paper, we present a full variability analysis of an optimized, synchronous pulsed half-latch level converter (PHLC) in the GLOBALFOUNDRIES 28nm technology. The variability analysis clearly illustrates the impact of ultra-low-power design on delay, energy and the energy-delay product (EDP). In particular, the normalized standard deviation for EDP in near-threshold operation is more than twice its value for nominal-supply operation. The analysis also illustrates the impact of variability on the architectural and topological decisions a designer has to make in ultra-low power design.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129452153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815366
Khaled Nouh, Haytham Saafan, Ahmed Ismail
Verification techniques such as Clock Domain Crossing (CDC) and Power-Aware verification are early ways to detect and debug silicon related bugs. One crucial problem is having an X-state that leads to mismatching behavior between synthesis and RTL. This paper describes how the X-problem affects CDC synchronization correctness and the power intent of the design and shows how the current protocol checking techniques misses real faults that occur due to having an X. Also, it proposes two methods to account for X in the current CDC and power aware verification. The paper provides a case study to prove the feasibility and usefulness of the approach proposed.
{"title":"X-Aware verification: A different perspective!","authors":"Khaled Nouh, Haytham Saafan, Ahmed Ismail","doi":"10.1109/ICECS.2013.6815366","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815366","url":null,"abstract":"Verification techniques such as Clock Domain Crossing (CDC) and Power-Aware verification are early ways to detect and debug silicon related bugs. One crucial problem is having an X-state that leads to mismatching behavior between synthesis and RTL. This paper describes how the X-problem affects CDC synchronization correctness and the power intent of the design and shows how the current protocol checking techniques misses real faults that occur due to having an X. Also, it proposes two methods to account for X in the current CDC and power aware verification. The paper provides a case study to prove the feasibility and usefulness of the approach proposed.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132059356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815354
Ehab Salahat, H. Saleh, B. Mohammad, M. Al-Qutayri, A. Sluzek, M. Ismail
Numerous techniques and algorithms have been developed and implemented, primarily in software, for object tracking, detection and recognition. A few attempts have been made to implement some of the algorithms in hardware. However, those attempts have not yielded optimal results in terms of accuracy, power and memory requirements. The aim of this paper is to explore and investigate a number of possible algorithms for real-time video surveillance, revealing their various theories, relationships, shortcomings, advantages and disadvantages, and pointing out their unsolved problems of practical interest in principled way, which would be of tremendous value to engineers and researchers trying to decide what algorithm among those many in literature is most suitable to specific application and the particular real-time System-on-Chip (SoC) implementation.
{"title":"Automated real-time video surveillance algorithms for SoC implementation: A survey","authors":"Ehab Salahat, H. Saleh, B. Mohammad, M. Al-Qutayri, A. Sluzek, M. Ismail","doi":"10.1109/ICECS.2013.6815354","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815354","url":null,"abstract":"Numerous techniques and algorithms have been developed and implemented, primarily in software, for object tracking, detection and recognition. A few attempts have been made to implement some of the algorithms in hardware. However, those attempts have not yielded optimal results in terms of accuracy, power and memory requirements. The aim of this paper is to explore and investigate a number of possible algorithms for real-time video surveillance, revealing their various theories, relationships, shortcomings, advantages and disadvantages, and pointing out their unsolved problems of practical interest in principled way, which would be of tremendous value to engineers and researchers trying to decide what algorithm among those many in literature is most suitable to specific application and the particular real-time System-on-Chip (SoC) implementation.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132194280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815438
Ahmad M. Marzouk, Ahmed A. Abdelmoaty, A. Helmy, Y. Ismail
Growing concerns about environmental issues and the world energy crisis have attracted a great deal of interests for the development and application of the photovoltaic (PV) power system that uses the nonpolluting and the most abundant solar energy. This paper introduces a novel maximum power point tracking (MPPT) algorithm that is based on the fact that the PV power curve is similar to a parabolic curve in nature. The algorithm is implemented and validated on Simulink/MATLAB. The simulation results show enhancement in tracking time and accuracy in comparison to the Perturb and Observe (P&O) algorithm.
{"title":"TPQA: Three point quadrature approximation MPPT algorithm","authors":"Ahmad M. Marzouk, Ahmed A. Abdelmoaty, A. Helmy, Y. Ismail","doi":"10.1109/ICECS.2013.6815438","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815438","url":null,"abstract":"Growing concerns about environmental issues and the world energy crisis have attracted a great deal of interests for the development and application of the photovoltaic (PV) power system that uses the nonpolluting and the most abundant solar energy. This paper introduces a novel maximum power point tracking (MPPT) algorithm that is based on the fact that the PV power curve is similar to a parabolic curve in nature. The algorithm is implemented and validated on Simulink/MATLAB. The simulation results show enhancement in tracking time and accuracy in comparison to the Perturb and Observe (P&O) algorithm.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133091046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815474
Sylvain Maréchal, F. Krummenacher, M. Kayal
This paper addresses the simulation of switched-capacitor circuits including capacitor nonlinearities at an intermediate modelling level, filling the gap between device level and behavioural level simulators. Starting with the resolution of the trivial case of integrator with ideal components, the impact of first- and higher-order capacitor nonlinearities is analyzed in detail and the related simulation approach is explained. As an application example, the expectable performance of a simulated incremental second-order ΣΔ converter is given.
{"title":"Simulating nonlinear capacitors in sigma-delta modulators","authors":"Sylvain Maréchal, F. Krummenacher, M. Kayal","doi":"10.1109/ICECS.2013.6815474","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815474","url":null,"abstract":"This paper addresses the simulation of switched-capacitor circuits including capacitor nonlinearities at an intermediate modelling level, filling the gap between device level and behavioural level simulators. Starting with the resolution of the trivial case of integrator with ideal components, the impact of first- and higher-order capacitor nonlinearities is analyzed in detail and the related simulation approach is explained. As an application example, the expectable performance of a simulated incremental second-order ΣΔ converter is given.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130017064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815439
Panagiotis Sismanoglou, D. Nikolos
The manufacturing test cost of an IC depends heavily of its test data volume. In this paper we show how to exploit the features of a dictionary based test data compression technique in order to increase the count and the length of 0s and 1s runs appearing in the compressed test data. Then, we experimentally show that using the ATE repeat instruction the test data volume which should be stored in the ATE vector memory can be further reduced significantly.
{"title":"Enhancing dictionary based test data compression using the ATE repeat instruction","authors":"Panagiotis Sismanoglou, D. Nikolos","doi":"10.1109/ICECS.2013.6815439","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815439","url":null,"abstract":"The manufacturing test cost of an IC depends heavily of its test data volume. In this paper we show how to exploit the features of a dictionary based test data compression technique in order to increase the count and the length of 0s and 1s runs appearing in the compressed test data. Then, we experimentally show that using the ATE repeat instruction the test data volume which should be stored in the ATE vector memory can be further reduced significantly.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"88 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132694030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815506
J. Dostál, V. Smotlacha
This paper deals with an accurate time transfer and atomic clocks comparison. It presents an adapter for clock comparison over an optical network, especially utilizing dense wavelength division multiplexing (DWDM). The adapter is a field-programmable gate array (FPGA) based device with DWDM transceivers and frequency synthesis functionality. For the second generation of adapters an embedded interpolating time interval counter in FPGA was developed. We also present results of interpolating counter functionality evaluation in respect to SR620 universal counter.
{"title":"Atomic clock comparison over optical network","authors":"J. Dostál, V. Smotlacha","doi":"10.1109/ICECS.2013.6815506","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815506","url":null,"abstract":"This paper deals with an accurate time transfer and atomic clocks comparison. It presents an adapter for clock comparison over an optical network, especially utilizing dense wavelength division multiplexing (DWDM). The adapter is a field-programmable gate array (FPGA) based device with DWDM transceivers and frequency synthesis functionality. For the second generation of adapters an embedded interpolating time interval counter in FPGA was developed. We also present results of interpolating counter functionality evaluation in respect to SR620 universal counter.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116352952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815502
Qi Zhang, Ning Wang, D. Yuan, Guohong Li, Hui Wang, Songlin Feng
A fully-integrated reconfigurable RF transceiver dedicated for the sub-1GHz short range wireless applications is presented. The RF transceiver mainly consists of a reconfigurable RF front-end, a low-power reconfigurable receiver IF part and a Σ-Δ fractional-N PLL. The RF front-end with highly switchable gain/NF/output power with broadband matching for sub-1GHz frequency is proposed. The polyphase filter (PPF) with independently reconfigurable center frequency/bandwidth/gain is proposed for different protocols. GFSK modulation format is adopted at data rates from 250Kbps to 2Mbps. The chip is implemented in 0.18um CMOS process. Operating in the typical 400MHz band with 2Mbps data rate, the receiver consumes 9.5mA from a 1.8V supply and achieves a sensitivity of -87dBm with 0.1% BER. The transmitter consumes 12mA for an output power of +3dBm.
{"title":"A low-power reconfigurable GFSK RF transceiver with sub-1GHz band for short range applications","authors":"Qi Zhang, Ning Wang, D. Yuan, Guohong Li, Hui Wang, Songlin Feng","doi":"10.1109/ICECS.2013.6815502","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815502","url":null,"abstract":"A fully-integrated reconfigurable RF transceiver dedicated for the sub-1GHz short range wireless applications is presented. The RF transceiver mainly consists of a reconfigurable RF front-end, a low-power reconfigurable receiver IF part and a Σ-Δ fractional-N PLL. The RF front-end with highly switchable gain/NF/output power with broadband matching for sub-1GHz frequency is proposed. The polyphase filter (PPF) with independently reconfigurable center frequency/bandwidth/gain is proposed for different protocols. GFSK modulation format is adopted at data rates from 250Kbps to 2Mbps. The chip is implemented in 0.18um CMOS process. Operating in the typical 400MHz band with 2Mbps data rate, the receiver consumes 9.5mA from a 1.8V supply and achieves a sensitivity of -87dBm with 0.1% BER. The transmitter consumes 12mA for an output power of +3dBm.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"314 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132162585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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