Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815332
Kamyar Keikhosravy, Pouya Kamalinejad, S. Mirabbasi, Victor C. M. Leung
In this paper, an ultra wideband analog voltage-mode buffer is presented which can drive a load impedance of 50 Ω. The presented feedback-based buffer uses a compound amplifier which is a parallel combination of a high-DC gain operational amplifier and a operation transconductance amplifier to achieve a high unity gain bandwidth. A proof-of-concept prototype is designed and fabricated in a 0.13 μm CMOS process. The simulation and measurement results of the proposed buffer are in good agreement. The prototype buffer circuit consumes 7.34 mW from a 1.3-V supply, while buffering a 2 GHz sinusoidal input signal with a 0.4 V peak-to-peak (Vpp) amplitude and driving an AC-coupled 50-Ω load.
{"title":"A wideband unity-gain buffer in 0.13-μm CMOS","authors":"Kamyar Keikhosravy, Pouya Kamalinejad, S. Mirabbasi, Victor C. M. Leung","doi":"10.1109/ICECS.2013.6815332","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815332","url":null,"abstract":"In this paper, an ultra wideband analog voltage-mode buffer is presented which can drive a load impedance of 50 Ω. The presented feedback-based buffer uses a compound amplifier which is a parallel combination of a high-DC gain operational amplifier and a operation transconductance amplifier to achieve a high unity gain bandwidth. A proof-of-concept prototype is designed and fabricated in a 0.13 μm CMOS process. The simulation and measurement results of the proposed buffer are in good agreement. The prototype buffer circuit consumes 7.34 mW from a 1.3-V supply, while buffering a 2 GHz sinusoidal input signal with a 0.4 V peak-to-peak (Vpp) amplitude and driving an AC-coupled 50-Ω load.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"516 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116218232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815571
D. Schinianakis, T. Stouraitis
An RNS implementation of Barrett's modular multiplication algorithm is presented in this paper. Existing algorithms for RNS modular multiplication employ Montgomery's technique. An algorithmic comparison with such state-of-the-art solutions shows that the proposed algorithm may reduce the total number of modular multiplications per RNS modular multiplication by 33%-50%.
{"title":"An RNS modular multiplication algorithm","authors":"D. Schinianakis, T. Stouraitis","doi":"10.1109/ICECS.2013.6815571","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815571","url":null,"abstract":"An RNS implementation of Barrett's modular multiplication algorithm is presented in this paper. Existing algorithms for RNS modular multiplication employ Montgomery's technique. An algorithmic comparison with such state-of-the-art solutions shows that the proposed algorithm may reduce the total number of modular multiplications per RNS modular multiplication by 33%-50%.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123478745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815487
E. Ashenafi, M. Chowdhury
Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator comprises of a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes very large chip area hampering the scaling down process. These limitations make passive inductor based on-chip regulator very unattractive for system-on-a-chip (SOC) and multi-/many-core environments. To facilitate complete on-chip integration of a voltage regulator this paper presents an active circuit technique to replace the passive inductor and emulate the inductive behavior required in a buck convertor. The proposed scheme combines a linear and a switching voltage regulator together in single active circuit. The amalgamation of the two regulators will obviate the need to use a physical inductor, instead utilize a second-generation current conveyor based active filter along with an inverter switch and a voltage follower current source. Design of the circuit is demonstrated using 0.5μm technology on Cadence Virtuoso tools. Simulation results and MATLAB plots are provided to verify the proposed design.
{"title":"Active on-chip voltage regulator based on second generation current conveyor","authors":"E. Ashenafi, M. Chowdhury","doi":"10.1109/ICECS.2013.6815487","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815487","url":null,"abstract":"Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator comprises of a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes very large chip area hampering the scaling down process. These limitations make passive inductor based on-chip regulator very unattractive for system-on-a-chip (SOC) and multi-/many-core environments. To facilitate complete on-chip integration of a voltage regulator this paper presents an active circuit technique to replace the passive inductor and emulate the inductive behavior required in a buck convertor. The proposed scheme combines a linear and a switching voltage regulator together in single active circuit. The amalgamation of the two regulators will obviate the need to use a physical inductor, instead utilize a second-generation current conveyor based active filter along with an inverter switch and a voltage follower current source. Design of the circuit is demonstrated using 0.5μm technology on Cadence Virtuoso tools. Simulation results and MATLAB plots are provided to verify the proposed design.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"381 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124693815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815365
Amna Al Dahak, L. Seneviratne, J. Dias
Autonomous robot exploration and map building for unknown environments is essential in a wide range of applications such as search and rescue, surveillance, military and other high risk scenarios. As the robot starts exploring its surroundings, it accumulatively builds a partial map of the environment composing of the areas that are currently known by the robot. In this work we present a new exploration and mapping solution that will capture the environment structure geometrically. The proposed Triangulation-Based exploration maps the environment using the Dynamic Triangulation Tree structure (DTT) developed in this study. Using triangles to store the geometry of the environment will significantly reduce the storage space required when compared to the occupancy grids used in many exploration and map building solutions. The efficiency of the proposed mapping structure is validated experimentally through simulations.
{"title":"Mapping for unknown environment using incremental triangulation","authors":"Amna Al Dahak, L. Seneviratne, J. Dias","doi":"10.1109/ICECS.2013.6815365","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815365","url":null,"abstract":"Autonomous robot exploration and map building for unknown environments is essential in a wide range of applications such as search and rescue, surveillance, military and other high risk scenarios. As the robot starts exploring its surroundings, it accumulatively builds a partial map of the environment composing of the areas that are currently known by the robot. In this work we present a new exploration and mapping solution that will capture the environment structure geometrically. The proposed Triangulation-Based exploration maps the environment using the Dynamic Triangulation Tree structure (DTT) developed in this study. Using triangles to store the geometry of the environment will significantly reduce the storage space required when compared to the occupancy grids used in many exploration and map building solutions. The efficiency of the proposed mapping structure is validated experimentally through simulations.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117190050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815507
L. Mohjazi, M. Al-Qutayri, H. Barada, K. Poon
Femtocells are small base stations used to enhance cellular coverage in an indoor environment. However, dense femtocell deployments can lead to severe performance degradation. This paper adopts a new strategy to self-optimize the pilot power of femtocells by creating disjoint femtocell clusters which are managed by the chosen cluster heads (CHs). Each CH optimizes the coverage of its connected members by applying a multi-objective heuristic based on genetic algorithm. The simulation results show that the proposed approach can significantly reduce both the computational time and the data overhead compared with the centralized power optimization.
{"title":"Clustering based self-optimization of pilot power in dense femtocell deployments using genetic algorithms","authors":"L. Mohjazi, M. Al-Qutayri, H. Barada, K. Poon","doi":"10.1109/ICECS.2013.6815507","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815507","url":null,"abstract":"Femtocells are small base stations used to enhance cellular coverage in an indoor environment. However, dense femtocell deployments can lead to severe performance degradation. This paper adopts a new strategy to self-optimize the pilot power of femtocells by creating disjoint femtocell clusters which are managed by the chosen cluster heads (CHs). Each CH optimizes the coverage of its connected members by applying a multi-objective heuristic based on genetic algorithm. The simulation results show that the proposed approach can significantly reduce both the computational time and the data overhead compared with the centralized power optimization.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128339329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815325
Á. Rodríguez-Vázquez, H. Alshaer, B. Sharif, A. Fahim, Eman El Mandouh, A. Salem, F. Aloul, Hoda S. Abdel-Aty, John F. Dodge, B. Mohammad, Hisham Mohamed
CMOS imagers are complex systems whose design requires quite different pieces of expertise, namely: pixels, analog signal processing, pixel readout and analog-to-digital conversion, digital signal processing, output drivers, etc. Confronting the design of new imagers require hence the concourse of multidisciplinary teams. However, because correct operation calls for the close interconnection among the different parts, global knowledge is mandatory for successful design. This is particularly pertinent for the newer generations of smart imagers required for high-end applications and/or requiring ultra-high image capture, on-chip image correction, scene interpretation, high dynamic range capture, etc. All these features demand architectural and circuital innovations and pose significant challenges to designers. Also, the increased interest on sensors capable of capturing 3-D scenes raise new challenges at circuit level related to the necessity to interface pixels different from those employed for 2-D capture, on the one hand, and to extract and convert to digital domain time information, on the other hand. This tutorial addresses the design of smart CMOS imagers by following a comprehensive and complete top-down approach where each subsystem is contemplated and described as a part of a whole. Starting the formulation of the performance metrics used to specify and characterize imagers, the tutorial explains how the subsystem behavior and non-idealities impact on the global imager metrics, thereby setting the basis to specify the subsystems for given global image sensor specs. Such methodology is illustrated in the tutorial via a dedicated, MATLAB-based modeling tool which will be employed to allow the attendees gaining insight on the impact of non-ideal sub-systems behaviors. The tutorial overviews the state-of-the-art regarding: pixels; analog signal processing and read-out circuitry; data conversion circuitry, covering both amplitude data converters (required for 2-D images) and time-to-digital converters (required for 3-D imagers); driving circuits. Practical design recipes are given for all these circuits. Architectures and circuit solutions employed for high dynamic range acquisition and embedded image processing are also reviewed. A case study is included where attendees are exposed to practical considerations to be taken during the design process, including the influence of packaging, optics and camera embedding.
{"title":"Tutorial 1: Foundations and Practical Design of CMOS Image Sensors","authors":"Á. Rodríguez-Vázquez, H. Alshaer, B. Sharif, A. Fahim, Eman El Mandouh, A. Salem, F. Aloul, Hoda S. Abdel-Aty, John F. Dodge, B. Mohammad, Hisham Mohamed","doi":"10.1109/ICECS.2013.6815325","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815325","url":null,"abstract":"CMOS imagers are complex systems whose design requires quite different pieces of expertise, namely: pixels, analog signal processing, pixel readout and analog-to-digital conversion, digital signal processing, output drivers, etc. Confronting the design of new imagers require hence the concourse of multidisciplinary teams. However, because correct operation calls for the close interconnection among the different parts, global knowledge is mandatory for successful design. This is particularly pertinent for the newer generations of smart imagers required for high-end applications and/or requiring ultra-high image capture, on-chip image correction, scene interpretation, high dynamic range capture, etc. All these features demand architectural and circuital innovations and pose significant challenges to designers. Also, the increased interest on sensors capable of capturing 3-D scenes raise new challenges at circuit level related to the necessity to interface pixels different from those employed for 2-D capture, on the one hand, and to extract and convert to digital domain time information, on the other hand. This tutorial addresses the design of smart CMOS imagers by following a comprehensive and complete top-down approach where each subsystem is contemplated and described as a part of a whole. Starting the formulation of the performance metrics used to specify and characterize imagers, the tutorial explains how the subsystem behavior and non-idealities impact on the global imager metrics, thereby setting the basis to specify the subsystems for given global image sensor specs. Such methodology is illustrated in the tutorial via a dedicated, MATLAB-based modeling tool which will be employed to allow the attendees gaining insight on the impact of non-ideal sub-systems behaviors. The tutorial overviews the state-of-the-art regarding: pixels; analog signal processing and read-out circuitry; data conversion circuitry, covering both amplitude data converters (required for 2-D images) and time-to-digital converters (required for 3-D imagers); driving circuits. Practical design recipes are given for all these circuits. Architectures and circuit solutions employed for high dynamic range acquisition and embedded image processing are also reviewed. A case study is included where attendees are exposed to practical considerations to be taken during the design process, including the influence of packaging, optics and camera embedding.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125850483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815485
D. Gan, G. Cai, J. Dias, L. Seneviratne
This paper presents the work on attitude control of quad-rotor UAVs applying an intuitive kinematics representation, called rotation vector. There are three elements in the rotation vector which has clear physical meaning of the rotations and avoids the singularity problem of Euler angles and the unity norm constraint problem of quaternions. Basic definition of the rotation vector and its relation with the object body angle velocity is introduced and used in the 6DOF quadrotor dynamics. Based on the property that the rotation vector rate is equivalent to the body angle velocity when the rotation is small, a simple and intuitive attitude reference is proposed. A proportional-derivative (PD) law is used by integrating the new attitude reference for the attitude control of quad-rotor UAVs. Simulation results prove the efficiency of the new method which provides a new model with intuitive physical meaning for quadrotor UAVs.
{"title":"Attitude control of quad-rotor UAVs using an intuitive kinematics model","authors":"D. Gan, G. Cai, J. Dias, L. Seneviratne","doi":"10.1109/ICECS.2013.6815485","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815485","url":null,"abstract":"This paper presents the work on attitude control of quad-rotor UAVs applying an intuitive kinematics representation, called rotation vector. There are three elements in the rotation vector which has clear physical meaning of the rotations and avoids the singularity problem of Euler angles and the unity norm constraint problem of quaternions. Basic definition of the rotation vector and its relation with the object body angle velocity is introduced and used in the 6DOF quadrotor dynamics. Based on the property that the rotation vector rate is equivalent to the body angle velocity when the rotation is small, a simple and intuitive attitude reference is proposed. A proportional-derivative (PD) law is used by integrating the new attitude reference for the attitude control of quad-rotor UAVs. Simulation results prove the efficiency of the new method which provides a new model with intuitive physical meaning for quadrotor UAVs.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"os-34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127693866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815497
Nada N. Saeed, Mohammed Abdel-Megeed Salem, A. Khamis
The large number of blind and visually impaired individuals in the society has motivated research groups to search for smart solutions that use vision-based technologies to improve their quality of life. This paper describes an Android-based application for object recognition developed to help the blind understand their environment better. This application is based on extracting local features of the object of interest, which are then matched to the corresponding features of objects saved in a knowledge base previously created. The local features are tested against more than one classification method and the results are analyzed. Deploying the application to a Samsung Galaxy Tab, the system is evaluated using a dataset especially developed for this purpose. The dataset contains more than 600 images of twelve objects under several distortions and viewing condition changes. Results of the analysis show that the system achieves real-time performance with high accuracy under most viewing conditions.
{"title":"Android-based object recognition for the visually impaired","authors":"Nada N. Saeed, Mohammed Abdel-Megeed Salem, A. Khamis","doi":"10.1109/ICECS.2013.6815497","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815497","url":null,"abstract":"The large number of blind and visually impaired individuals in the society has motivated research groups to search for smart solutions that use vision-based technologies to improve their quality of life. This paper describes an Android-based application for object recognition developed to help the blind understand their environment better. This application is based on extracting local features of the object of interest, which are then matched to the corresponding features of objects saved in a knowledge base previously created. The local features are tested against more than one classification method and the results are analyzed. Deploying the application to a Samsung Galaxy Tab, the system is evaluated using a dataset especially developed for this purpose. The dataset contains more than 600 images of twelve objects under several distortions and viewing condition changes. Results of the analysis show that the system achieves real-time performance with high accuracy under most viewing conditions.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122306832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815359
Sara Al Maeeni, S. Muhaidat, I. Abualhaol
Research on non-coherent detection for cooperative communications is at an early stage and many fundamental problems are still open. We will be working on an important open problems in broadband cooperative wireless communications. A novel non-coherent detection scheme for a multi-relay cooperative orthogonal frequency division multiplexing (OFDM) wireless system is investigated. We consider a distributed space-time block code (STBC) system over time-varying fading channels, in which source-relay, relay-destination, and source-destination links experience different Doppler spreads. Simulation results demonstrate that the recursive decoder achieves sufficient results even under quasi-static fading assumption.
{"title":"Efficient non-coherent detection techniques for broadband cooperative networks","authors":"Sara Al Maeeni, S. Muhaidat, I. Abualhaol","doi":"10.1109/ICECS.2013.6815359","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815359","url":null,"abstract":"Research on non-coherent detection for cooperative communications is at an early stage and many fundamental problems are still open. We will be working on an important open problems in broadband cooperative wireless communications. A novel non-coherent detection scheme for a multi-relay cooperative orthogonal frequency division multiplexing (OFDM) wireless system is investigated. We consider a distributed space-time block code (STBC) system over time-varying fading channels, in which source-relay, relay-destination, and source-destination links experience different Doppler spreads. Simulation results demonstrate that the recursive decoder achieves sufficient results even under quasi-static fading assumption.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126138326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815552
Goran Molnar, M. Vucic
Popular multiplierless decimation filter is the cascaded-integrator-comb (CIC) filter. However, the magnitude response of this filter has a high passband droop and poor selectivity. One technique for improving the response is sharpening. In the design of sharpened CIC filters, the Kaiser-Hamming method is well established. It results in maximally flat filters. Recently, the weighted least-squares method has been proposed. It improves the response better than the Kaiser-Hamming method. In this paper, we present a method for the design of sharpened CIC filters by using the weighted minimax error criterion. The method is based on the iterative reweighted least-squares procedure. The features of the presented method are illustrated with the design of narrowband and wideband filters. It is shown that the proposed filters are preferable compared to the maximally flat and the weighted least-squares counterparts.
{"title":"Weighted minimax design of sharpened CIC filters","authors":"Goran Molnar, M. Vucic","doi":"10.1109/ICECS.2013.6815552","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815552","url":null,"abstract":"Popular multiplierless decimation filter is the cascaded-integrator-comb (CIC) filter. However, the magnitude response of this filter has a high passband droop and poor selectivity. One technique for improving the response is sharpening. In the design of sharpened CIC filters, the Kaiser-Hamming method is well established. It results in maximally flat filters. Recently, the weighted least-squares method has been proposed. It improves the response better than the Kaiser-Hamming method. In this paper, we present a method for the design of sharpened CIC filters by using the weighted minimax error criterion. The method is based on the iterative reweighted least-squares procedure. The features of the presented method are illustrated with the design of narrowband and wideband filters. It is shown that the proposed filters are preferable compared to the maximally flat and the weighted least-squares counterparts.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131267680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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