Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815332
Kamyar Keikhosravy, Pouya Kamalinejad, S. Mirabbasi, Victor C. M. Leung
In this paper, an ultra wideband analog voltage-mode buffer is presented which can drive a load impedance of 50 Ω. The presented feedback-based buffer uses a compound amplifier which is a parallel combination of a high-DC gain operational amplifier and a operation transconductance amplifier to achieve a high unity gain bandwidth. A proof-of-concept prototype is designed and fabricated in a 0.13 μm CMOS process. The simulation and measurement results of the proposed buffer are in good agreement. The prototype buffer circuit consumes 7.34 mW from a 1.3-V supply, while buffering a 2 GHz sinusoidal input signal with a 0.4 V peak-to-peak (Vpp) amplitude and driving an AC-coupled 50-Ω load.
{"title":"A wideband unity-gain buffer in 0.13-μm CMOS","authors":"Kamyar Keikhosravy, Pouya Kamalinejad, S. Mirabbasi, Victor C. M. Leung","doi":"10.1109/ICECS.2013.6815332","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815332","url":null,"abstract":"In this paper, an ultra wideband analog voltage-mode buffer is presented which can drive a load impedance of 50 Ω. The presented feedback-based buffer uses a compound amplifier which is a parallel combination of a high-DC gain operational amplifier and a operation transconductance amplifier to achieve a high unity gain bandwidth. A proof-of-concept prototype is designed and fabricated in a 0.13 μm CMOS process. The simulation and measurement results of the proposed buffer are in good agreement. The prototype buffer circuit consumes 7.34 mW from a 1.3-V supply, while buffering a 2 GHz sinusoidal input signal with a 0.4 V peak-to-peak (Vpp) amplitude and driving an AC-coupled 50-Ω load.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"516 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116218232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815497
Nada N. Saeed, Mohammed Abdel-Megeed Salem, A. Khamis
The large number of blind and visually impaired individuals in the society has motivated research groups to search for smart solutions that use vision-based technologies to improve their quality of life. This paper describes an Android-based application for object recognition developed to help the blind understand their environment better. This application is based on extracting local features of the object of interest, which are then matched to the corresponding features of objects saved in a knowledge base previously created. The local features are tested against more than one classification method and the results are analyzed. Deploying the application to a Samsung Galaxy Tab, the system is evaluated using a dataset especially developed for this purpose. The dataset contains more than 600 images of twelve objects under several distortions and viewing condition changes. Results of the analysis show that the system achieves real-time performance with high accuracy under most viewing conditions.
{"title":"Android-based object recognition for the visually impaired","authors":"Nada N. Saeed, Mohammed Abdel-Megeed Salem, A. Khamis","doi":"10.1109/ICECS.2013.6815497","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815497","url":null,"abstract":"The large number of blind and visually impaired individuals in the society has motivated research groups to search for smart solutions that use vision-based technologies to improve their quality of life. This paper describes an Android-based application for object recognition developed to help the blind understand their environment better. This application is based on extracting local features of the object of interest, which are then matched to the corresponding features of objects saved in a knowledge base previously created. The local features are tested against more than one classification method and the results are analyzed. Deploying the application to a Samsung Galaxy Tab, the system is evaluated using a dataset especially developed for this purpose. The dataset contains more than 600 images of twelve objects under several distortions and viewing condition changes. Results of the analysis show that the system achieves real-time performance with high accuracy under most viewing conditions.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122306832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815325
Á. Rodríguez-Vázquez, H. Alshaer, B. Sharif, A. Fahim, Eman El Mandouh, A. Salem, F. Aloul, Hoda S. Abdel-Aty, John F. Dodge, B. Mohammad, Hisham Mohamed
CMOS imagers are complex systems whose design requires quite different pieces of expertise, namely: pixels, analog signal processing, pixel readout and analog-to-digital conversion, digital signal processing, output drivers, etc. Confronting the design of new imagers require hence the concourse of multidisciplinary teams. However, because correct operation calls for the close interconnection among the different parts, global knowledge is mandatory for successful design. This is particularly pertinent for the newer generations of smart imagers required for high-end applications and/or requiring ultra-high image capture, on-chip image correction, scene interpretation, high dynamic range capture, etc. All these features demand architectural and circuital innovations and pose significant challenges to designers. Also, the increased interest on sensors capable of capturing 3-D scenes raise new challenges at circuit level related to the necessity to interface pixels different from those employed for 2-D capture, on the one hand, and to extract and convert to digital domain time information, on the other hand. This tutorial addresses the design of smart CMOS imagers by following a comprehensive and complete top-down approach where each subsystem is contemplated and described as a part of a whole. Starting the formulation of the performance metrics used to specify and characterize imagers, the tutorial explains how the subsystem behavior and non-idealities impact on the global imager metrics, thereby setting the basis to specify the subsystems for given global image sensor specs. Such methodology is illustrated in the tutorial via a dedicated, MATLAB-based modeling tool which will be employed to allow the attendees gaining insight on the impact of non-ideal sub-systems behaviors. The tutorial overviews the state-of-the-art regarding: pixels; analog signal processing and read-out circuitry; data conversion circuitry, covering both amplitude data converters (required for 2-D images) and time-to-digital converters (required for 3-D imagers); driving circuits. Practical design recipes are given for all these circuits. Architectures and circuit solutions employed for high dynamic range acquisition and embedded image processing are also reviewed. A case study is included where attendees are exposed to practical considerations to be taken during the design process, including the influence of packaging, optics and camera embedding.
{"title":"Tutorial 1: Foundations and Practical Design of CMOS Image Sensors","authors":"Á. Rodríguez-Vázquez, H. Alshaer, B. Sharif, A. Fahim, Eman El Mandouh, A. Salem, F. Aloul, Hoda S. Abdel-Aty, John F. Dodge, B. Mohammad, Hisham Mohamed","doi":"10.1109/ICECS.2013.6815325","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815325","url":null,"abstract":"CMOS imagers are complex systems whose design requires quite different pieces of expertise, namely: pixels, analog signal processing, pixel readout and analog-to-digital conversion, digital signal processing, output drivers, etc. Confronting the design of new imagers require hence the concourse of multidisciplinary teams. However, because correct operation calls for the close interconnection among the different parts, global knowledge is mandatory for successful design. This is particularly pertinent for the newer generations of smart imagers required for high-end applications and/or requiring ultra-high image capture, on-chip image correction, scene interpretation, high dynamic range capture, etc. All these features demand architectural and circuital innovations and pose significant challenges to designers. Also, the increased interest on sensors capable of capturing 3-D scenes raise new challenges at circuit level related to the necessity to interface pixels different from those employed for 2-D capture, on the one hand, and to extract and convert to digital domain time information, on the other hand. This tutorial addresses the design of smart CMOS imagers by following a comprehensive and complete top-down approach where each subsystem is contemplated and described as a part of a whole. Starting the formulation of the performance metrics used to specify and characterize imagers, the tutorial explains how the subsystem behavior and non-idealities impact on the global imager metrics, thereby setting the basis to specify the subsystems for given global image sensor specs. Such methodology is illustrated in the tutorial via a dedicated, MATLAB-based modeling tool which will be employed to allow the attendees gaining insight on the impact of non-ideal sub-systems behaviors. The tutorial overviews the state-of-the-art regarding: pixels; analog signal processing and read-out circuitry; data conversion circuitry, covering both amplitude data converters (required for 2-D images) and time-to-digital converters (required for 3-D imagers); driving circuits. Practical design recipes are given for all these circuits. Architectures and circuit solutions employed for high dynamic range acquisition and embedded image processing are also reviewed. A case study is included where attendees are exposed to practical considerations to be taken during the design process, including the influence of packaging, optics and camera embedding.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125850483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815563
Chu-Hsiang Chia, Pui-Sun Lei, R. Chang, Tzu-Ying Kao
This paper presents a high-speed DC-DC converter with the adaptive DCM controller and the switch-scaling circuit using TSMC 0.18μm CMOS process. The input voltage is 1.8V and the output voltage is 1.2V. The maximum loading is 300mA and the required passive components are at nano-scale. The proposed DC-DC converter has over 80% efficiency at loading range from 50mA to 300mA. The output ripple is below 10% of the output voltage at all loadings. To minimize the power consumption, a low-power and adaptive DCM controller is proposed to increase the efficiency and also reduce the output ripple when the loading is below 150mA. When the loading is over 200mA, the switch-scaling circuit will turn on the extra power MOS to keep the efficiency. The switching frequency of the proposed converter changes from 200kHz to 50MHz, depending on the loading. The loading boundary between proposed DCM and CCM control is 150mA.
{"title":"A high-speed DC-DC converter with high efficiency at wide loading range","authors":"Chu-Hsiang Chia, Pui-Sun Lei, R. Chang, Tzu-Ying Kao","doi":"10.1109/ICECS.2013.6815563","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815563","url":null,"abstract":"This paper presents a high-speed DC-DC converter with the adaptive DCM controller and the switch-scaling circuit using TSMC 0.18μm CMOS process. The input voltage is 1.8V and the output voltage is 1.2V. The maximum loading is 300mA and the required passive components are at nano-scale. The proposed DC-DC converter has over 80% efficiency at loading range from 50mA to 300mA. The output ripple is below 10% of the output voltage at all loadings. To minimize the power consumption, a low-power and adaptive DCM controller is proposed to increase the efficiency and also reduce the output ripple when the loading is below 150mA. When the loading is over 200mA, the switch-scaling circuit will turn on the extra power MOS to keep the efficiency. The switching frequency of the proposed converter changes from 200kHz to 50MHz, depending on the loading. The loading boundary between proposed DCM and CCM control is 150mA.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127761103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815552
Goran Molnar, M. Vucic
Popular multiplierless decimation filter is the cascaded-integrator-comb (CIC) filter. However, the magnitude response of this filter has a high passband droop and poor selectivity. One technique for improving the response is sharpening. In the design of sharpened CIC filters, the Kaiser-Hamming method is well established. It results in maximally flat filters. Recently, the weighted least-squares method has been proposed. It improves the response better than the Kaiser-Hamming method. In this paper, we present a method for the design of sharpened CIC filters by using the weighted minimax error criterion. The method is based on the iterative reweighted least-squares procedure. The features of the presented method are illustrated with the design of narrowband and wideband filters. It is shown that the proposed filters are preferable compared to the maximally flat and the weighted least-squares counterparts.
{"title":"Weighted minimax design of sharpened CIC filters","authors":"Goran Molnar, M. Vucic","doi":"10.1109/ICECS.2013.6815552","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815552","url":null,"abstract":"Popular multiplierless decimation filter is the cascaded-integrator-comb (CIC) filter. However, the magnitude response of this filter has a high passband droop and poor selectivity. One technique for improving the response is sharpening. In the design of sharpened CIC filters, the Kaiser-Hamming method is well established. It results in maximally flat filters. Recently, the weighted least-squares method has been proposed. It improves the response better than the Kaiser-Hamming method. In this paper, we present a method for the design of sharpened CIC filters by using the weighted minimax error criterion. The method is based on the iterative reweighted least-squares procedure. The features of the presented method are illustrated with the design of narrowband and wideband filters. It is shown that the proposed filters are preferable compared to the maximally flat and the weighted least-squares counterparts.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131267680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815507
L. Mohjazi, M. Al-Qutayri, H. Barada, K. Poon
Femtocells are small base stations used to enhance cellular coverage in an indoor environment. However, dense femtocell deployments can lead to severe performance degradation. This paper adopts a new strategy to self-optimize the pilot power of femtocells by creating disjoint femtocell clusters which are managed by the chosen cluster heads (CHs). Each CH optimizes the coverage of its connected members by applying a multi-objective heuristic based on genetic algorithm. The simulation results show that the proposed approach can significantly reduce both the computational time and the data overhead compared with the centralized power optimization.
{"title":"Clustering based self-optimization of pilot power in dense femtocell deployments using genetic algorithms","authors":"L. Mohjazi, M. Al-Qutayri, H. Barada, K. Poon","doi":"10.1109/ICECS.2013.6815507","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815507","url":null,"abstract":"Femtocells are small base stations used to enhance cellular coverage in an indoor environment. However, dense femtocell deployments can lead to severe performance degradation. This paper adopts a new strategy to self-optimize the pilot power of femtocells by creating disjoint femtocell clusters which are managed by the chosen cluster heads (CHs). Each CH optimizes the coverage of its connected members by applying a multi-objective heuristic based on genetic algorithm. The simulation results show that the proposed approach can significantly reduce both the computational time and the data overhead compared with the centralized power optimization.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128339329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815453
V. Rieger, C. Brendler, Naser Pour Aryan, A. Rothermel
A compact 10-bit current-steering D/A converter in a 0.35 μm CMOS technology is presented. The DAC is designed for active pixel sensor control of a retinal implant. A new current cell has been used to minimize power consumption and reduce glitching. To guarantee monotonicity and to achieve good dynamic and static performance a segmentation level of 4-6 has been used. A triple common-centroid layout technique has been applied and an active area of 0.7 mm2 has been used. The measured differential and integral linearity errors are less than ± 0.2 LSB and ± 0.3 LSB, respectively.
{"title":"A 10-bit current-steering D/A converter for active pixel sensor control","authors":"V. Rieger, C. Brendler, Naser Pour Aryan, A. Rothermel","doi":"10.1109/ICECS.2013.6815453","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815453","url":null,"abstract":"A compact 10-bit current-steering D/A converter in a 0.35 μm CMOS technology is presented. The DAC is designed for active pixel sensor control of a retinal implant. A new current cell has been used to minimize power consumption and reduce glitching. To guarantee monotonicity and to achieve good dynamic and static performance a segmentation level of 4-6 has been used. A triple common-centroid layout technique has been applied and an active area of 0.7 mm2 has been used. The measured differential and integral linearity errors are less than ± 0.2 LSB and ± 0.3 LSB, respectively.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134419653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815541
Kerem Kapucu, C. Dehollain
This work discusses the remote powering link of a passive UHF RFID tag for sensor applications. The design, implementation, and measurements of the base-station antenna, tag antenna, and the rectifier are presented. The base-station antenna is a 50 Ω rectangular patch antenna with a measured far-field gain of 3.6 dBi. The tag antenna is an inductively coupled meandered dipole antenna impedance matched to the tag chip. The measured far-field gain of the tag antenna is 1.2 dBi. The three-stage, differential-input rectifier is measured to deliver 1 mW to a 5 kΩ load with a power conversion efficiency of 65% at a distance of 1.5 meters from the base station. The rectifier is implemented in 0.18 μm UMC CMOS process.
{"title":"Remote powering link for a passive UHF RFID tag for capacitive sensor applications","authors":"Kerem Kapucu, C. Dehollain","doi":"10.1109/ICECS.2013.6815541","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815541","url":null,"abstract":"This work discusses the remote powering link of a passive UHF RFID tag for sensor applications. The design, implementation, and measurements of the base-station antenna, tag antenna, and the rectifier are presented. The base-station antenna is a 50 Ω rectangular patch antenna with a measured far-field gain of 3.6 dBi. The tag antenna is an inductively coupled meandered dipole antenna impedance matched to the tag chip. The measured far-field gain of the tag antenna is 1.2 dBi. The three-stage, differential-input rectifier is measured to deliver 1 mW to a 5 kΩ load with a power conversion efficiency of 65% at a distance of 1.5 meters from the base station. The rectifier is implemented in 0.18 μm UMC CMOS process.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134529223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815548
Yogesh Dilip Save, R. Rakhi, N. D. Shambhulingayya, A. Srivastava, M. R. Das, Saket Choudhary, K. Moudgalya
In this paper, we discuss the implementation of Open Source CAD (Oscad) [1], a complete EDA tool for Electronics and Electrical engineers. The paper illustrates the use of Oscad for circuit design, simulation and PCB design. It also gives implementation details of an in-house developed circuit simulator, Scilab based Mini Circuit Simulator (SMCSim), available in Oscad. The simulator can provide the system of equations for the circuit under test. This feature is unique to Oscad. The paper presents two examples to show the capabilities of Oscad.
{"title":"Oscad: An open source EDA tool for circuit design, simulation, analysis and PCB design","authors":"Yogesh Dilip Save, R. Rakhi, N. D. Shambhulingayya, A. Srivastava, M. R. Das, Saket Choudhary, K. Moudgalya","doi":"10.1109/ICECS.2013.6815548","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815548","url":null,"abstract":"In this paper, we discuss the implementation of Open Source CAD (Oscad) [1], a complete EDA tool for Electronics and Electrical engineers. The paper illustrates the use of Oscad for circuit design, simulation and PCB design. It also gives implementation details of an in-house developed circuit simulator, Scilab based Mini Circuit Simulator (SMCSim), available in Oscad. The simulator can provide the system of equations for the circuit under test. This feature is unique to Oscad. The paper presents two examples to show the capabilities of Oscad.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134599429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815482
A. H. Yüzer, S. Bassam, F. Ghannouchi, S. Demir
This paper presents a proposal for a new memory polynomial modeling technique with non-uniform delay taps to capture the thermal memory effects in power amplifiers. In the proposed modeling structure, each order of the memory polynomial is assigned a different memory delay. The delay profile is an exponentially shaped function, instead of equal unit delays for all memory polynomial branches. Three different metrics, the memory effect modeling ratio (MEMR) and the normalized mean square error (NMSE) and spectrum error (SE) are used to benchmark the proposed exponentially shaped delay profile memorial polynomial model performance against previously published models, namely the memoryless, the unit delay and sparse delay memory based polynomial models. The model coefficients of four models are extracted for three different excitation signals, which were selected as a 64-QAM signal around 2.14 GHz with 20 kHz, 30 kHz and 40 kHz bandwidths, ensuring that the thermal memory effects dominate the electrical memory effects. It is shown that the proposed model outperforms all the previously published models for all three excitation signals used in the experiment.
{"title":"Memory polynomial with shaped memory delay profile and modeling the thermal memory effect","authors":"A. H. Yüzer, S. Bassam, F. Ghannouchi, S. Demir","doi":"10.1109/ICECS.2013.6815482","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815482","url":null,"abstract":"This paper presents a proposal for a new memory polynomial modeling technique with non-uniform delay taps to capture the thermal memory effects in power amplifiers. In the proposed modeling structure, each order of the memory polynomial is assigned a different memory delay. The delay profile is an exponentially shaped function, instead of equal unit delays for all memory polynomial branches. Three different metrics, the memory effect modeling ratio (MEMR) and the normalized mean square error (NMSE) and spectrum error (SE) are used to benchmark the proposed exponentially shaped delay profile memorial polynomial model performance against previously published models, namely the memoryless, the unit delay and sparse delay memory based polynomial models. The model coefficients of four models are extracted for three different excitation signals, which were selected as a 64-QAM signal around 2.14 GHz with 20 kHz, 30 kHz and 40 kHz bandwidths, ensuring that the thermal memory effects dominate the electrical memory effects. It is shown that the proposed model outperforms all the previously published models for all three excitation signals used in the experiment.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133277142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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