Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815422
Abbas Bradai, T. Ahmed, Samir Medjiah
Scalable video coding has drawn great interest in content delivery in many multimedia services thanks to its capability to handle terminal heterogeneity and network conditions variation. In our previous work, and under the umbrella of ENVISION, we have proposed a playout smoothing mechanism to ensure the uniform delivery of the layered stream, by reducing the quality changes that the stream undergoes when adapting to changing network conditions. In this paper we study the resulting video quality, from the final user perception under different network conditions of loss and delays. For that we have adopted the Double Stimulus Impairment Scale (DSIS) method. The results show that the Mean Opinion Score for the smoothed video clips was higher under different network configuration. This confirms the effectiveness of the proposed smoothing mechanism.
{"title":"QoE assessment for SVC live distribution and adaptation: ENVISION case study","authors":"Abbas Bradai, T. Ahmed, Samir Medjiah","doi":"10.1109/ICECS.2013.6815422","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815422","url":null,"abstract":"Scalable video coding has drawn great interest in content delivery in many multimedia services thanks to its capability to handle terminal heterogeneity and network conditions variation. In our previous work, and under the umbrella of ENVISION, we have proposed a playout smoothing mechanism to ensure the uniform delivery of the layered stream, by reducing the quality changes that the stream undergoes when adapting to changing network conditions. In this paper we study the resulting video quality, from the final user perception under different network conditions of loss and delays. For that we have adopted the Double Stimulus Impairment Scale (DSIS) method. The results show that the Mean Opinion Score for the smoothed video clips was higher under different network configuration. This confirms the effectiveness of the proposed smoothing mechanism.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133217468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815435
Janko Katic, S. Rodriguez, A. Rusu
This paper presents an ultra-low power control circuit for a DC-DC boost converter targeting implantable thermoelectric energy harvesting applications. Efficiency of the input converter is enhanced by utilizing zero-current switching technique. Adaptive delay between ON states of switches assures zero-voltage switching of synchronous rectifier and reduces switching losses. The control circuit employing both techniques consumes an average power of 620nW. This allows the converter to operate from harvested power below 5μW. For voltage conversion ratios above 20, the proposed circuits and techniques demonstrate efficiency improvement compared to the state-of-the-art solutions.
{"title":"An efficient boost converter control for thermoelectric energy harvesting","authors":"Janko Katic, S. Rodriguez, A. Rusu","doi":"10.1109/ICECS.2013.6815435","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815435","url":null,"abstract":"This paper presents an ultra-low power control circuit for a DC-DC boost converter targeting implantable thermoelectric energy harvesting applications. Efficiency of the input converter is enhanced by utilizing zero-current switching technique. Adaptive delay between ON states of switches assures zero-voltage switching of synchronous rectifier and reduces switching losses. The control circuit employing both techniques consumes an average power of 620nW. This allows the converter to operate from harvested power below 5μW. For voltage conversion ratios above 20, the proposed circuits and techniques demonstrate efficiency improvement compared to the state-of-the-art solutions.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131663092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815375
Xiao Liu, C. Dehollain
This paper proposes a new way to compensate comparator errors in successive approximation analog-to-digital convertor (SAR ADC). The method adds negatively biased capacitance to traditional binary-scaled compensation, increasing ADC accuracy by up to 20%. A novel digital-to-analog convertor (DAC) structure is introduced to further increase its efficiency, which reduces total capacitance by 80%. According to mathematical and Cadence simulation, the proposed method provides an efficient trade-off between accuracy and conversion speed.
{"title":"A compensation technique for SAR ADC comparator noise","authors":"Xiao Liu, C. Dehollain","doi":"10.1109/ICECS.2013.6815375","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815375","url":null,"abstract":"This paper proposes a new way to compensate comparator errors in successive approximation analog-to-digital convertor (SAR ADC). The method adds negatively biased capacitance to traditional binary-scaled compensation, increasing ADC accuracy by up to 20%. A novel digital-to-analog convertor (DAC) structure is introduced to further increase its efficiency, which reduces total capacitance by 80%. According to mathematical and Cadence simulation, the proposed method provides an efficient trade-off between accuracy and conversion speed.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123892501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815351
Khalfan AlMarashda
Securing video content transmission is a highly demanded subject for various applications and objectives such as privacy in surveillance and military confidentiality. A promising approach called Joint Encryption Compression (JEC) is considered to be a balance between video security and efficiency. JEC approach is based on involving encryption within video compression processes. However, the state of the art JEC approach lacks a major security aspect; a well defined structured framework considering the Video Security Assurance (VSA). The aim of this PhD research1 is to design, implement and evaluate an efficient VSA framework based on JEC for surveillance application. This framework will involve the combination of a set of cryptographic functionalities such as signing, hashing and encryption to achieve the VSA objectives. The proposed framework will utilize a set of classification studies and methodologies such as selectivity, non-equality and scalability in order to develop an efficient computation adaptation approach.
{"title":"Video security assurance framework based on efficient Joint Cryptography Compression approach","authors":"Khalfan AlMarashda","doi":"10.1109/ICECS.2013.6815351","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815351","url":null,"abstract":"Securing video content transmission is a highly demanded subject for various applications and objectives such as privacy in surveillance and military confidentiality. A promising approach called Joint Encryption Compression (JEC) is considered to be a balance between video security and efficiency. JEC approach is based on involving encryption within video compression processes. However, the state of the art JEC approach lacks a major security aspect; a well defined structured framework considering the Video Security Assurance (VSA). The aim of this PhD research1 is to design, implement and evaluate an efficient VSA framework based on JEC for surveillance application. This framework will involve the combination of a set of cryptographic functionalities such as signing, hashing and encryption to achieve the VSA objectives. The proposed framework will utilize a set of classification studies and methodologies such as selectivity, non-equality and scalability in order to develop an efficient computation adaptation approach.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114328616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815488
S. Baron, Michelle S. Wangham, C. Zeferino
Networks-on-Chip (NoCs) are vulnerable to security attacks, which can degrade the network performance, reduce its availability or even block the entire network. In this context, this work aimed at increasing the availability of a NoC by means of the implementation of hardware-based mechanisms that filter malicious packets injected into the network by an attacking core. The mechanisms discard packets that affect the network availability, and regulate the injection rate of communication flows that attempt to consume a bandwidth higher than a limit specified by the system designer. The security mechanisms were described in VHDL and synthesized to an ASIC technology. Results demonstrate that they are effective in improving the network availability, with a reduced silicon overhead and low impact to the NoC performance.
{"title":"Security mechanisms to improve the availability of a Network-on-Chip","authors":"S. Baron, Michelle S. Wangham, C. Zeferino","doi":"10.1109/ICECS.2013.6815488","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815488","url":null,"abstract":"Networks-on-Chip (NoCs) are vulnerable to security attacks, which can degrade the network performance, reduce its availability or even block the entire network. In this context, this work aimed at increasing the availability of a NoC by means of the implementation of hardware-based mechanisms that filter malicious packets injected into the network by an attacking core. The mechanisms discard packets that affect the network availability, and regulate the injection rate of communication flows that attempt to consume a bandwidth higher than a limit specified by the system designer. The security mechanisms were described in VHDL and synthesized to an ASIC technology. Results demonstrate that they are effective in improving the network availability, with a reduced silicon overhead and low impact to the NoC performance.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116466311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815390
Alaa A. S. Al-Rubaie, C. Tsimenidis, M. Johnston, B. Sharif
Physical layer network coding (PNC) is a novel technique that allows two users to exchange messages in a wireless network. The most significant feature of PNC is the exploitation of interference at a relay due to incoming signals from two users, allowing an increase in throughput. In this paper, Extrinsic Information Transfer (ExIT) charts are employed to evaluate the performance of bit-interleaved coded modulation with iterative decoding (BICM-ID) combined with PNC. We address critical design issues to enhance decoding performance and provide analytical bounds on the performance. The analysis is extended for PNC employing Turbo and Low-Density Parity-Check (LDPC) codes to compare the performance with BICM-ID on the AWGN channel. Our results show that BICM-ID with PNC performs very similarly to a turbo-coded PNC scheme but, surprisingly, it outperforms a LDPC-coded PNC scheme, due to the Sum-Product decoding algorithm, which is less robust to unreliable symbols broadcast from the relay and needs more iterations to reach convergence. This shows that when considering trade-offs between performance and complexity, BICM-ID is an attractive coding scheme for wireless relay networks employing PNC.
物理层网络编码(PNC)是一种允许两个用户在无线网络中交换消息的新技术。PNC最重要的特点是利用来自两个用户的输入信号在中继上产生的干扰，从而增加吞吐量。本文采用外部信息传输(Extrinsic Information Transfer, ExIT)图来评价比特交织迭代译码编码调制(BICM-ID)与PNC相结合的性能。我们解决了关键的设计问题，以提高解码性能，并提供性能的分析边界。将分析扩展到采用Turbo和低密度奇偶校验(LDPC)码的PNC，以比较其在AWGN信道上与BICM-ID的性能。我们的研究结果表明，带有PNC的BICM-ID的性能与涡轮编码的PNC方案非常相似，但令人惊讶的是，它优于ldpc编码的PNC方案，这是由于和积解码算法，该算法对来自中继的不可靠符号广播的鲁棒性较差，需要更多的迭代才能达到收敛。这表明，在考虑性能和复杂性之间的权衡时，BICM-ID是采用PNC的无线中继网络的一种有吸引力的编码方案。
{"title":"Performance and ExIT chart analysis of BICM-ID for physical layer network coding","authors":"Alaa A. S. Al-Rubaie, C. Tsimenidis, M. Johnston, B. Sharif","doi":"10.1109/ICECS.2013.6815390","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815390","url":null,"abstract":"Physical layer network coding (PNC) is a novel technique that allows two users to exchange messages in a wireless network. The most significant feature of PNC is the exploitation of interference at a relay due to incoming signals from two users, allowing an increase in throughput. In this paper, Extrinsic Information Transfer (ExIT) charts are employed to evaluate the performance of bit-interleaved coded modulation with iterative decoding (BICM-ID) combined with PNC. We address critical design issues to enhance decoding performance and provide analytical bounds on the performance. The analysis is extended for PNC employing Turbo and Low-Density Parity-Check (LDPC) codes to compare the performance with BICM-ID on the AWGN channel. Our results show that BICM-ID with PNC performs very similarly to a turbo-coded PNC scheme but, surprisingly, it outperforms a LDPC-coded PNC scheme, due to the Sum-Product decoding algorithm, which is less robust to unreliable symbols broadcast from the relay and needs more iterations to reach convergence. This shows that when considering trade-offs between performance and complexity, BICM-ID is an attractive coding scheme for wireless relay networks employing PNC.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123460786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815355
Bassant Selim, S. Muhaidat, N. Alsindi, Mohammed Ismail El-Naggar
Spectrum sensing is an essential feature of Cognitive Radio (CR) that enables the nodes to determine the availability of the spectrum to be exploited. Recent work on CR propose localization of Primary Users (PUs) which enables CR nodes, also called Secondary Users (SUs), to utilize gray spectrum (occupied by PUs) by limiting their transmission power and hence not causing interference to PUs. Techniques for cooperative localization of PU are inspired from localization in Wireless Sensor Networks. There are a number of algorithms for the enhancement of these techniques in the context of CR. The intended work, presented in this paper, aims to define an algorithm for cooperative PU localization in Cognitive Radio Networks based on an optimal tolerated error. This approach would minimize cooperation overhead while maximizing the probability of detection. The overhead refers to any extra sensing time, delay, energy and operations devoted to cooperative sensing and any performance degradation caused by cooperative sensing [1].
{"title":"Optimal cooperative primary user localization in Cognitive Radio networks","authors":"Bassant Selim, S. Muhaidat, N. Alsindi, Mohammed Ismail El-Naggar","doi":"10.1109/ICECS.2013.6815355","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815355","url":null,"abstract":"Spectrum sensing is an essential feature of Cognitive Radio (CR) that enables the nodes to determine the availability of the spectrum to be exploited. Recent work on CR propose localization of Primary Users (PUs) which enables CR nodes, also called Secondary Users (SUs), to utilize gray spectrum (occupied by PUs) by limiting their transmission power and hence not causing interference to PUs. Techniques for cooperative localization of PU are inspired from localization in Wireless Sensor Networks. There are a number of algorithms for the enhancement of these techniques in the context of CR. The intended work, presented in this paper, aims to define an algorithm for cooperative PU localization in Cognitive Radio Networks based on an optimal tolerated error. This approach would minimize cooperation overhead while maximizing the probability of detection. The overhead refers to any extra sensing time, delay, energy and operations devoted to cooperative sensing and any performance degradation caused by cooperative sensing [1].","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124431654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815528
F. D. Baumgratz, S. Ferreira, S. Bampi
This paper presents an RF system-level design of a Spectrum Sensing Direct Conversion Receiver for Cognitive Radios. An extension to the recently developed IEEE 802.22 standard from 54MHz to 4GHz is proposed to take advantage of additional underused frequency bands. The proposed architecture is designed to detect IEEE 802.22, IEEE 802.16, and LTE signals as incumbents. The receiver is composed of low noise amplifier (LNA), mixer and variable gain amplifier (VGA) with noise figure, 1dB compression point, second and third order intermodulation point, and gain defined through budget simulation. Results show that severe linearity requirements are imposed on such receiver due to the strong interferers entering in the wideband receiver.
{"title":"RF system level design for a Spectrum Sensing Receiver","authors":"F. D. Baumgratz, S. Ferreira, S. Bampi","doi":"10.1109/ICECS.2013.6815528","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815528","url":null,"abstract":"This paper presents an RF system-level design of a Spectrum Sensing Direct Conversion Receiver for Cognitive Radios. An extension to the recently developed IEEE 802.22 standard from 54MHz to 4GHz is proposed to take advantage of additional underused frequency bands. The proposed architecture is designed to detect IEEE 802.22, IEEE 802.16, and LTE signals as incumbents. The receiver is composed of low noise amplifier (LNA), mixer and variable gain amplifier (VGA) with noise figure, 1dB compression point, second and third order intermodulation point, and gain defined through budget simulation. Results show that severe linearity requirements are imposed on such receiver due to the strong interferers entering in the wideband receiver.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125840543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815376
H. Mostafa, Y. Ismail
Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, a novel VTC circuit is proposed which achieves high linearity and large dynamic analog input range. This new VTC circuit can be used in a 5 bit time-based ADC with no sample and hold circuit for analog input frequencies up to 4 GHz.
{"title":"Highly-linear voltage-to-time converter (VTC) circuit for time-based analog-to-digital converters (T-ADCs)","authors":"H. Mostafa, Y. Ismail","doi":"10.1109/ICECS.2013.6815376","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815376","url":null,"abstract":"Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, a novel VTC circuit is proposed which achieves high linearity and large dynamic analog input range. This new VTC circuit can be used in a 5 bit time-based ADC with no sample and hold circuit for analog input frequencies up to 4 GHz.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124801786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICECS.2013.6815557
S. Chouhan, K. Halonen
Low Drop Out (LDO) Regulator is used to maintain steady voltage in power generation blocks. Voltage reference is the most important component in LDO design. The output voltage of LDO is a multiple of the reference voltage. Band gap voltage reference circuits (BVRC) are utilized in LDO for this purpose. The output voltage of a bandgap reference circuit is based on the bandgap voltage of the semiconductor: a well-defined, temperature independent physical value. Diodes and Bipolar Junction Transistors (BJTs) are used for implementing BVRC. In sub-micron CMOS digital processes, lack of lateral pnps can be seen as a disadvantage. In this work, we are proposing a completely MOS based voltage reference scheme. The proposed voltage reference has been implemented using standard 0.18 μm CMOS technology. It generates a constant reference voltage of 594.72mV. The operating supply voltage for the proposed circuit ranges from 1.25V to 2V. The layout area is 0.0055 mm2, with maximum power dissipation of 2.5 μW, simulated at 2V supply voltage. The operating temperature ranges from -10 °C to 110 °C with a temperature coefficient of 4.8 ppm/°C. The simulated line sensitivity is 0.2mV/V, with the supply voltage variation from 1.25V to 2V and the PSRR at 100Hz is -67dB.
{"title":"A micro-power 4.8 ppm/°C CMOS voltage reference circuit for linear drop out regulator used in RFID","authors":"S. Chouhan, K. Halonen","doi":"10.1109/ICECS.2013.6815557","DOIUrl":"https://doi.org/10.1109/ICECS.2013.6815557","url":null,"abstract":"Low Drop Out (LDO) Regulator is used to maintain steady voltage in power generation blocks. Voltage reference is the most important component in LDO design. The output voltage of LDO is a multiple of the reference voltage. Band gap voltage reference circuits (BVRC) are utilized in LDO for this purpose. The output voltage of a bandgap reference circuit is based on the bandgap voltage of the semiconductor: a well-defined, temperature independent physical value. Diodes and Bipolar Junction Transistors (BJTs) are used for implementing BVRC. In sub-micron CMOS digital processes, lack of lateral pnps can be seen as a disadvantage. In this work, we are proposing a completely MOS based voltage reference scheme. The proposed voltage reference has been implemented using standard 0.18 μm CMOS technology. It generates a constant reference voltage of 594.72mV. The operating supply voltage for the proposed circuit ranges from 1.25V to 2V. The layout area is 0.0055 mm2, with maximum power dissipation of 2.5 μW, simulated at 2V supply voltage. The operating temperature ranges from -10 °C to 110 °C with a temperature coefficient of 4.8 ppm/°C. The simulated line sensitivity is 0.2mV/V, with the supply voltage variation from 1.25V to 2V and the PSRR at 100Hz is -67dB.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128380778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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