Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401812
C. Bordas, K. Grenier, D. Dubuc, M. Paillard, J. Cazaux
This paper presents the design and fabrication of an impedance tuner integrated thanks an RF-MEMS technology which is fully compatible with IC. The developed technology aims to fabricate RF-MEMS devices which are able to handle medium RF-power and also targets to be compatible with IC integration. Concerning the design, we have defined an appropriate methodology, specifically developed for RF-MEMS devices, which takes into account the large dispersion on the RF-MEMS contact quality and then down state capacitor value, and the values of generated impedances that we want as large as possible. The prospective of this work is to associate monolithically a power amplifier with this high Q (and then low losses) tuner in order to be able to tune the PAE or even the operating class.
{"title":"PRIME 2007 High quality medium power RF-MEMS based impedance tuner for smart microsystem integration","authors":"C. Bordas, K. Grenier, D. Dubuc, M. Paillard, J. Cazaux","doi":"10.1109/RME.2007.4401812","DOIUrl":"https://doi.org/10.1109/RME.2007.4401812","url":null,"abstract":"This paper presents the design and fabrication of an impedance tuner integrated thanks an RF-MEMS technology which is fully compatible with IC. The developed technology aims to fabricate RF-MEMS devices which are able to handle medium RF-power and also targets to be compatible with IC integration. Concerning the design, we have defined an appropriate methodology, specifically developed for RF-MEMS devices, which takes into account the large dispersion on the RF-MEMS contact quality and then down state capacitor value, and the values of generated impedances that we want as large as possible. The prospective of this work is to associate monolithically a power amplifier with this high Q (and then low losses) tuner in order to be able to tune the PAE or even the operating class.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124382768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401831
G. M. Lazzerini, M. Dei, P. Bruschi, M. Piotto
An analog circuit for the compensation of pressure effects in thermal flow meters is presented. The result is obtained by modulating the power delivered to the heater by means of a feedback loop that senses the pressure variations with no need of an additional pressure sensor. A possible system architecture is proposed and the effectiveness of the method is demonstrated by means of VHDL-AMS simulations.
{"title":"VHDL-AMS modeling of an integrated gas flow sensor readout channel with pressure compensation.","authors":"G. M. Lazzerini, M. Dei, P. Bruschi, M. Piotto","doi":"10.1109/RME.2007.4401831","DOIUrl":"https://doi.org/10.1109/RME.2007.4401831","url":null,"abstract":"An analog circuit for the compensation of pressure effects in thermal flow meters is presented. The result is obtained by modulating the power delivered to the heater by means of a feedback loop that senses the pressure variations with no need of an additional pressure sensor. A possible system architecture is proposed and the effectiveness of the method is demonstrated by means of VHDL-AMS simulations.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117200908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401832
A. ALii, Y. Leblebici
This article presents a power-efficient and low- voltage CMOS output driver circuit based on low-voltage differential signaling (LVDS) standard. To reduce the ringing at the output of the proposed driver circuit and simultaneously keep the power consumption low, a new technique has been applied to control the output voltage slew. A pre-driver circuit is also utilized to have a very low total equivalent input capacitance of 50 fF. Designed in 0.18 mum CMOS technology, the entire output driver circuit including the input pre-driver, draws only 5.6 mArms while the output voltage swing is VOD = 400 mV and the other specs are compliant with the LVDS requirements.
提出了一种基于低压差分信号(LVDS)标准的低功耗、低电压CMOS输出驱动电路。为了减少驱动电路输出端的振铃，同时保持低功耗，采用了一种新的技术来控制输出电压的变化。预驱动电路也被用于具有50ff的非常低的总等效输入电容。采用0.18 μ m CMOS技术设计，整个输出驱动电路(包括输入前置驱动器)的功耗仅为5.6 mArms，输出电压摆幅为VOD = 400 mV，其他规格均符合LVDS要求。
{"title":"A power-efficient LVDS driver circuit in 0.18-μm CMOS technology","authors":"A. ALii, Y. Leblebici","doi":"10.1109/RME.2007.4401832","DOIUrl":"https://doi.org/10.1109/RME.2007.4401832","url":null,"abstract":"This article presents a power-efficient and low- voltage CMOS output driver circuit based on low-voltage differential signaling (LVDS) standard. To reduce the ringing at the output of the proposed driver circuit and simultaneously keep the power consumption low, a new technique has been applied to control the output voltage slew. A pre-driver circuit is also utilized to have a very low total equivalent input capacitance of 50 fF. Designed in 0.18 mum CMOS technology, the entire output driver circuit including the input pre-driver, draws only 5.6 mArms while the output voltage swing is VOD = 400 mV and the other specs are compliant with the LVDS requirements.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117248272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401842
W. Tatinian, G. Jacquemod, F. Ben Abdeljelil, L. Carpineto
This paper shows the feasibility of combining rotary traveling wave (RTW) oscillator and frequency switch tuning compensation based on a capacitor network to achieve a temperature and process variations robustness of voltage controlled oscillators (VCO). This concept has been proved by combining transistor level simulations for the active part and electromagnetic simulations for the transmission lines. Global system specification have also been checked with high level phase locked loop (PLL) modeling.
{"title":"RTW VCO with switched-capacitor tuning for satellite communication applications","authors":"W. Tatinian, G. Jacquemod, F. Ben Abdeljelil, L. Carpineto","doi":"10.1109/RME.2007.4401842","DOIUrl":"https://doi.org/10.1109/RME.2007.4401842","url":null,"abstract":"This paper shows the feasibility of combining rotary traveling wave (RTW) oscillator and frequency switch tuning compensation based on a capacitor network to achieve a temperature and process variations robustness of voltage controlled oscillators (VCO). This concept has been proved by combining transistor level simulations for the active part and electromagnetic simulations for the transmission lines. Global system specification have also been checked with high level phase locked loop (PLL) modeling.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114299496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401823
H. Panhofer
This paper presents a current measurement system operating in an automotive environment. The architecture incorporates a SigmaDelta modulator with a common-mode control circuit. A new technique of error compensation of circuit imperfections is presented. An experimental prototype has been produced that achieves a resolution of over 12 bits. Results show that the proposed technique improves the common-mode rejection ratio of the system.
{"title":"A current measurement system for automotive applications","authors":"H. Panhofer","doi":"10.1109/RME.2007.4401823","DOIUrl":"https://doi.org/10.1109/RME.2007.4401823","url":null,"abstract":"This paper presents a current measurement system operating in an automotive environment. The architecture incorporates a SigmaDelta modulator with a common-mode control circuit. A new technique of error compensation of circuit imperfections is presented. An experimental prototype has been produced that achieves a resolution of over 12 bits. Results show that the proposed technique improves the common-mode rejection ratio of the system.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"24 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126063550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401821
A. Boudabous, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi
In this paper, we present an efficient hardware/software (HW/SW) implementation of the vector median filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using muClinux as operating system. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.
{"title":"HW/SW FPGA implementation of Vector Median Filter","authors":"A. Boudabous, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi","doi":"10.1109/RME.2007.4401821","DOIUrl":"https://doi.org/10.1109/RME.2007.4401821","url":null,"abstract":"In this paper, we present an efficient hardware/software (HW/SW) implementation of the vector median filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using muClinux as operating system. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131094970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401867
Y. D. Gokdel, S. Talay, G. Dundar
In this paper, different solutions to the saturation problem of the integrator building block of sigma-delta (SD) modulators are proposed. Saturation causes an error that limits the dynamic input range of SD A/D converters and consequently decreases its SNR. The proposed structure, using a variable gain integrator followed by a non-uniform quantizer as companding, makes the usage of higher input levels to the A/D converter possible. Also with speech signals in which very high and very low signals reside, this architecture performs much better.
{"title":"Adaptive high performance ΣΔ modulator designs","authors":"Y. D. Gokdel, S. Talay, G. Dundar","doi":"10.1109/RME.2007.4401867","DOIUrl":"https://doi.org/10.1109/RME.2007.4401867","url":null,"abstract":"In this paper, different solutions to the saturation problem of the integrator building block of sigma-delta (SD) modulators are proposed. Saturation causes an error that limits the dynamic input range of SD A/D converters and consequently decreases its SNR. The proposed structure, using a variable gain integrator followed by a non-uniform quantizer as companding, makes the usage of higher input levels to the A/D converter possible. Also with speech signals in which very high and very low signals reside, this architecture performs much better.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131143959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401866
A. Padovani, A. Chimenton, P. Olivo, P. Fantini, L. Vendrame, S. Mennillo
The continuous scaling of physical dimensions has strongly increased circuit performance variability and the traditional corner-case methodology is becoming unreliable. As a consequence, there is an urgent need for new and more accurate statistical models. In this scenario, the purpose of this paper is twofold: 1) to give the reader the basic concepts of statistical modeling, and 2) to discuss a viable statistical approach that could be adopted into a traditional IC design flow for the next technology generations.
{"title":"Statistical methodologies for integrated circuits design","authors":"A. Padovani, A. Chimenton, P. Olivo, P. Fantini, L. Vendrame, S. Mennillo","doi":"10.1109/RME.2007.4401866","DOIUrl":"https://doi.org/10.1109/RME.2007.4401866","url":null,"abstract":"The continuous scaling of physical dimensions has strongly increased circuit performance variability and the traditional corner-case methodology is becoming unreliable. As a consequence, there is an urgent need for new and more accurate statistical models. In this scenario, the purpose of this paper is twofold: 1) to give the reader the basic concepts of statistical modeling, and 2) to discuss a viable statistical approach that could be adopted into a traditional IC design flow for the next technology generations.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133620106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401836
A. Ghio, S. Pischiutta
We present here a hardware-friendly structure for the support vector machine (SVM), useful to implement its feedforward phase on resource limited devices, such as field programmable gate arrays (FPGAs), on which a floating-point unit is seldom available. We tested our proposal using an artificial machine-vision benchmark dataset for automotive applications.
{"title":"A Support Vector Machine based pedestrian recognition system on resource-limited hardware architectures","authors":"A. Ghio, S. Pischiutta","doi":"10.1109/RME.2007.4401836","DOIUrl":"https://doi.org/10.1109/RME.2007.4401836","url":null,"abstract":"We present here a hardware-friendly structure for the support vector machine (SVM), useful to implement its feedforward phase on resource limited devices, such as field programmable gate arrays (FPGAs), on which a floating-point unit is seldom available. We tested our proposal using an artificial machine-vision benchmark dataset for automotive applications.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131466955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401818
M. Fons, F. Fons, E. Cantó
Nowadays biometrics and embedded systems technologies bring the required means to face those security challenges in the current technological age. The electronic age points to the embedded security as one efficient solution for those applications where confidential treatment of the information is needed. Moreover, the genuine biometric characteristics of each individual become the most reliable features to be used as personal identifiers in front of the world, replacing those low-security tokens such as ID cards, PINs and passwords. Following this direction, the HW-SW co-design of a fingerprint-based personal recognition system embedded on a dynamically reconfigurable platform is suggested in this work. The selected system architecture provides the power to design these high performance applications at low cost.
{"title":"Embedded security: New trends in personal recognition systems","authors":"M. Fons, F. Fons, E. Cantó","doi":"10.1109/RME.2007.4401818","DOIUrl":"https://doi.org/10.1109/RME.2007.4401818","url":null,"abstract":"Nowadays biometrics and embedded systems technologies bring the required means to face those security challenges in the current technological age. The electronic age points to the embedded security as one efficient solution for those applications where confidential treatment of the information is needed. Moreover, the genuine biometric characteristics of each individual become the most reliable features to be used as personal identifiers in front of the world, replacing those low-security tokens such as ID cards, PINs and passwords. Following this direction, the HW-SW co-design of a fingerprint-based personal recognition system embedded on a dynamically reconfigurable platform is suggested in this work. The selected system architecture provides the power to design these high performance applications at low cost.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129681209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：