Pub Date : 2007-07-01DOI: 10.1109/RME.2007.4401835
Y. Luque, E. Kerhervé, N. Deltimple, D. Belot
This paper describes the feasibility of a power amplifier (PA) in 0.13mum CMOS technology from STMicroelectronics. It is designed for the UMTS W-CDMA standard. This power amplifier provides 33 dBm maximal output power with 60% of power added efficiency (PAE) at 1.95 GHz. This standard requires linearity from -20 dBm till 24 dBm output power. The linear gain is 16.7 dB and the compression point (OCP1) is 28.25 dBm. In order to fulfil UMTS W-CDMA specifications, especially on linearity, the maximum 24dBm of output power required are reached in a linear class of operation.
{"title":"A 0.13 μm CMOS stacked folded fully differential PA structure for W-CDMA Application","authors":"Y. Luque, E. Kerhervé, N. Deltimple, D. Belot","doi":"10.1109/RME.2007.4401835","DOIUrl":"https://doi.org/10.1109/RME.2007.4401835","url":null,"abstract":"This paper describes the feasibility of a power amplifier (PA) in 0.13mum CMOS technology from STMicroelectronics. It is designed for the UMTS W-CDMA standard. This power amplifier provides 33 dBm maximal output power with 60% of power added efficiency (PAE) at 1.95 GHz. This standard requires linearity from -20 dBm till 24 dBm output power. The linear gain is 16.7 dB and the compression point (OCP1) is 28.25 dBm. In order to fulfil UMTS W-CDMA specifications, especially on linearity, the maximum 24dBm of output power required are reached in a linear class of operation.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"1884 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128707459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-01DOI: 10.1109/RME.2007.4401863
P. Camino, D. Dallet, B. Quertier, A. Baudry, G. Comoretto, B. Le Gal
This study was initiated in the frame of the 2-stage, 32-demultiplexed input digital filter of the large correlator system of the ALMA (Atacama Large Millimeter Array) interferometer project. The main goal of this work was to reduce the power consumption of the implemented architecture in large FPGAs by optimizing the amount of logic elements. A modified structure of the CIC (cascaded integrator comb) filter for a time demultiplexed architecture is investigated. Different implementations are discussed and compared in terms of performances (complexity, power consumption). We demonstrate that a multistage architecture significantly improves the power dissipation.
{"title":"A decimation filter for a very large band signal in radioastronomy","authors":"P. Camino, D. Dallet, B. Quertier, A. Baudry, G. Comoretto, B. Le Gal","doi":"10.1109/RME.2007.4401863","DOIUrl":"https://doi.org/10.1109/RME.2007.4401863","url":null,"abstract":"This study was initiated in the frame of the 2-stage, 32-demultiplexed input digital filter of the large correlator system of the ALMA (Atacama Large Millimeter Array) interferometer project. The main goal of this work was to reduce the power consumption of the implemented architecture in large FPGAs by optimizing the amount of logic elements. A modified structure of the CIC (cascaded integrator comb) filter for a time demultiplexed architecture is investigated. Different implementations are discussed and compared in terms of performances (complexity, power consumption). We demonstrate that a multistage architecture significantly improves the power dissipation.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128966982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-01DOI: 10.1109/RME.2007.4401814
A. Mariano, D. Dallet, Y. Deval, J. Bégueret
A High-Speed Multi-Bit Bandpass Continuous- Time Delta-Sigma Modulator is presented in this paper. This modulator samples at high-IF signals, performing the direct conversion in the modern RF front-end receivers. In order to improve the design flexibility, an advanced design methodology is used. This methodology is very interesting for complex mixed-signal IC design, since it combines behavioral models and transistor level models in the same environment, reducing the simulation time.
{"title":"High-speed multi-bit continuous-time bandpass delta-sigma modulator","authors":"A. Mariano, D. Dallet, Y. Deval, J. Bégueret","doi":"10.1109/RME.2007.4401814","DOIUrl":"https://doi.org/10.1109/RME.2007.4401814","url":null,"abstract":"A High-Speed Multi-Bit Bandpass Continuous- Time Delta-Sigma Modulator is presented in this paper. This modulator samples at high-IF signals, performing the direct conversion in the modern RF front-end receivers. In order to improve the design flexibility, an advanced design methodology is used. This methodology is very interesting for complex mixed-signal IC design, since it combines behavioral models and transistor level models in the same environment, reducing the simulation time.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122634733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-01DOI: 10.1109/RME.2007.4401854
P. Crombez, J. Craninckx, M. Steyaert
To limit design time for the large range of specifications resulting from the multitude of modern communications standards, a good design strategy for analog circuits is essential, even within a given building block. This paper presents an efficient approach to design biquadratic sections for a low-pass baseband filter based on the gm-C architecture. Starting from high-level specifications, the proposed methodology completely determines the biquad's architecture level for linearity and power optimization. As an illustration, a 10 MHz bandwidth Butterworth biquad section optimized for power and linearity applying the proposed design flow has been successfully designed in a 0.13 mum CMOS technology with a 1.2V supply voltage. It achieves a SFDR of 67 dB for a power consumption of only 3 mW.
为了限制由众多现代通信标准导致的大范围规格的设计时间，即使在给定的构建块内，良好的模拟电路设计策略也是必不可少的。本文提出了一种基于gm-C结构的低通基带滤波器双二次段的有效设计方法。从高级规格开始，提出的方法完全决定了biquad的线性度和功率优化的架构水平。作为一个例子，应用所提出的设计流程，在0.13 μ m CMOS技术和1.2V电源电压下，成功地设计了一个针对功率和线性度进行优化的10 MHz带宽巴特沃斯双极截面。它实现了67 dB的SFDR，功耗仅为3 mW。
{"title":"A linearity and power efficient design strategy for architecture optimization of gm-C biquadratic filters","authors":"P. Crombez, J. Craninckx, M. Steyaert","doi":"10.1109/RME.2007.4401854","DOIUrl":"https://doi.org/10.1109/RME.2007.4401854","url":null,"abstract":"To limit design time for the large range of specifications resulting from the multitude of modern communications standards, a good design strategy for analog circuits is essential, even within a given building block. This paper presents an efficient approach to design biquadratic sections for a low-pass baseband filter based on the gm-C architecture. Starting from high-level specifications, the proposed methodology completely determines the biquad's architecture level for linearity and power optimization. As an illustration, a 10 MHz bandwidth Butterworth biquad section optimized for power and linearity applying the proposed design flow has been successfully designed in a 0.13 mum CMOS technology with a 1.2V supply voltage. It achieves a SFDR of 67 dB for a power consumption of only 3 mW.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117280870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-01DOI: 10.1109/RME.2007.4401870
F. Svelto
In nanometer CMOS technologies, several effects emerge due to short channel-lengths. Some of the most important ones are velocity saturation and gate leakage currents. As a result different transistor models are required to allow accurate prediction of analog circuit performance. The transconductance and speed are both limited by velocity saturation. Also noise and mismatch suffer from smaller channel lengths, as a result of the thinner gate oxides used. Moreover the supply voltage has been reduced to values around 1 Volt, creating new challenges for analog circuit design.
{"title":"State of the art and perspectives in RF and mm-wave microelectronics","authors":"F. Svelto","doi":"10.1109/RME.2007.4401870","DOIUrl":"https://doi.org/10.1109/RME.2007.4401870","url":null,"abstract":"In nanometer CMOS technologies, several effects emerge due to short channel-lengths. Some of the most important ones are velocity saturation and gate leakage currents. As a result different transistor models are required to allow accurate prediction of analog circuit performance. The transconductance and speed are both limited by velocity saturation. Also noise and mismatch suffer from smaller channel lengths, as a result of the thinner gate oxides used. Moreover the supply voltage has been reduced to values around 1 Volt, creating new challenges for analog circuit design.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129414493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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