Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401852
P. Freitas, G. Billiot, J. Bégueret, H. Lapuyade
This paper reviews two basic analog circuits that employ new capabilities brought about by independently driven double gate CMOS transistors (IDGMOS). The subject of the first review is a 1 V supply voltage follower that uses IDGMOS to increase the input range up to the supply voltage and to enhance the biasing circuit of the follower. The second looks at a new general method to make fully balanced differential amplifiers (FBAs) with compact common-mode feed back. IDGMOS FBAs perform complete transistor reuse without using any extra device to execute the feed-back amplifier functions, i.e. error evaluation and amplification. An application of this is illustrated with the simulation of a simple 1-stage differential amplifier with 38 dB gain and a 90.3 degree phase margin. The complete feed back loop includes the aforementioned voltage follower. The common-mode open loop gain is only about 21 dB but the common-mode reference voltage range, within 10% relative error, remains between 0.3 V and 0.9 V.
本文综述了采用独立驱动双栅CMOS晶体管(IDGMOS)带来的新功能的两种基本模拟电路。第一个回顾的主题是一个1 V电源电压跟随器，它使用IDGMOS将输入范围增加到电源电压，并增强跟随器的偏置电路。第二部分研究了一种新的通用方法来制作具有紧凑共模反馈的全平衡差分放大器(FBAs)。IDGMOS FBAs无需使用任何额外的器件来执行反馈放大器功能，即误差评估和放大，即可完成晶体管的完全重用。通过对增益为38db、相位裕度为90.3度的简单1级差分放大器的仿真，说明了该方法的应用。完整的反馈回路包括前面提到的电压跟随器。共模开环增益仅为21 dB左右，但共模参考电压范围在0.3 V ~ 0.9 V之间，相对误差在10%以内。
{"title":"Analog circuit design based on independently driven double gate MOSfet","authors":"P. Freitas, G. Billiot, J. Bégueret, H. Lapuyade","doi":"10.1109/RME.2007.4401852","DOIUrl":"https://doi.org/10.1109/RME.2007.4401852","url":null,"abstract":"This paper reviews two basic analog circuits that employ new capabilities brought about by independently driven double gate CMOS transistors (IDGMOS). The subject of the first review is a 1 V supply voltage follower that uses IDGMOS to increase the input range up to the supply voltage and to enhance the biasing circuit of the follower. The second looks at a new general method to make fully balanced differential amplifiers (FBAs) with compact common-mode feed back. IDGMOS FBAs perform complete transistor reuse without using any extra device to execute the feed-back amplifier functions, i.e. error evaluation and amplification. An application of this is illustrated with the simulation of a simple 1-stage differential amplifier with 38 dB gain and a 90.3 degree phase margin. The complete feed back loop includes the aforementioned voltage follower. The common-mode open loop gain is only about 21 dB but the common-mode reference voltage range, within 10% relative error, remains between 0.3 V and 0.9 V.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401801
M. Figueiredo, R. Aguiar
Jitter in CMOS technologies depend on several physical and design parameters, which are expected to change with scaling. Also, some parameters will have to change (by the introduction of enhancement techniques) in order to meet the desired performance goals for each new generation. The impact of each one of these parameters is here evaluated in order to give some insight on the jitter generation, amplification and coupling phenomena in actual and future designs. The work is based on AMS (0.8 um and 0.35 um) and UMC (180 nm and 130 nm) models for high performance, minimum sized transistors. Also, data from ITRS has been used to predict jitter dependency on the various parameters in deep-submicron CMOS generations.
{"title":"Predicting noise and jitter in CMOS inverters","authors":"M. Figueiredo, R. Aguiar","doi":"10.1109/RME.2007.4401801","DOIUrl":"https://doi.org/10.1109/RME.2007.4401801","url":null,"abstract":"Jitter in CMOS technologies depend on several physical and design parameters, which are expected to change with scaling. Also, some parameters will have to change (by the introduction of enhancement techniques) in order to meet the desired performance goals for each new generation. The impact of each one of these parameters is here evaluated in order to give some insight on the jitter generation, amplification and coupling phenomena in actual and future designs. The work is based on AMS (0.8 um and 0.35 um) and UMC (180 nm and 130 nm) models for high performance, minimum sized transistors. Also, data from ITRS has been used to predict jitter dependency on the various parameters in deep-submicron CMOS generations.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123765256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401849
T. Levi, N. Lewis, J. Tomas, P. Fouillat
This paper proposes scaling guidelines for CMOS analog design during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to obtain a decrease of area. The proposed guidelines are applied to linear examples: OTAs. The results are compared on four CMOS processes whose minimum length are 0.8 mum, 0.35 mum, 0.25 mum and 0.12 mum.
{"title":"Scaling guidelines for CMOS linear analog design","authors":"T. Levi, N. Lewis, J. Tomas, P. Fouillat","doi":"10.1109/RME.2007.4401849","DOIUrl":"https://doi.org/10.1109/RME.2007.4401849","url":null,"abstract":"This paper proposes scaling guidelines for CMOS analog design during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to obtain a decrease of area. The proposed guidelines are applied to linear examples: OTAs. The results are compared on four CMOS processes whose minimum length are 0.8 mum, 0.35 mum, 0.25 mum and 0.12 mum.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127993369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401825
M. Schipani, P. Bruschi, G. C. Tripoli, T. Ungaretti
A CMOS interface for three-axis capacitive accelerometers is presented. The circuit implements an innovative readout approach which allows to obtain a power consumption much lower than traditional schemes, thanks also to the reduced circuit complexity. A total power consumption of 175 muW at the nominal supply voltage 2.5 V is obtained for the entire interface.
{"title":"A low power CMOS interface circuit for three-axis integrated accelerometers","authors":"M. Schipani, P. Bruschi, G. C. Tripoli, T. Ungaretti","doi":"10.1109/RME.2007.4401825","DOIUrl":"https://doi.org/10.1109/RME.2007.4401825","url":null,"abstract":"A CMOS interface for three-axis capacitive accelerometers is presented. The circuit implements an innovative readout approach which allows to obtain a power consumption much lower than traditional schemes, thanks also to the reduced circuit complexity. A total power consumption of 175 muW at the nominal supply voltage 2.5 V is obtained for the entire interface.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115582467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401862
A. Bovy, P. Courmontagne, H. Chalopin
In certain cases, impacts linked to the transmission channel have to be precised. This is the case when it is question to study the contribution in terms of needs, consumption and size of the Channel Estimator in the Low cost and low power ASIC's Digital Signal Process working at equivalent frequency equal to 40 GHz. Thus, in this paper the path loss in the case of ground reflection is studied, according to the ECC and CEPT frequency and power limitations. It allows quantifying the path loss contribution, the Signal to Noise Ratio (SNR) degradation and particularly the Intersymbol Interference (ISI) between signal and echoes in the case of very high speed UWB transmission, only few nanoseconds average repetition interval, short range transmission (0-1 m) and short pulse power. Impacts of those echoes are discussed.
{"title":"A ground reflection theory of UWB transmission in the case of CEPT band limited spectrum","authors":"A. Bovy, P. Courmontagne, H. Chalopin","doi":"10.1109/RME.2007.4401862","DOIUrl":"https://doi.org/10.1109/RME.2007.4401862","url":null,"abstract":"In certain cases, impacts linked to the transmission channel have to be precised. This is the case when it is question to study the contribution in terms of needs, consumption and size of the Channel Estimator in the Low cost and low power ASIC's Digital Signal Process working at equivalent frequency equal to 40 GHz. Thus, in this paper the path loss in the case of ground reflection is studied, according to the ECC and CEPT frequency and power limitations. It allows quantifying the path loss contribution, the Signal to Noise Ratio (SNR) degradation and particularly the Intersymbol Interference (ISI) between signal and echoes in the case of very high speed UWB transmission, only few nanoseconds average repetition interval, short range transmission (0-1 m) and short pulse power. Impacts of those echoes are discussed.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116247870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401796
V. Sharma, U. Moon, G. Temes
Power consumption of pipelined ADCs is a strong function of the number of bits resolved per stage, particularly for high-performance ADCs. Despite this, conventional design techniques continue to use interstage gain levels of 2N which leave significant gaps in the design space, limiting the extent of optimization. This paper discusses a design method for arbitrary integer-valued interstage gain which retain all benefits of conventional schemes while optimizing power consumption. To demonstrate the practical benefits, a prototype 16-bit 20 Msps ADC with a target power consumption of 200 mW is designed using the proposed techniques.
{"title":"Efficient pipelined ADCs using integer gain MDACs","authors":"V. Sharma, U. Moon, G. Temes","doi":"10.1109/RME.2007.4401796","DOIUrl":"https://doi.org/10.1109/RME.2007.4401796","url":null,"abstract":"Power consumption of pipelined ADCs is a strong function of the number of bits resolved per stage, particularly for high-performance ADCs. Despite this, conventional design techniques continue to use interstage gain levels of 2N which leave significant gaps in the design space, limiting the extent of optimization. This paper discusses a design method for arbitrary integer-valued interstage gain which retain all benefits of conventional schemes while optimizing power consumption. To demonstrate the practical benefits, a prototype 16-bit 20 Msps ADC with a target power consumption of 200 mW is designed using the proposed techniques.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116447239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401865
Waseem Muhammad, S. Coudert, R. Ameur-Boulifa, R. Pacalet
SoC validation has become more challenging due to extensive reuse of intellectual property (IP) components in today's design. Simulation and formal validation techniques are suffering longer computation time, limited coverage and combinatorial explosion. To enhance both techniques, it is necessary to work at high abstraction level. In this perspective, the proposed methodology assists abstraction of IP components. We present in this paper a technique to separate control state machine from the data processing in register transfer level (RTL) IP models as first requirement for our notion of abstract data processing. A dependency analysis is performed on the given model based on the information of control and data inputs provided by the designer to obtain two separate entities in the form of control and data slice. The control slice and abstract functional representation of data slice are intended to be used for rapid simulation, static formal analysis and understanding the functionality of the model.
{"title":"Separating control and data processing in RT level virtual IP components","authors":"Waseem Muhammad, S. Coudert, R. Ameur-Boulifa, R. Pacalet","doi":"10.1109/RME.2007.4401865","DOIUrl":"https://doi.org/10.1109/RME.2007.4401865","url":null,"abstract":"SoC validation has become more challenging due to extensive reuse of intellectual property (IP) components in today's design. Simulation and formal validation techniques are suffering longer computation time, limited coverage and combinatorial explosion. To enhance both techniques, it is necessary to work at high abstraction level. In this perspective, the proposed methodology assists abstraction of IP components. We present in this paper a technique to separate control state machine from the data processing in register transfer level (RTL) IP models as first requirement for our notion of abstract data processing. A dependency analysis is performed on the given model based on the information of control and data inputs provided by the designer to obtain two separate entities in the form of control and data slice. The control slice and abstract functional representation of data slice are intended to be used for rapid simulation, static formal analysis and understanding the functionality of the model.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134646956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401855
F. Frustaci, P. Corsonello, G. Cocorullo
This work proposes a new noise-tolerant dynamic circuit design. It has been extensively compared to previously published schemes. The new design can achieve a level of noise robustness that is unreachable by the previous proposals. Furthermore, it has minimal delay and energy penalties. Under the same energy-delay product, the proposed design shows a noise-robustness that is increased by up to 116%, in comparison with the existing schemes.
{"title":"A new noise-tolerant dynamic logic circuit design","authors":"F. Frustaci, P. Corsonello, G. Cocorullo","doi":"10.1109/RME.2007.4401855","DOIUrl":"https://doi.org/10.1109/RME.2007.4401855","url":null,"abstract":"This work proposes a new noise-tolerant dynamic circuit design. It has been extensively compared to previously published schemes. The new design can achieve a level of noise robustness that is unreachable by the previous proposals. Furthermore, it has minimal delay and energy penalties. Under the same energy-delay product, the proposed design shows a noise-robustness that is increased by up to 116%, in comparison with the existing schemes.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127614454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401798
T. Caldwell, D. Johns
Incremental ADCs can operate at lower oversampling ratios than DeltaSigma modulators, resulting in higher input signal bandwidths. In this paper it is shown that time-interleaving can further increase the input signal bandwidth in incremental ADCs to the point that the oversampling ratio is equal to the time-interleaving factor, resulting in no decrease in the allowable input signal bandwidth due to oversampling. This paper investigates some of the advantages and challenges that time-interleaved incremental ADCs offer, and presents an example where a time-interleaved by 4 incremental ADC with an oversampling ratio of 4 can attain a resolution of 12 bits.
{"title":"Time-interleaved incremental data converters with low oversampling ratios","authors":"T. Caldwell, D. Johns","doi":"10.1109/RME.2007.4401798","DOIUrl":"https://doi.org/10.1109/RME.2007.4401798","url":null,"abstract":"Incremental ADCs can operate at lower oversampling ratios than DeltaSigma modulators, resulting in higher input signal bandwidths. In this paper it is shown that time-interleaving can further increase the input signal bandwidth in incremental ADCs to the point that the oversampling ratio is equal to the time-interleaving factor, resulting in no decrease in the allowable input signal bandwidth due to oversampling. This paper investigates some of the advantages and challenges that time-interleaved incremental ADCs offer, and presents an example where a time-interleaved by 4 incremental ADC with an oversampling ratio of 4 can attain a resolution of 12 bits.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114642046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-07-02DOI: 10.1109/RME.2007.4401844
F. Zito, D. Zito, D. Pepe
The building blocks of the transmitter for system-on-a-chip CMOS nano-power radar systems are presented. They consist of a novel fully integrated UWB pulse generator and a digitally programmable delay element. The pulse generator provides monocycle pulses with duration time close to 250 ps and 1-V peak-to-peak amplitude. In detail, the circuit provides a sinusoidal-like monocycle when activated by a negative edge of a trigger signal provided by a micro-controller. This activation can be delayed in the range 1-3 ns, by acting on a 5-bit programmable delay element, which provides a total set of 32 different delay times.
{"title":"UWB 3.1–10.6 GHz CMOS transmitter for system-on-a-chip nano-power pulse radars","authors":"F. Zito, D. Zito, D. Pepe","doi":"10.1109/RME.2007.4401844","DOIUrl":"https://doi.org/10.1109/RME.2007.4401844","url":null,"abstract":"The building blocks of the transmitter for system-on-a-chip CMOS nano-power radar systems are presented. They consist of a novel fully integrated UWB pulse generator and a digitally programmable delay element. The pulse generator provides monocycle pulses with duration time close to 250 ps and 1-V peak-to-peak amplitude. In detail, the circuit provides a sinusoidal-like monocycle when activated by a negative edge of a trigger signal provided by a micro-controller. This activation can be delayed in the range 1-3 ns, by acting on a 5-bit programmable delay element, which provides a total set of 32 different delay times.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124036877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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