Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313911
Jiawei Xu, P. Harpe, J. Pettine, C. Hoof, R. Yazicioglu
This paper presents a power-efficient ASIC for bio-impedance spectroscopy, as well as ECG and respiration recording. The ASIC includes a wideband stimulation current source with a pseudo-random binary sequence, a low-noise instrumentation amplifier, and a low power 12b SAR ADC. This ASIC is able to measure bio-impedances from 1Ω to 10kΩ with 0.1Ω resolution, and covers a frequency range up to 125kHz. Furthermore, the ASIC can simultaneously record ECG and respiration while consuming only 31μW from a 1.8V supply.
本文介绍了一种用于生物阻抗谱、心电和呼吸记录的低功耗ASIC。该ASIC包括一个带伪随机二进制序列的宽带激励电流源、一个低噪声仪表放大器和一个低功耗12b SAR ADC。该ASIC能够以0.1Ω分辨率测量从1Ω到10kΩ的生物阻抗，覆盖频率范围高达125kHz。此外，ASIC可以同时记录心电和呼吸，仅消耗31μW的1.8V电源。
{"title":"A low power configurable bio-impedance spectroscopy (BIS) ASIC with simultaneous ECG and respiration recording functionality","authors":"Jiawei Xu, P. Harpe, J. Pettine, C. Hoof, R. Yazicioglu","doi":"10.1109/ESSCIRC.2015.7313911","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313911","url":null,"abstract":"This paper presents a power-efficient ASIC for bio-impedance spectroscopy, as well as ECG and respiration recording. The ASIC includes a wideband stimulation current source with a pseudo-random binary sequence, a low-noise instrumentation amplifier, and a low power 12b SAR ADC. This ASIC is able to measure bio-impedances from 1Ω to 10kΩ with 0.1Ω resolution, and covers a frequency range up to 125kHz. Furthermore, the ASIC can simultaneously record ECG and respiration while consuming only 31μW from a 1.8V supply.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89339251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313874
T. Someya, H. Fuketa, K. Matsunaga, H. Morimura, T. Sakurai, M. Takamiya
A glitch-free programmable voltage detector is proposed for RF energy harvesting. In energy harvesting applications, ultra-low power (<; 1nW), PVT-variation tolerant, and glitch-free voltage detectors are required to turn on or off the output switch which connects an output capacitor of the energy harvester and the load circuits. The proposed multiple voltage duplicator (MVD) enables the ultra-low power (248pW at 1V) feature, detection voltage programmability (<; 49-mV step), and temperature-variation tolerant (0.11mV/°C in -20°C to 80°C) operation in 250-nm CMOS. In the conventional voltage detectors, when the input voltage is increased from 0V, a glitch of the output is observed, which mistakenly turns on the output switch and spoils the energy harvesting. To remove the glitch, the glitch-free programmable voltage detector is proposed.
{"title":"248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting","authors":"T. Someya, H. Fuketa, K. Matsunaga, H. Morimura, T. Sakurai, M. Takamiya","doi":"10.1109/ESSCIRC.2015.7313874","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313874","url":null,"abstract":"A glitch-free programmable voltage detector is proposed for RF energy harvesting. In energy harvesting applications, ultra-low power (<; 1nW), PVT-variation tolerant, and glitch-free voltage detectors are required to turn on or off the output switch which connects an output capacitor of the energy harvester and the load circuits. The proposed multiple voltage duplicator (MVD) enables the ultra-low power (248pW at 1V) feature, detection voltage programmability (<; 49-mV step), and temperature-variation tolerant (0.11mV/°C in -20°C to 80°C) operation in 250-nm CMOS. In the conventional voltage detectors, when the input voltage is increased from 0V, a glitch of the output is observed, which mistakenly turns on the output switch and spoils the energy harvesting. To remove the glitch, the glitch-free programmable voltage detector is proposed.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75685745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313857
B. V. Liempd, B. Hershberg, B. Debaillie, P. Wambacq, J. Craninckx
When using electrical-balance duplexers (EBDs) to provide RF self-interference cancellation for in-band full-duplex, in-band distortion produced by nonlinear CMOS switches in the duplexer cause distortion that limits the headroom for additional self-interference cancellation in subsequent cancellation schemes in the transceiver. A prototype EBD is fabricated in 0.18μm SOI CMOS to investigate the dynamic range limitations of a transceiver architecture for next-generation wireless systems that supports in-band full-duplex and legacy FDD. Measurements show -85dBm in-band distortion at +10dBm TX input power, enough for short-range links at 10MHz BW.
当使用电平衡双工器(ebd)为带内全双工提供射频自干扰消除时，双工器中非线性CMOS开关产生的带内失真会导致失真，从而限制了收发器后续抵消方案中额外自干扰消除的剩余空间。为了研究支持带内全双工和传统FDD的下一代无线系统的收发器架构的动态范围限制，在0.18μm SOI CMOS中制作了EBD原型。测量显示，在+10dBm的TX输入功率下，带内失真为-85dBm，足以用于10MHz BW的短距离链路。
{"title":"An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power","authors":"B. V. Liempd, B. Hershberg, B. Debaillie, P. Wambacq, J. Craninckx","doi":"10.1109/ESSCIRC.2015.7313857","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313857","url":null,"abstract":"When using electrical-balance duplexers (EBDs) to provide RF self-interference cancellation for in-band full-duplex, in-band distortion produced by nonlinear CMOS switches in the duplexer cause distortion that limits the headroom for additional self-interference cancellation in subsequent cancellation schemes in the transceiver. A prototype EBD is fabricated in 0.18μm SOI CMOS to investigate the dynamic range limitations of a transceiver architecture for next-generation wireless systems that supports in-band full-duplex and legacy FDD. Measurements show -85dBm in-band distortion at +10dBm TX input power, enough for short-range links at 10MHz BW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82717648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313839
S. Zeinolabedin, Jun Zhou, Xin Liu, T. T. Kim
This paper proposes a power and area efficient Laplacian Pyramid processing engine (LPPE) for multi-resolution image representation in image/video processing. In the proposed LPPE, a novel FIFO architecture with adaptive data compression is proposed to reduce the power and area consumption of LPPE. A new filtering extension method is also proposed to reduce the output errors. In circuit level, near-threshold design is adopted to further reduce the power consumption by supply voltage scaling. The proposed LPPE fabricated in a 0.18 μm CMOS process technology can process 112 frames per second at 3.68 MHz and 0.5 V while consuming only 452 μW.
{"title":"A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression","authors":"S. Zeinolabedin, Jun Zhou, Xin Liu, T. T. Kim","doi":"10.1109/ESSCIRC.2015.7313839","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313839","url":null,"abstract":"This paper proposes a power and area efficient Laplacian Pyramid processing engine (LPPE) for multi-resolution image representation in image/video processing. In the proposed LPPE, a novel FIFO architecture with adaptive data compression is proposed to reduce the power and area consumption of LPPE. A new filtering extension method is also proposed to reduce the output errors. In circuit level, near-threshold design is adopted to further reduce the power consumption by supply voltage scaling. The proposed LPPE fabricated in a 0.18 μm CMOS process technology can process 112 frames per second at 3.68 MHz and 0.5 V while consuming only 452 μW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75344648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313871
Abhik Das, Yuan Gao, T. T. Kim
With the emergence of thin-film thermo-electric generators (TEG), power density and sustainability of energy harvesting sources have improved. These novel power sources however exhibit high internal electrical resistances. Conventional state-of-the-art boost converters encounter low efficiency and potential startup failures when harvesting energy from such sources. This paper presents a highly efficient boost converter for thermo-electric energy harvesting systems based on a novel Power-on-Reset (PoR) driven startup circuit. It utilizes the feedback between TEG, the boost converter, and the PoR circuit, converting a reset signal edge into a train of pulses. The proposed startup circuit is automatically disabled once startup operation is completed, and consumes the quiescent power of 2nW in steady-state. The proposed boost converter has a self-startup TEG voltage of 220mV and a peak power conversion efficiency of 76% with a minimum input for operation being 85mV.
{"title":"A 76% efficiency boost converter with 220mV self-startup and 2nW quiescent power for high resistance thermo-electric energy harvesting","authors":"Abhik Das, Yuan Gao, T. T. Kim","doi":"10.1109/ESSCIRC.2015.7313871","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313871","url":null,"abstract":"With the emergence of thin-film thermo-electric generators (TEG), power density and sustainability of energy harvesting sources have improved. These novel power sources however exhibit high internal electrical resistances. Conventional state-of-the-art boost converters encounter low efficiency and potential startup failures when harvesting energy from such sources. This paper presents a highly efficient boost converter for thermo-electric energy harvesting systems based on a novel Power-on-Reset (PoR) driven startup circuit. It utilizes the feedback between TEG, the boost converter, and the PoR circuit, converting a reset signal edge into a train of pulses. The proposed startup circuit is automatically disabled once startup operation is completed, and consumes the quiescent power of 2nW in steady-state. The proposed boost converter has a self-startup TEG voltage of 220mV and a peak power conversion efficiency of 76% with a minimum input for operation being 85mV.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80584929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.
{"title":"120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs","authors":"Hsiang-An Yang, Chao-Chang Chiu, Shin-Chi Lai, Jui-Lung Chen, Chih-Wei Chang, Che-Hao Meng, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Hsin-Yu Luo","doi":"10.1109/ESSCIRC.2015.7313884","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313884","url":null,"abstract":"High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76255781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313856
Chuanwei Li, A. Liscidini
A current re-use PA-VCO cell for FSK transmitters is presented. High efficiency and low phase noise are obtained through the stacking of a PA and a class-C VCO. Without the use of any DC-DC converters, the voltage headroom of these two blocks can be set maximizing the efficiency of both the PA and the VCO. The structure is inserted in a 130nm CMOS BLE transmitter. A TX efficiency of 17.5% is achieved delivering an output power of -1dBm at 2.4GHz with a VCO phase noise of -129dBc/Hz @ 2.5MHz frequency offset.
{"title":"A current re-use PA-VCO cell for low-power BLE transmitters","authors":"Chuanwei Li, A. Liscidini","doi":"10.1109/ESSCIRC.2015.7313856","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313856","url":null,"abstract":"A current re-use PA-VCO cell for FSK transmitters is presented. High efficiency and low phase noise are obtained through the stacking of a PA and a class-C VCO. Without the use of any DC-DC converters, the voltage headroom of these two blocks can be set maximizing the efficiency of both the PA and the VCO. The structure is inserted in a 130nm CMOS BLE transmitter. A TX efficiency of 17.5% is achieved delivering an output power of -1dBm at 2.4GHz with a VCO phase noise of -129dBc/Hz @ 2.5MHz frequency offset.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77641226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313870
Jacob Göppert, Y. Manoli
This paper presents an inductive DC-DC boost converter for energy harvesting using a thermoelectric generator with a minimum start-up voltage of 70 mV and a regulated output voltage of 1.25 V. With a typical generator resistance of 40 Ω an output power of 17μW can be provided, which translates to an end-to-end efficiency of 58%. The converter employs Schmitt-Trigger logic start-up control circuitry and an ultra-low voltage charge pump using modified Schmitt-Trigger driving circuits optimized for driving capacitive loads. Together with a novel ultra-low leakage power switch and the required control scheme, this enables, to the authors knowledge, the lowest minimum voltage with fully integrated start-up.
{"title":"Fully integrated start-up at 70 mV of boost converters for thermoelectric energy harvesting","authors":"Jacob Göppert, Y. Manoli","doi":"10.1109/ESSCIRC.2015.7313870","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313870","url":null,"abstract":"This paper presents an inductive DC-DC boost converter for energy harvesting using a thermoelectric generator with a minimum start-up voltage of 70 mV and a regulated output voltage of 1.25 V. With a typical generator resistance of 40 Ω an output power of 17μW can be provided, which translates to an end-to-end efficiency of 58%. The converter employs Schmitt-Trigger logic start-up control circuitry and an ultra-low voltage charge pump using modified Schmitt-Trigger driving circuits optimized for driving capacitive loads. Together with a novel ultra-low leakage power switch and the required control scheme, this enables, to the authors knowledge, the lowest minimum voltage with fully integrated start-up.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81221023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313826
H. Uemura, Y. Kurita, H. Furuyama
In order to realize reliable OOB (Out-of-Band) transmission which is a major problem in optically connected SATA (Serial ATA) or SAS (Serial Attached SCSI), 12.5 Gb/s driver and receiver ICs with a newly-developed double threshold AGC were fabricated by TSMC 90 nm CMOS process. The double threshold AGC realized the rejection of small noise in a transmission line in an idle condition and the suppression of long decay in the end of a burst, and highly reliable optical OOB transmission was achieved. Optically connected SATA 6 Gb/s system operation was demonstrated for the first time in the world.
{"title":"12.5Gb/s optical driver and receiver ICs with double threshold AGC for SATA Out-of-Band transmission","authors":"H. Uemura, Y. Kurita, H. Furuyama","doi":"10.1109/ESSCIRC.2015.7313826","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313826","url":null,"abstract":"In order to realize reliable OOB (Out-of-Band) transmission which is a major problem in optically connected SATA (Serial ATA) or SAS (Serial Attached SCSI), 12.5 Gb/s driver and receiver ICs with a newly-developed double threshold AGC were fabricated by TSMC 90 nm CMOS process. The double threshold AGC realized the rejection of small noise in a transmission line in an idle condition and the suppression of long decay in the end of a burst, and highly reliable optical OOB transmission was achieved. Optically connected SATA 6 Gb/s system operation was demonstrated for the first time in the world.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85465718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313907
A. Narayanan, M. Katsuragi, K. Kimura, Satoshi Kondo, K. K. Tokgoz, K. Nakata, W. Deng, K. Okada, A. Matsuzawa
This paper presents a fractional-N PLL working in sub-sampling mode using a pipelined phase-interpolator. The proposed pipelined phase-interpolator can achieve high phase linearity with very low power consumption. The fractional-N sub-sampling PLL is implemented in a standard 65nm CMOS technology. The PLL works at a frequency ranging from 4.3GHz to 4.9GHz while consuming 3.3mW. The measured in-band phase noise in fractional-N mode is -114dBc/Hz at 400kHz offset from the carrier, while working with a bandwidth of approximately 2MHz. The combination of high-precision low-power phase-interpolation technique and the sub-sampling technique realizes a high-performance fractional-N frequency synthesizer with the highest reported FoM.
{"title":"A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB","authors":"A. Narayanan, M. Katsuragi, K. Kimura, Satoshi Kondo, K. K. Tokgoz, K. Nakata, W. Deng, K. Okada, A. Matsuzawa","doi":"10.1109/ESSCIRC.2015.7313907","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313907","url":null,"abstract":"This paper presents a fractional-N PLL working in sub-sampling mode using a pipelined phase-interpolator. The proposed pipelined phase-interpolator can achieve high phase linearity with very low power consumption. The fractional-N sub-sampling PLL is implemented in a standard 65nm CMOS technology. The PLL works at a frequency ranging from 4.3GHz to 4.9GHz while consuming 3.3mW. The measured in-band phase noise in fractional-N mode is -114dBc/Hz at 400kHz offset from the carrier, while working with a bandwidth of approximately 2MHz. The combination of high-precision low-power phase-interpolation technique and the sub-sampling technique realizes a high-performance fractional-N frequency synthesizer with the highest reported FoM.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91449916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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