Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313896
Mihail Jefremow, D. Schmitt-Landsiedel, T. Kern, M. Stiftinger, Christoph Roll
This paper proposes two new design techniques, the slope sense amplifier (S-SA) circuit combined with in situ current monitoring (ISCM) implemented in a 40nm embedded FLASH technology. S-SA reduces the sense delay time below 4.5ns thereby enabling a sub 10ns read access time operation for an 8Mbit memory sector. It also provides a power reduction of more than 40% and reduces the occupied area of the sensing circuits by 50%. The S-SA enables a reduced signal development time on the BL increases the read window by 50%. In addition the ISCM improves the write performance by a factor of at least 1.6.
{"title":"Slope only sense amplifier with 4.5ns sense delay for 8Mbit memory sector, employing in situ current monitoring with 66% write speed improvement in 40nm embedded flash for automotive","authors":"Mihail Jefremow, D. Schmitt-Landsiedel, T. Kern, M. Stiftinger, Christoph Roll","doi":"10.1109/ESSCIRC.2015.7313896","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313896","url":null,"abstract":"This paper proposes two new design techniques, the slope sense amplifier (S-SA) circuit combined with in situ current monitoring (ISCM) implemented in a 40nm embedded FLASH technology. S-SA reduces the sense delay time below 4.5ns thereby enabling a sub 10ns read access time operation for an 8Mbit memory sector. It also provides a power reduction of more than 40% and reduces the occupied area of the sensing circuits by 50%. The S-SA enables a reduced signal development time on the BL increases the read window by 50%. In addition the ISCM improves the write performance by a factor of at least 1.6.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84708452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313886
Anders Nejdel, Xiaodong Liu, Mattias Palm, Lars Sundström, Markus Törmänen, H. Sjöland, P. Andreani
We present a wideband quadrature radio receiver employing ΔΣ-based A/D-converting channel-select filters (AD-CSFs). The output of the quadrature passive mixer is directly connected to the input of the ADCSFs, which incorporate the functionalities of both channel selection and data conversion in a single power-optimized block. The 65nm CMOS receiver has a frequency range of 0.6-3.0 GHz and can be programmed to support the 2xLTE20, LTE20, and LTE10 bandwidths. The receiver noise figure varies from 2.4 to 3.5 dB. In 2xLTE20 mode, the current consumption is between 33mA at 0.6 GHz and 44mA at 3.0 GHz, including 10-21mA for LO generation and distribution, supplied from 1.2 V. The SNDR is 47-51dB at an LO frequency of 1.8 GHz.
{"title":"A 0.6–3.0GHz 65nm CMOS radio receiver with ΔΣ-based A/D-converting channel-select filters","authors":"Anders Nejdel, Xiaodong Liu, Mattias Palm, Lars Sundström, Markus Törmänen, H. Sjöland, P. Andreani","doi":"10.1109/ESSCIRC.2015.7313886","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313886","url":null,"abstract":"We present a wideband quadrature radio receiver employing ΔΣ-based A/D-converting channel-select filters (AD-CSFs). The output of the quadrature passive mixer is directly connected to the input of the ADCSFs, which incorporate the functionalities of both channel selection and data conversion in a single power-optimized block. The 65nm CMOS receiver has a frequency range of 0.6-3.0 GHz and can be programmed to support the 2xLTE20, LTE20, and LTE10 bandwidths. The receiver noise figure varies from 2.4 to 3.5 dB. In 2xLTE20 mode, the current consumption is between 33mA at 0.6 GHz and 44mA at 3.0 GHz, including 10-21mA for LO generation and distribution, supplied from 1.2 V. The SNDR is 47-51dB at an LO frequency of 1.8 GHz.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84450817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313861
A. Vasilica, V. Anghel, G. Pristavu, G. Brezeanu
This paper proposes an adaptive soft-start technique which offers both dynamic overshoot protection at start-up and maximum current regulation during steady state. The circuit is included in a boost converter IC Controller manufactured in a 50V, 0.5μm CMOS technology and tested via simulations and measurements. A comparative study is performed regarding converter's operation with and without the proposed block. Results emphasize the proposed solution's ability to suppress overshoots and reduce start-up time. Moreover, the measured start-up time is quasi-constant for a fixed number of LEDs, regardless of LED current.
{"title":"Suppressing start-up time variation versus load current — Adaptive soft-start in boost LED drivers","authors":"A. Vasilica, V. Anghel, G. Pristavu, G. Brezeanu","doi":"10.1109/ESSCIRC.2015.7313861","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313861","url":null,"abstract":"This paper proposes an adaptive soft-start technique which offers both dynamic overshoot protection at start-up and maximum current regulation during steady state. The circuit is included in a boost converter IC Controller manufactured in a 50V, 0.5μm CMOS technology and tested via simulations and measurements. A comparative study is performed regarding converter's operation with and without the proposed block. Results emphasize the proposed solution's ability to suppress overshoots and reduce start-up time. Moreover, the measured start-up time is quasi-constant for a fixed number of LEDs, regardless of LED current.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82647716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313855
A. Banerjee, Lei Ding, R. Hezar
A high efficiency multi-mode class-E outphasing RF power amplifier with a passive combining circuit is presented. The multi-mode PA improves efficiency at lower power levels by switching ON and OFF individual branches and using Efficiency Enhancement Circuit (EEC). The proposed power amplifier is designed in 45nm CMOS technology. The PA delivers 31.6 dBm peak output power at 2.4GHz with 49.2% drain efficiency in high power single level mode. For 64-QAM LTE signal with 10MHz and 20MHz bandwidth, -57 dBc and -53 dBc ACPR are obtained in single level outphasing mode with DPD. 25% and 33% average drain efficiency are obtained with LTE signal with 6 dB peak-to-average power ratio (PAPR) in single level outphasing and AMO mode respectively.
{"title":"High efficiency multi-mode outphasing RF power amplifier in 45nm CMOS","authors":"A. Banerjee, Lei Ding, R. Hezar","doi":"10.1109/ESSCIRC.2015.7313855","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313855","url":null,"abstract":"A high efficiency multi-mode class-E outphasing RF power amplifier with a passive combining circuit is presented. The multi-mode PA improves efficiency at lower power levels by switching ON and OFF individual branches and using Efficiency Enhancement Circuit (EEC). The proposed power amplifier is designed in 45nm CMOS technology. The PA delivers 31.6 dBm peak output power at 2.4GHz with 49.2% drain efficiency in high power single level mode. For 64-QAM LTE signal with 10MHz and 20MHz bandwidth, -57 dBc and -53 dBc ACPR are obtained in single level outphasing mode with DPD. 25% and 33% average drain efficiency are obtained with LTE signal with 6 dB peak-to-average power ratio (PAPR) in single level outphasing and AMO mode respectively.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79051821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313835
Shailesh Kulkarni, Ibrahim Kazi, David Seebacher, P. Singerl, F. Dielacher, W. Dehaene, P. Reynaert
A fully digital 0.9GHz-2.6GHz multimode modulator based on the principle of RF-PWM is presented. It makes use of a delay-line based phase modulator which delays an incoming LO-signal with a resolution of 4ps. The modulator is designed to drive highly efficient switching power amplifiers and support carrier frequencies over a wide range. The modulator has been implemented in 40nm CMOS technology. It achieves an EVM of better than -29dB for a 802.11g 64-QAM OFDM signal. It has also been tested with 40MHz single carrier 64-QAM modulated signals. The measured ACPR is below -30dB up to 2GHz and possible improvements are demonstrated.
{"title":"Multi-standard wideband OFDM RF-PWM transmitter in 40nm CMOS","authors":"Shailesh Kulkarni, Ibrahim Kazi, David Seebacher, P. Singerl, F. Dielacher, W. Dehaene, P. Reynaert","doi":"10.1109/ESSCIRC.2015.7313835","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313835","url":null,"abstract":"A fully digital 0.9GHz-2.6GHz multimode modulator based on the principle of RF-PWM is presented. It makes use of a delay-line based phase modulator which delays an incoming LO-signal with a resolution of 4ps. The modulator is designed to drive highly efficient switching power amplifiers and support carrier frequencies over a wide range. The modulator has been implemented in 40nm CMOS technology. It achieves an EVM of better than -29dB for a 802.11g 64-QAM OFDM signal. It has also been tested with 40MHz single carrier 64-QAM modulated signals. The measured ACPR is below -30dB up to 2GHz and possible improvements are demonstrated.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81839614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313889
T. Rabuske, J. Fernandes
The linearity of the vast majority of the ADC topologies is limited by the linearity of the employed circuit elements, e.g. resistors and capacitors. This paper presents a 9-b charge-mode SAR ADC that uses only very nonlinear MOSCAPs as the DAC capacitance elements and still presents 67 dB of SFDR. The track-and-hold exploits the routing parasitics as the sampling capacitance, entirely obviating MOM capacitors in the design. The circuit employs local voltage boosting and a new boost-and-bootstrap switch in order to allow operation under 0.4 V of supply voltage. Still, the ADC topology achieves a differential input swing of 1.6 Vpp, which is four times the supply voltage. The 0.13-μm CMOS prototype achieves an ENOB of 8.01 at 300 kSps while consuming 354 nW. The corresponding FoM is 4.57 fJ/conversion-step.
{"title":"A 9-b 0.4-V charge-mode SAR ADC with 1.6-V input swing and a MOSCAP-only DAC","authors":"T. Rabuske, J. Fernandes","doi":"10.1109/ESSCIRC.2015.7313889","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313889","url":null,"abstract":"The linearity of the vast majority of the ADC topologies is limited by the linearity of the employed circuit elements, e.g. resistors and capacitors. This paper presents a 9-b charge-mode SAR ADC that uses only very nonlinear MOSCAPs as the DAC capacitance elements and still presents 67 dB of SFDR. The track-and-hold exploits the routing parasitics as the sampling capacitance, entirely obviating MOM capacitors in the design. The circuit employs local voltage boosting and a new boost-and-bootstrap switch in order to allow operation under 0.4 V of supply voltage. Still, the ADC topology achieves a differential input swing of 1.6 Vpp, which is four times the supply voltage. The 0.13-μm CMOS prototype achieves an ENOB of 8.01 at 300 kSps while consuming 354 nW. The corresponding FoM is 4.57 fJ/conversion-step.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75649041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313843
J. González, V. Puyal, A. Siligaris, C. Jany, C. Dehos
This work presents a mmW frequency selector as the core of the LO generator for E-band transceivers. Two 10 GHz apart mmW LO frequencies generated by a mixer from a single 50 GHz frequency and its 5 GHz submultiple are sent to the proposed circuit that outputs a single frequency tone of either 45 GHz or 55 GHz. The circuit is realized in BiCMOS 55nm technology combining 55nm CMOS transistors and SiGe HBTs with fT and fmax ~300 GHz. The circuit is based on injection-locked oscillators, presents a phase noise @ 1MHz offset of -110 dBc/Hz with 0 dB of excess phase noise added to the input, and consumes 53mW.
{"title":"A 45GHz/55GHz LO frequency selector for E-band transceivers based on switchable injection locked-oscillators in BiCMOS 55nm","authors":"J. González, V. Puyal, A. Siligaris, C. Jany, C. Dehos","doi":"10.1109/ESSCIRC.2015.7313843","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313843","url":null,"abstract":"This work presents a mmW frequency selector as the core of the LO generator for E-band transceivers. Two 10 GHz apart mmW LO frequencies generated by a mixer from a single 50 GHz frequency and its 5 GHz submultiple are sent to the proposed circuit that outputs a single frequency tone of either 45 GHz or 55 GHz. The circuit is realized in BiCMOS 55nm technology combining 55nm CMOS transistors and SiGe HBTs with fT and fmax ~300 GHz. The circuit is based on injection-locked oscillators, presents a phase noise @ 1MHz offset of -110 dBc/Hz with 0 dB of excess phase noise added to the input, and consumes 53mW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75899564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313829
D. Pepe, D. Zito
A 78.8-92.8 GHz 4-bit (16 phases) digitally controlled vector modulator active phase shifter has been designed and implemented in 28nm FDSOI CMOS by STMicroelectronics. The phase shifter exploits a novel IQ generator based on a cascode amplifier incorporating a lumped element coupled line quadrature coupler to generate the in-phase (I) and quadrature (Q) signals. The phase shifter consumes 18 mA from a 1.2 V supply. The measured performances are: average gain of 2.3 dB at 87.4 GHz (between 3.2 and -1.6 dB for the 16 phase states) and -3 dB bandwidth (B3dB) from 78.8 to 92.8 GHz; RMS gain error equal to 1.68 dB at 87.4 GHz and lower than 2 dB in the B3dB; RMS phase error equal to 9.4o at 87.4 GHz and lower than 11.9o in the B3dB; S11 lower than -10.5 dB in the B3dB; average input referred 1 dB compression point of -7 dBm (between -8 and -5 dBm for the 16 phase states); average noise figure equal to 10.8 dB at 87 GHz (between -9 and -12 dB for the 16 phase states).
{"title":"A 78.8–92.8 GHz 4-bit 0–360° active phase shifter in 28nm FDSOI CMOS with 2.3 dB average peak gain","authors":"D. Pepe, D. Zito","doi":"10.1109/ESSCIRC.2015.7313829","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313829","url":null,"abstract":"A 78.8-92.8 GHz 4-bit (16 phases) digitally controlled vector modulator active phase shifter has been designed and implemented in 28nm FDSOI CMOS by STMicroelectronics. The phase shifter exploits a novel IQ generator based on a cascode amplifier incorporating a lumped element coupled line quadrature coupler to generate the in-phase (I) and quadrature (Q) signals. The phase shifter consumes 18 mA from a 1.2 V supply. The measured performances are: average gain of 2.3 dB at 87.4 GHz (between 3.2 and -1.6 dB for the 16 phase states) and -3 dB bandwidth (B3dB) from 78.8 to 92.8 GHz; RMS gain error equal to 1.68 dB at 87.4 GHz and lower than 2 dB in the B3dB; RMS phase error equal to 9.4o at 87.4 GHz and lower than 11.9o in the B3dB; S11 lower than -10.5 dB in the B3dB; average input referred 1 dB compression point of -7 dBm (between -8 and -5 dBm for the 16 phase states); average noise figure equal to 10.8 dB at 87 GHz (between -9 and -12 dB for the 16 phase states).","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74796908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313831
S. Shopov, S. Voinigescu
A versatile three-lane transceiver front-end is integrated in a production 28nm FDSOI CMOS technology. Each lane can operate at up to 40Gb/s data rate in receive mode with record 10mVPP sensitivity and 40dB gain, or up to 60Gb/s data rate in transmit mode with adjustable output swing between 2.6 and 4.3 VPP in a 50Ω load, as needed for a variety of silicon photonics and III-V optical modulators. The output stage can swing up to 100 mA at 60 Gb/s in 50Ω or 100fF capacitive loads. Single-ended CMOS inverter-based topologies are employed in all circuit blocks to minimize power consumption and to reduce the lane footprint to that of a ground-signal pad I/O. Even with the reduced footprint, special layout techniques enabled a lane-to-lane isolation better than 40 dB up to 55 GHz. The measured Tx-to-Rx dynamic range is larger than 54 dB at 40 Gb/s.
{"title":"A 3×40Gb/s 28nm FDSOI CMOS front-end array with 10mVPP sensitivity and >4VPP output swing","authors":"S. Shopov, S. Voinigescu","doi":"10.1109/ESSCIRC.2015.7313831","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313831","url":null,"abstract":"A versatile three-lane transceiver front-end is integrated in a production 28nm FDSOI CMOS technology. Each lane can operate at up to 40Gb/s data rate in receive mode with record 10mVPP sensitivity and 40dB gain, or up to 60Gb/s data rate in transmit mode with adjustable output swing between 2.6 and 4.3 VPP in a 50Ω load, as needed for a variety of silicon photonics and III-V optical modulators. The output stage can swing up to 100 mA at 60 Gb/s in 50Ω or 100fF capacitive loads. Single-ended CMOS inverter-based topologies are employed in all circuit blocks to minimize power consumption and to reduce the lane footprint to that of a ground-signal pad I/O. Even with the reduced footprint, special layout techniques enabled a lane-to-lane isolation better than 40 dB up to 55 GHz. The measured Tx-to-Rx dynamic range is larger than 54 dB at 40 Gb/s.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76626712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313820
M. Steyaert, F. Tavernier, H. Meyvaert, Athanasios Sarafianos, N. Butzen
In the last several years, significant efforts and advances have been made towards the CMOS integration of power converters. In this paper, an overview is given of what might be considered the next step in this domain: AC-DC conversion, efficient high-ratio voltage conversion, wide operating range and energy storage for energy scavenging. The main focus is on CMOS integration as this is the ultimate goal from any system integration point of view. Also, an overview of the state of the art will be discussed.
{"title":"When hardware is free, power is expensive! Is integrated power management the solution?","authors":"M. Steyaert, F. Tavernier, H. Meyvaert, Athanasios Sarafianos, N. Butzen","doi":"10.1109/ESSCIRC.2015.7313820","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313820","url":null,"abstract":"In the last several years, significant efforts and advances have been made towards the CMOS integration of power converters. In this paper, an overview is given of what might be considered the next step in this domain: AC-DC conversion, efficient high-ratio voltage conversion, wide operating range and energy storage for energy scavenging. The main focus is on CMOS integration as this is the ultimate goal from any system integration point of view. Also, an overview of the state of the art will be discussed.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89217808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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