Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313851
Yipeng Wang, Duona Luo, Quan Pan, Liwen Jing, Zhixin Li, C. Yue
This paper presents, for the first time, an optical-to-mm-wave modulator SoC with an integrated 850-nm wavelength optical receiver front-end for short-range backhaul connectivity in emerging fiber-wireless mobile networks. Realized in 65-nm CMOS, the optical front-end achieves -3dBm optical input sensitivity at 4Gb/s with 10-12 BER. The modulator directly up-converts the de-multiplexed 2Gb/s I/Q NRZ data to a 4Gb/s QPSK signal at 60GHz. The SoC consumes 78mW and produces -7.2dBm output power with -12dB EVM at a bit efficiency of 19.6pJ/b.
{"title":"A 60GHz 4Gb/s fully integrated NRZ-to-QPSK modulator SoC for backhaul links in fiber-wireless networks","authors":"Yipeng Wang, Duona Luo, Quan Pan, Liwen Jing, Zhixin Li, C. Yue","doi":"10.1109/ESSCIRC.2015.7313851","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313851","url":null,"abstract":"This paper presents, for the first time, an optical-to-mm-wave modulator SoC with an integrated 850-nm wavelength optical receiver front-end for short-range backhaul connectivity in emerging fiber-wireless mobile networks. Realized in 65-nm CMOS, the optical front-end achieves -3dBm optical input sensitivity at 4Gb/s with 10-12 BER. The modulator directly up-converts the de-multiplexed 2Gb/s I/Q NRZ data to a 4Gb/s QPSK signal at 60GHz. The SoC consumes 78mW and produces -7.2dBm output power with -12dB EVM at a bit efficiency of 19.6pJ/b.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74117311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313854
B. V. Liempd, Saneaki Ariumi, E. Martens, Shih-Hung Chen, P. Wambacq, J. Craninckx
IM3-cancellation is a popular technique in LNAs to achieve very high linearity, but is also very sensitive to the exact device (bias) operating point. A 0.7-1.15GHz complementary common-gate LNA in 0.18μm silicon-on-insulator CMOS is presented that achieves good out-of-band (OOB) linearity without IM3-cancellation. Measurements of the 0.9mm2 prototype show a gain of >7dB, an NF of <;2.3dB, more than +15dBm OOB-IIP3 and over 0dBm B1dB. Compared to other work, this LNA has a similar or better linearity at only 10mW. The LNA uses a nominal supply of 2.5V, but was tested up to 3.7V and showed no significant degradation of its linearity for ±400mV supply variations. A power clamp, designed to enable testing at higher core supply voltage, withstands a >2.6kV HBM discharge, while the overall circuit is protected for >1kV HBM discharges.
{"title":"A 0.7–1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection","authors":"B. V. Liempd, Saneaki Ariumi, E. Martens, Shih-Hung Chen, P. Wambacq, J. Craninckx","doi":"10.1109/ESSCIRC.2015.7313854","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313854","url":null,"abstract":"IM3-cancellation is a popular technique in LNAs to achieve very high linearity, but is also very sensitive to the exact device (bias) operating point. A 0.7-1.15GHz complementary common-gate LNA in 0.18μm silicon-on-insulator CMOS is presented that achieves good out-of-band (OOB) linearity without IM3-cancellation. Measurements of the 0.9mm2 prototype show a gain of >7dB, an NF of <;2.3dB, more than +15dBm OOB-IIP3 and over 0dBm B1dB. Compared to other work, this LNA has a similar or better linearity at only 10mW. The LNA uses a nominal supply of 2.5V, but was tested up to 3.7V and showed no significant degradation of its linearity for ±400mV supply variations. A power clamp, designed to enable testing at higher core supply voltage, withstands a >2.6kV HBM discharge, while the overall circuit is protected for >1kV HBM discharges.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74165245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313841
M. Igarashi, K. Takeuchi, T. Okagaki, K. Shibutani, Hiroaki Matsushita, K. Nii
We propose an on-die aging monitor based on ring-oscillator (RO) which measures bias-temperature-instabilities (BTI) and AC hot-carrier-infection (HCI). The monitor consists of a symmetric RO (SRO) and an asymmetric RO (ASRO). The effect of NBTI and PBTI can be separated by focusing on the difference in sensitivity observed in SRO and ASRO under DC stress condition. In addition, the speed degradation caused by AC-HCI is monitored because unbalanced delay with long/short transition in ASRO has high sensitivity against AC-HCI under AC stress. A test chip including both SRO and ASRO using 2NAND standard cells is implemented in a 16 nm Fin-FET bulk CMOS technology. We observe that Vth shift due to PBTI measured from frequency degradation is 2 mV, which is still 1/10 of NBTI in Fin-FET technology. The measured AC-HCI shows almost half percentage of all aging factors. The aging monitor optimizes the design guard band (GB) in design phase and enables dependable system in high performance application LSIs.
{"title":"An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology","authors":"M. Igarashi, K. Takeuchi, T. Okagaki, K. Shibutani, Hiroaki Matsushita, K. Nii","doi":"10.1109/ESSCIRC.2015.7313841","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313841","url":null,"abstract":"We propose an on-die aging monitor based on ring-oscillator (RO) which measures bias-temperature-instabilities (BTI) and AC hot-carrier-infection (HCI). The monitor consists of a symmetric RO (SRO) and an asymmetric RO (ASRO). The effect of NBTI and PBTI can be separated by focusing on the difference in sensitivity observed in SRO and ASRO under DC stress condition. In addition, the speed degradation caused by AC-HCI is monitored because unbalanced delay with long/short transition in ASRO has high sensitivity against AC-HCI under AC stress. A test chip including both SRO and ASRO using 2NAND standard cells is implemented in a 16 nm Fin-FET bulk CMOS technology. We observe that Vth shift due to PBTI measured from frequency degradation is 2 mV, which is still 1/10 of NBTI in Fin-FET technology. The measured AC-HCI shows almost half percentage of all aging factors. The aging monitor optimizes the design guard band (GB) in design phase and enables dependable system in high performance application LSIs.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81019182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313847
Shunli Ma, Guangyao Zhou, Jia-Feng Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren
This paper presents an accurate quadrature clock signals with phase calibration for ultra-high speed real-time sampling system. The proposed four-phase clock generator is a phase locked loop (PLL) with a novel quadrature divider which can realize tunable quadrature phase to calibrate variable mismatches. The operating frequency of the proposed quadrature clock can be tuned from 5.5GHz to 7.85GHz which can be used in four-channel time-interleaved sampler. The real-time sampling system achieve 28-31.2GS/s sampling rate. The chip consumes 28mW power with 1.2V supply voltage in TSMC 65 nm CMOS process. The measurements show that the calibration phase can cover ±10°I phase and Q phase mismatch. The phase noise is -115 dBc/Hz@1MHz offset frequency at 6.85GHz center frequency and cycle-to-cycle time RMS jitter is 210fs.
{"title":"A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system","authors":"Shunli Ma, Guangyao Zhou, Jia-Feng Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren","doi":"10.1109/ESSCIRC.2015.7313847","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313847","url":null,"abstract":"This paper presents an accurate quadrature clock signals with phase calibration for ultra-high speed real-time sampling system. The proposed four-phase clock generator is a phase locked loop (PLL) with a novel quadrature divider which can realize tunable quadrature phase to calibrate variable mismatches. The operating frequency of the proposed quadrature clock can be tuned from 5.5GHz to 7.85GHz which can be used in four-channel time-interleaved sampler. The real-time sampling system achieve 28-31.2GS/s sampling rate. The chip consumes 28mW power with 1.2V supply voltage in TSMC 65 nm CMOS process. The measurements show that the calibration phase can cover ±10°I phase and Q phase mismatch. The phase noise is -115 dBc/Hz@1MHz offset frequency at 6.85GHz center frequency and cycle-to-cycle time RMS jitter is 210fs.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81180190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313833
Badr Malki, B. Verbruggen, E. Martens, P. Wambacq, J. Craninckx
A Discrete-Time (DT) analog baseband for Software-Defined-Radio (SDR) receivers is presented. A zero-IF baseband signal at the input of a programmable gm is converted to current, which is integrated on a 5th order DT IIR filter with a bandwidth ranging from 150 kHz to 80 MHz. The IIR is followed by a DT amplifier which integrates freely selectable samples to implement active FIR filtering while simultaneously offering variable-gain amplification. This integration happens on the DAC capacitance of a 2x interleaved 10b ADC, which finally quantizes the filtered signal at a maximum rate of 300 MS/s. The 28 nm prototype achieves +10 dBm IIP3, 2 nV/VHz IRN and 52 dB gain range while consuming a maximum power of 15 mW.
{"title":"A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS","authors":"Badr Malki, B. Verbruggen, E. Martens, P. Wambacq, J. Craninckx","doi":"10.1109/ESSCIRC.2015.7313833","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313833","url":null,"abstract":"A Discrete-Time (DT) analog baseband for Software-Defined-Radio (SDR) receivers is presented. A zero-IF baseband signal at the input of a programmable gm is converted to current, which is integrated on a 5th order DT IIR filter with a bandwidth ranging from 150 kHz to 80 MHz. The IIR is followed by a DT amplifier which integrates freely selectable samples to implement active FIR filtering while simultaneously offering variable-gain amplification. This integration happens on the DAC capacitance of a 2x interleaved 10b ADC, which finally quantizes the filtered signal at a maximum rate of 300 MS/s. The 28 nm prototype achieves +10 dBm IIP3, 2 nV/VHz IRN and 52 dB gain range while consuming a maximum power of 15 mW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79056595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313888
A. Siligaris, Y. Andee, E. Mercier, Jose Moron Guerra, J. Lampin, G. Ducournau, Y. Quéré
A low power 278-GHz CMOS zero-IF heterodyne receiver is presented in this paper. The circuit includes a passive mixer, a baseband amplifier, a 278-GHz triple push sub-harmonic injection locked oscillator and an integrated antenna. The receiver measured maximum conversion gain is -12 dB and the DC power consumption is 47 mW. The on-chip antenna size is 390×280 μm2. The heterodyne receiver is used as a THz detector for imaging. It is shown that thanks to the heterodyne structure and the oscillator locking the THz image quality and contrast increases significantly. The imaging system achieves a noise equivalent power (NEP) of 0.2 fW/Hz.
{"title":"A 278 GHz heterodyne receiver with on-chip antenna for THz imaging in 65 nm CMOS process","authors":"A. Siligaris, Y. Andee, E. Mercier, Jose Moron Guerra, J. Lampin, G. Ducournau, Y. Quéré","doi":"10.1109/ESSCIRC.2015.7313888","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313888","url":null,"abstract":"A low power 278-GHz CMOS zero-IF heterodyne receiver is presented in this paper. The circuit includes a passive mixer, a baseband amplifier, a 278-GHz triple push sub-harmonic injection locked oscillator and an integrated antenna. The receiver measured maximum conversion gain is -12 dB and the DC power consumption is 47 mW. The on-chip antenna size is 390×280 μm2. The heterodyne receiver is used as a THz detector for imaging. It is shown that thanks to the heterodyne structure and the oscillator locking the THz image quality and contrast increases significantly. The imaging system achieves a noise equivalent power (NEP) of 0.2 fW/Hz.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81983303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313869
Masaki Yonekura, H. Ishikuro
This paper presents a new technique to suppress I/Q mismatch and decrease power consumption and chip area. The proposed technique uses two methods for all integrators and DAC in the modulator which are main sources of the mismatch and power. One is proposed ternary capacitor rotation technique to compensate the I/Q mismatch and achieve high image-rejection. The other is amplifier-sharing technique to reduce the number of amplifier and power consumption. The third-order 1bit delta-sigma modulator was designed in 65nm CMOS process, and fabricated test chip achieved an image-rejection ratio (IRR) of higher than 70dB throughout a 1MHz bandwidth. The overall power consumption is 12.7mW including I/Q channels.
{"title":"I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique","authors":"Masaki Yonekura, H. Ishikuro","doi":"10.1109/ESSCIRC.2015.7313869","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313869","url":null,"abstract":"This paper presents a new technique to suppress I/Q mismatch and decrease power consumption and chip area. The proposed technique uses two methods for all integrators and DAC in the modulator which are main sources of the mismatch and power. One is proposed ternary capacitor rotation technique to compensate the I/Q mismatch and achieve high image-rejection. The other is amplifier-sharing technique to reduce the number of amplifier and power consumption. The third-order 1bit delta-sigma modulator was designed in 65nm CMOS process, and fabricated test chip achieved an image-rejection ratio (IRR) of higher than 70dB throughout a 1MHz bandwidth. The overall power consumption is 12.7mW including I/Q channels.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86368555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313862
J. Duarte, S. Khandelwal, A. Medury, C. Hu, P. Kushwaha, H. Agarwal, A. Dasgupta, Y. Chauhan
This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG model's capabilities for circuit design using FinFET transistors for advanced technology nodes.
{"title":"BSIM-CMG: Standard FinFET compact model for advanced circuit design","authors":"J. Duarte, S. Khandelwal, A. Medury, C. Hu, P. Kushwaha, H. Agarwal, A. Dasgupta, Y. Chauhan","doi":"10.1109/ESSCIRC.2015.7313862","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313862","url":null,"abstract":"This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG model's capabilities for circuit design using FinFET transistors for advanced technology nodes.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90484528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313852
K. Settaluri, Sen Lin, S. Moazeni, E. Timurdogan, Chen Sun, M. Moresco, Z. Su, Yu-hsin Chen, G. Leake, D. LaTulipe, C. McDonough, J. Hebding, D. Coolbaugh, M. Watts, V. Stojanović
A full optical chip-to-chip link is demonstrated for the first time in a wafer-scale heterogeneous platform, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs). This development platform yields 1000s of functional photonic components as well as 16M transistors per chip module. The transmitter operates at 6Gb/s with an energy cost of 100fJ/bit and the receiver at 7Gb/s with a sensitivity of 26μA (-14.5dBm) and 340fJ/bit energy consumption. A full 5Gb/s chip-to-chip link, with the on-chip calibration and self-test, is demonstrated over a 100m single mode optical fiber with 560fJ/bit of electrical and 4.2pJ/bit of optical energy.
{"title":"Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform","authors":"K. Settaluri, Sen Lin, S. Moazeni, E. Timurdogan, Chen Sun, M. Moresco, Z. Su, Yu-hsin Chen, G. Leake, D. LaTulipe, C. McDonough, J. Hebding, D. Coolbaugh, M. Watts, V. Stojanović","doi":"10.1109/ESSCIRC.2015.7313852","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313852","url":null,"abstract":"A full optical chip-to-chip link is demonstrated for the first time in a wafer-scale heterogeneous platform, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs). This development platform yields 1000s of functional photonic components as well as 16M transistors per chip module. The transmitter operates at 6Gb/s with an energy cost of 100fJ/bit and the receiver at 7Gb/s with a sensitivity of 26μA (-14.5dBm) and 340fJ/bit energy consumption. A full 5Gb/s chip-to-chip link, with the on-chip calibration and self-test, is demonstrated over a 100m single mode optical fiber with 560fJ/bit of electrical and 4.2pJ/bit of optical energy.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90645207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313866
Amrith Sukumaran, S. Pavan
DACs based on switched-capacitor feedback are used in CTΔΣMs to achieve low jitter sensitivity. Unfortunately, they all severely compromise the alias rejection of the modulator around multiples of the sampling frequency. We introduce the Dual Switched-Capacitor Return-to-Zero (Dual-SCRZ) DAC, which addresses this problem. It combines the low clock jitter sensitivity of a Switched-Capacitor DAC with the low peak-to-average ratio characteristic of an NRZ DAC. A single-bit continuous-time ΔΣ modulator that uses the Dual-SCRZ technique and opamp-assistance to improve linearity and reduce jitter sensitivity achieves 91/85.1/83dB DR/SNR/SNDR in a 2MHz bandwidth. Operating at a sampling rate of 256MHz in a 0.18μm CMOS process, the CTDSM dissipates 14.8mW from a 1.8V supply.
{"title":"A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC","authors":"Amrith Sukumaran, S. Pavan","doi":"10.1109/ESSCIRC.2015.7313866","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313866","url":null,"abstract":"DACs based on switched-capacitor feedback are used in CTΔΣMs to achieve low jitter sensitivity. Unfortunately, they all severely compromise the alias rejection of the modulator around multiples of the sampling frequency. We introduce the Dual Switched-Capacitor Return-to-Zero (Dual-SCRZ) DAC, which addresses this problem. It combines the low clock jitter sensitivity of a Switched-Capacitor DAC with the low peak-to-average ratio characteristic of an NRZ DAC. A single-bit continuous-time ΔΣ modulator that uses the Dual-SCRZ technique and opamp-assistance to improve linearity and reduce jitter sensitivity achieves 91/85.1/83dB DR/SNR/SNDR in a 2MHz bandwidth. Operating at a sampling rate of 256MHz in a 0.18μm CMOS process, the CTDSM dissipates 14.8mW from a 1.8V supply.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89664483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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