Pub Date : 2015-09-18DOI: 10.1109/ESSCIRC.2015.7313901
F. Kuo, M. Babaie, H. Chen, K. Yen, Jinn-Yeh Chien, Lan-chou Cho, F. Kuo, C. Jou, F. Hsueh, R. Staszewski
We propose a new transmitter (TX) architecture for ultra-low power radios. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter is realized in 28nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5mW while delivering 0dBm/3 dBm RF power in Bluetooth Low-Energy.
{"title":"A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm","authors":"F. Kuo, M. Babaie, H. Chen, K. Yen, Jinn-Yeh Chien, Lan-chou Cho, F. Kuo, C. Jou, F. Hsueh, R. Staszewski","doi":"10.1109/ESSCIRC.2015.7313901","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313901","url":null,"abstract":"We propose a new transmitter (TX) architecture for ultra-low power radios. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter is realized in 28nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5mW while delivering 0dBm/3 dBm RF power in Bluetooth Low-Energy.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86763113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-14DOI: 10.1109/ESSCIRC.2015.7313834
B. Debaillie, B. V. Liempd, B. Hershberg, J. Craninckx, K. Rikkinen, D. V. D. Broek, E. Klumperink, B. Nauta
In-band full-duplex is a promising air interface technique to tackle several of the key challenges of next generation (5G) mobile networks. Simultaneous transmission and reception in the same frequency band increases the throughput and spectral efficiency, and reduces the air interface delay. Its implementation in 5G systems, however, restrains the full-duplex transceiver design requirements. Two analog integrated circuit solutions are presented and evaluated in the frame of 5G applications. The first design is a self-interference cancelling front-end implemented in 65nm CMOS, and the second design is an electrical-balance duplexer implemented in 0.18μm RF SOI CMOS. Both designs are attractive in the context of 5G; they allow dense integration, are configurable to support alternative and legacy standards, are compatible with conventional antenna(s), and they provide an attractive full-duplex performance for wireless communications.
带内全双工是一种很有前途的空中接口技术，可以解决下一代(5G)移动网络的几个关键挑战。在同一频段内同时收发，提高了吞吐量和频谱效率，减少了空口延迟。然而，它在5G系统中的实现限制了全双工收发器的设计要求。在5G应用的框架下，提出并评估了两种模拟集成电路解决方案。第一个设计是采用65nm CMOS实现的自干扰消除前端，第二个设计是采用0.18μm RF SOI CMOS实现的电平衡双工器。在5G的背景下，这两种设计都很有吸引力;它们允许密集集成，可配置以支持替代标准和传统标准，与传统天线兼容，并为无线通信提供有吸引力的全双工性能。
{"title":"In-band full-duplex transceiver technology for 5G mobile networks","authors":"B. Debaillie, B. V. Liempd, B. Hershberg, J. Craninckx, K. Rikkinen, D. V. D. Broek, E. Klumperink, B. Nauta","doi":"10.1109/ESSCIRC.2015.7313834","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313834","url":null,"abstract":"In-band full-duplex is a promising air interface technique to tackle several of the key challenges of next generation (5G) mobile networks. Simultaneous transmission and reception in the same frequency band increases the throughput and spectral efficiency, and reduces the air interface delay. Its implementation in 5G systems, however, restrains the full-duplex transceiver design requirements. Two analog integrated circuit solutions are presented and evaluated in the frame of 5G applications. The first design is a self-interference cancelling front-end implemented in 65nm CMOS, and the second design is an electrical-balance duplexer implemented in 0.18μm RF SOI CMOS. Both designs are attractive in the context of 5G; they allow dense integration, are configurable to support alternative and legacy standards, are compatible with conventional antenna(s), and they provide an attractive full-duplex performance for wireless communications.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80081546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/ESSCIRC.2015.7313908
Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, H. Ko, Sungchun Jang, Sang-Hyeok Chu, W. Bae, Yoonsoo Kim, D. Jeong
In this paper, a low-phase-noise subharmonically injection-locked all-digital phase-locked loop (PLL) with simplified overall architecture based on a complementary switched injection technique and a sub-sampling bang-bang detector (SSBBPD) is presented. The proposed PLL does not require a timing calibration circuit for phase alignment between the PLL and injection loops. Moreover, instead of a pulse generator, a complementary switched injection technique is used to achieve high frequency (e.g. 5 GHz) injection-locked oscillator. The proposed PLL was implemented in a 65-nm CMOS process on an active area of 0.06mm2, with measurement result showing that it achieves a 484-fs integrated RMS jitter from 1 kHz to 40 MHz at a 5-GHz output frequency while consuming 15.4 mW.
{"title":"A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection","authors":"Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, H. Ko, Sungchun Jang, Sang-Hyeok Chu, W. Bae, Yoonsoo Kim, D. Jeong","doi":"10.1109/ESSCIRC.2015.7313908","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313908","url":null,"abstract":"In this paper, a low-phase-noise subharmonically injection-locked all-digital phase-locked loop (PLL) with simplified overall architecture based on a complementary switched injection technique and a sub-sampling bang-bang detector (SSBBPD) is presented. The proposed PLL does not require a timing calibration circuit for phase alignment between the PLL and injection loops. Moreover, instead of a pulse generator, a complementary switched injection technique is used to achieve high frequency (e.g. 5 GHz) injection-locked oscillator. The proposed PLL was implemented in a 65-nm CMOS process on an active area of 0.06mm2, with measurement result showing that it achieves a 484-fs integrated RMS jitter from 1 kHz to 40 MHz at a 5-GHz output frequency while consuming 15.4 mW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74960596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/ESSCIRC.2015.7313864
C. D. Berti, P. Malcovati, L. Crespi, A. Baschirotto
A 3rd-order continuous-time ΣΔ modulator for MEMS microphones in 0.16-μm CMOS technology achieves 106.7-dB DR and 93.2-dB peak SNDR, consuming 390 μW from a 1.6-V power supply and occupying an area of 0.21 mm2. The ΣΔ modulator, based on a feedforward architecture, uses only two operational amplifiers for achieving the 3rd-order loop-filter transfer function, a 15-level quantizer, and a feedback DAC with three-level current-steering elements, which minimizes the noise contribution at small input signal, in order to achieve a DR > 100 dB with the largest reported Schreier FoM (184 dB).
{"title":"A 106.7-dB DR, 390-μW CT 3rd-order ΣΔ modulator for MEMS microphones","authors":"C. D. Berti, P. Malcovati, L. Crespi, A. Baschirotto","doi":"10.1109/ESSCIRC.2015.7313864","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313864","url":null,"abstract":"A 3<sup>rd</sup>-order continuous-time ΣΔ modulator for MEMS microphones in 0.16-μm CMOS technology achieves 106.7-dB DR and 93.2-dB peak SNDR, consuming 390 μW from a 1.6-V power supply and occupying an area of 0.21 mm<sup>2</sup>. The ΣΔ modulator, based on a feedforward architecture, uses only two operational amplifiers for achieving the 3<sup>rd</sup>-order loop-filter transfer function, a 15-level quantizer, and a feedback DAC with three-level current-steering elements, which minimizes the noise contribution at small input signal, in order to achieve a DR > 100 dB with the largest reported Schreier FoM (184 dB).","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89838498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Conversion efficiency degrades in case of heavy-to-light loading change since state-of-art overshoot reduction techniques simply dissipate redundant energy at the output of buck DC-DC converter. Thus, the proposed dual-mode ripple-recovered compensator (D-RRC) and multi-phase suppressing output overshoot voltage (MP-SOOV) technique uses 33nH bondwire inductance to recycle energy and provides 47.1mW/μs ultra-fast power-recycling rate to suppress overshoot voltage from 507mV to 95mV with 81.3% improvement when load changes from 1.7A to 0.3A. Experimental results show 93% high efficiency and highspeed operation with only tens of nano second on-time period.
{"title":"Suppressing output overshoot voltage technique with 47.1mW/μs power-recycling rate and 93% peak efficiency DC-DC converter for multi-core processors","authors":"M. Chien, Wen-Hau Yang, Ying-Wei Chou, Hsin-Chieh Chen, Wei-Chung Chen, Ke-Horng Chen, Chinder Wey, Shin-Chi Lai, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Hsin-Yu Luo","doi":"10.1109/ESSCIRC.2015.7313860","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313860","url":null,"abstract":"Conversion efficiency degrades in case of heavy-to-light loading change since state-of-art overshoot reduction techniques simply dissipate redundant energy at the output of buck DC-DC converter. Thus, the proposed dual-mode ripple-recovered compensator (D-RRC) and multi-phase suppressing output overshoot voltage (MP-SOOV) technique uses 33nH bondwire inductance to recycle energy and provides 47.1mW/μs ultra-fast power-recycling rate to suppress overshoot voltage from 507mV to 95mV with 81.3% improvement when load changes from 1.7A to 0.3A. Experimental results show 93% high efficiency and highspeed operation with only tens of nano second on-time period.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79127504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/ESSCIRC.2015.7313844
Haikun Jia, B. Chi, Zhihua Wang
An 8.2 GHz low-phase-noise Class-F quadrature voltage controlled oscillator (QVCO) is presented. With the proposed triple coupling technique, the oscillation frequency of the QVCO is only determined by the inter-stage passive matching components, and the introduced third harmonic at the drain of the transistors help form the approximately square voltage waveform to achieve low impulse-sensitivity function (ISF) value, which results in good phase noise performance and good quadrature phase accuracy. Implemented in 65nm CMOS, the QVCO shows a measured phase noise of -120.86 dBc/Hz at 1 MHz offset from 7.76 GHz carrier frequency (188.4 dBc/Hz FoM value), and a measured quadrature phase error of 0.72°. The QVCO consumes 10.6-12.3 mW power from one 0.6 V supply and 0.38mm2 active die area.
{"title":"An 8.2 GHz triple coupling low-phase-noise class-F QVCO in 65nm CMOS","authors":"Haikun Jia, B. Chi, Zhihua Wang","doi":"10.1109/ESSCIRC.2015.7313844","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313844","url":null,"abstract":"An 8.2 GHz low-phase-noise Class-F quadrature voltage controlled oscillator (QVCO) is presented. With the proposed triple coupling technique, the oscillation frequency of the QVCO is only determined by the inter-stage passive matching components, and the introduced third harmonic at the drain of the transistors help form the approximately square voltage waveform to achieve low impulse-sensitivity function (ISF) value, which results in good phase noise performance and good quadrature phase accuracy. Implemented in 65nm CMOS, the QVCO shows a measured phase noise of -120.86 dBc/Hz at 1 MHz offset from 7.76 GHz carrier frequency (188.4 dBc/Hz FoM value), and a measured quadrature phase error of 0.72°. The QVCO consumes 10.6-12.3 mW power from one 0.6 V supply and 0.38mm2 active die area.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88287679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/ESSCIRC.2015.7313913
Chao Chen, Zhao Chen, Z. Chang, M. Pertijs
This paper presents a power- and area-efficient 9-channel LNA array for piezoelectric ultrasound transducers to enable real-time 3D imaging with miniature endoscopic and catheter-based probes. In view of the relatively low impedance of piezoelectric transducers, the LNA is implemented as a capacitive feedback voltage amplifier, rather than a trans-impedance amplifier, to achieve a better noise-power trade-off. The use of a current-efficient inverter-based OTA with optimized bias scheme and dual-rail regulation further improves the power efficiency of the LNA while keeping the area compact: 0.01 mm2 per channel. Electrical and acoustic measurement results show that the proposed LNA achieves a 0.6 mPa/√Hz input-referred noise at 4 MHz while consuming only 0.135 mW, which represents a noise efficiency 2.5 × better than the state-of-the-art.
{"title":"A compact 0.135-mW/channel LNA array for piezoelectric ultrasound transducers","authors":"Chao Chen, Zhao Chen, Z. Chang, M. Pertijs","doi":"10.1109/ESSCIRC.2015.7313913","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313913","url":null,"abstract":"This paper presents a power- and area-efficient 9-channel LNA array for piezoelectric ultrasound transducers to enable real-time 3D imaging with miniature endoscopic and catheter-based probes. In view of the relatively low impedance of piezoelectric transducers, the LNA is implemented as a capacitive feedback voltage amplifier, rather than a trans-impedance amplifier, to achieve a better noise-power trade-off. The use of a current-efficient inverter-based OTA with optimized bias scheme and dual-rail regulation further improves the power efficiency of the LNA while keeping the area compact: 0.01 mm2 per channel. Electrical and acoustic measurement results show that the proposed LNA achieves a 0.6 mPa/√Hz input-referred noise at 4 MHz while consuming only 0.135 mW, which represents a noise efficiency 2.5 × better than the state-of-the-art.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88832436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/ESSCIRC.2015.7313887
Nam-Seog Kim, J. Rabaey
A triple-channel wavelet-based dual-resolution spectrum sensor fabricated with 1V 65nm CMOS technology provides 3.1-10.6GHz range of spectrum sensing bandwidth with <;6.4mW/GHz efficiency. Dual-resolution cooperative sensing with two adjacent channels eliminates fine detection process, which leads to <;0.4msec of total sensing time. The spectrum sensor achieves the minimum detection sensitivity of -75dBm and out of band rejection of <;-45dBc by exploiting triangular wavelet with LPF. 3.1-5GHz harmonic rejection mixers suppress third harmonic to -32dBc. Die area is 2.75mm2 with on-die PLLs.
{"title":"A 3.1–10.6GHz wavelet-based dual-resolution spectrum sensing with harmonic rejection mixers","authors":"Nam-Seog Kim, J. Rabaey","doi":"10.1109/ESSCIRC.2015.7313887","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313887","url":null,"abstract":"A triple-channel wavelet-based dual-resolution spectrum sensor fabricated with 1V 65nm CMOS technology provides 3.1-10.6GHz range of spectrum sensing bandwidth with <;6.4mW/GHz efficiency. Dual-resolution cooperative sensing with two adjacent channels eliminates fine detection process, which leads to <;0.4msec of total sensing time. The spectrum sensor achieves the minimum detection sensitivity of -75dBm and out of band rejection of <;-45dBc by exploiting triangular wavelet with LPF. 3.1-5GHz harmonic rejection mixers suppress third harmonic to -32dBc. Die area is 2.75mm2 with on-die PLLs.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86083079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/ESSCIRC.2015.7313836
Ying Chen, Y. Pei, D. Leenaerts
A fully-integrated 30GHz single-channel phased array transmitter is demonstrated in a 0.25-μm SiGe:C BiCMOS process. The integration covers the baseband I/Q modulation up to the RF output, including a 40GHz PLL with an ultra-low phase noise. A phase shift resolution of 10° and an amplitude resolution of 5-bit are achieved with an LO phase-oversampling vector modulator. The CSP packaged transmitter delivers a saturation output power of 10~13dBm over 27.6~30.3GHz. The 40GHz PLL achieves a measured integrated phase noise of 1.5° RMS from 100Hz to 10MHz and has a reference spur <;-70dBc. The transmitter chip achieves an EVM of 5.9% at 6dB back-off for 40-Mb/s 16-QAM modulation. The proposed transmitter is suitable for Ka-band VSAT and back-haul point-to-point applications.
{"title":"A fully integrated 30GHz 16-QAM single-channel phased array transmitter with 5.9% EVM at 6dB back-off","authors":"Ying Chen, Y. Pei, D. Leenaerts","doi":"10.1109/ESSCIRC.2015.7313836","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313836","url":null,"abstract":"A fully-integrated 30GHz single-channel phased array transmitter is demonstrated in a 0.25-μm SiGe:C BiCMOS process. The integration covers the baseband I/Q modulation up to the RF output, including a 40GHz PLL with an ultra-low phase noise. A phase shift resolution of 10° and an amplitude resolution of 5-bit are achieved with an LO phase-oversampling vector modulator. The CSP packaged transmitter delivers a saturation output power of 10~13dBm over 27.6~30.3GHz. The 40GHz PLL achieves a measured integrated phase noise of 1.5° RMS from 100Hz to 10MHz and has a reference spur <;-70dBc. The transmitter chip achieves an EVM of 5.9% at 6dB back-off for 40-Mb/s 16-QAM modulation. The proposed transmitter is suitable for Ka-band VSAT and back-haul point-to-point applications.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77545412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/ESSCIRC.2015.7313838
K. Lee, Junyoung Park, Injoon Hong, H. Yoo
An Intelligent Task Scheduler (ITS) together with Congestion-avoiding Flexible Routing (CAFeR) are proposed to minimize network congestion of network-on-chip (NoC), so as to improve the throughput of multi-core system for fast and accurate object recognition. The ITS predicts the communication pattern of next frame and intelligently assigns tasks to consumer cores. It also adaptively controls buffer threshold of each link in NoC to support CAFeR to enhance packet transaction throughput, which enables packets to communicate with less congestion. Thanks to the proposed ITS with 91.4% of prediction accuracy and CAFeR, the overall latency is reduced by 50.2%.
{"title":"Intelligent task scheduler with high throughput NoC for real-time mobile object recognition SoC","authors":"K. Lee, Junyoung Park, Injoon Hong, H. Yoo","doi":"10.1109/ESSCIRC.2015.7313838","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313838","url":null,"abstract":"An Intelligent Task Scheduler (ITS) together with Congestion-avoiding Flexible Routing (CAFeR) are proposed to minimize network congestion of network-on-chip (NoC), so as to improve the throughput of multi-core system for fast and accurate object recognition. The ITS predicts the communication pattern of next frame and intelligently assigns tasks to consumer cores. It also adaptively controls buffer threshold of each link in NoC to support CAFeR to enhance packet transaction throughput, which enables packets to communicate with less congestion. Thanks to the proposed ITS with 91.4% of prediction accuracy and CAFeR, the overall latency is reduced by 50.2%.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81830053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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