Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313842
S. Mathew, D. Johnston, P. Newman, Sudhir K. Satpathy, Vikram B. Suresh, M. Anders, Himanshu Kaul, Gregory K. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy
An all-digital full-entropy True Random Number Generator (TRNG) with measured 1.3GHz operation and total power consumption of 1.5mW at 0.75V, 25oC is fabricated in 14nm FinFET CMOS. Three independent self-calibrating entropy sources, coupled with pre-extraction correlation suppressors and a real-time BIW extractor enable ultra-low energy consumption of 3pJ/bit, while generating cryptographic-quality keys with measured Shannon entropy up to 0.99999999995 and lower-bound min-entropy >0.99. The 100% digital design enables a compact layout occupying 1088μm2, with scalable operation down to 300mV, while passing all NIST statistical randomness tests.
{"title":"μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS","authors":"S. Mathew, D. Johnston, P. Newman, Sudhir K. Satpathy, Vikram B. Suresh, M. Anders, Himanshu Kaul, Gregory K. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy","doi":"10.1109/ESSCIRC.2015.7313842","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313842","url":null,"abstract":"An all-digital full-entropy True Random Number Generator (TRNG) with measured 1.3GHz operation and total power consumption of 1.5mW at 0.75V, 25oC is fabricated in 14nm FinFET CMOS. Three independent self-calibrating entropy sources, coupled with pre-extraction correlation suppressors and a real-time BIW extractor enable ultra-low energy consumption of 3pJ/bit, while generating cryptographic-quality keys with measured Shannon entropy up to 0.99999999995 and lower-bound min-entropy >0.99. The 100% digital design enables a compact layout occupying 1088μm2, with scalable operation down to 300mV, while passing all NIST statistical randomness tests.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90278448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313878
Yeomyung Kim, Woojun Choi, Jaehoon Kim, Sanghoon Lee, Sanghoon Lee, Hyeongon Kim, K. Makinwa, Youngcheol Chae, Tae Wook Kim
This paper describes an all-CMOS embedded temperature sensor that directly controls the self-refresh period of a 25nm mobile DRAM. It occupies 0.02mm2, and achieves 0.04°C resolution and ±2°C accuracy from 20°C to 95°C after a single temperature trim. This performance is enabled by the use of dynamic threshold MOSFETs as temperature sensing devices, and by using chopping and trimming to mitigate the effects of device mismatch and process spread. The sensor consumes 9uW at a conversion rate of 7-kHz and a resolution of 50mK, which corresponds to a resolution FoM of 3.2pJK2. When used to control the self-refresh period of an 8GB mobile DRAM, the sensor reduces its standby current by 7x over a 20°C to 95°C range.
{"title":"A 0.02mm2 embedded temperature sensor with ±2°C inaccuracy for self-refresh control in 25nm mobile DRAM","authors":"Yeomyung Kim, Woojun Choi, Jaehoon Kim, Sanghoon Lee, Sanghoon Lee, Hyeongon Kim, K. Makinwa, Youngcheol Chae, Tae Wook Kim","doi":"10.1109/ESSCIRC.2015.7313878","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313878","url":null,"abstract":"This paper describes an all-CMOS embedded temperature sensor that directly controls the self-refresh period of a 25nm mobile DRAM. It occupies 0.02mm2, and achieves 0.04°C resolution and ±2°C accuracy from 20°C to 95°C after a single temperature trim. This performance is enabled by the use of dynamic threshold MOSFETs as temperature sensing devices, and by using chopping and trimming to mitigate the effects of device mismatch and process spread. The sensor consumes 9uW at a conversion rate of 7-kHz and a resolution of 50mK, which corresponds to a resolution FoM of 3.2pJK2. When used to control the self-refresh period of an 8GB mobile DRAM, the sensor reduces its standby current by 7x over a 20°C to 95°C range.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90302662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313898
S. Spiridon, Han Yan, H. Eberhart
This paper presents a linearity improvement technique for overcoming signal-dependent induced switching time mismatch in DAC-based transmitters. By dynamically triggering a dummy final retiming stage, the signal-dependent induced pattern for the switching time of the DAC current source cells is broken. The immediate effect is the significant distortion reduction (IM3 improves up to 15 dB), especially for narrowband signals. Thus, the full linearity potential of these transmitters is achieved by an IM3 of -73 dBc at 1 GHz for only 2 MHz tone spacing. With minimal design optimizations, the overall DAC power consumption increase due to the dummy triggering is limited to only 10%. Two latest generation (40 nm and 28 nm) high-speed wide-band DAC-based wireline transmitters have been used as test vehicles for verifying this technique.
{"title":"A linearity improvement technique for overcoming signal-dependent induced switching time mismatch in DAC-Based transmitters","authors":"S. Spiridon, Han Yan, H. Eberhart","doi":"10.1109/ESSCIRC.2015.7313898","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313898","url":null,"abstract":"This paper presents a linearity improvement technique for overcoming signal-dependent induced switching time mismatch in DAC-based transmitters. By dynamically triggering a dummy final retiming stage, the signal-dependent induced pattern for the switching time of the DAC current source cells is broken. The immediate effect is the significant distortion reduction (IM3 improves up to 15 dB), especially for narrowband signals. Thus, the full linearity potential of these transmitters is achieved by an IM3 of -73 dBc at 1 GHz for only 2 MHz tone spacing. With minimal design optimizations, the overall DAC power consumption increase due to the dummy triggering is limited to only 10%. Two latest generation (40 nm and 28 nm) high-speed wide-band DAC-based wireline transmitters have been used as test vehicles for verifying this technique.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78273667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313894
K. Sarfraz, M. Chan
This paper presents the highest measured read access frequency for a multi-ported register file (RF) fabricated in a low-power (LP) 1.2V TSMC 65nm low-Vt CMOS process. Active power is reduced with the use of low-capacitance dynamic local bitlines (LBLs). The dc noise robustness of low-Vt dynamic LBLs is enhanced by 94% compared to conventional low-Vt dynamic LBLs with novel gated inverter-based read port architecture. The 2-read, 1-write-ported 32-entry × 32-bit per word RF demonstrates measured 3.2GHz operation at 1.2V by consuming 44.2mW of active power and 197.5μW of leakage power. The RF is measured down to 0.4V.
{"title":"A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines","authors":"K. Sarfraz, M. Chan","doi":"10.1109/ESSCIRC.2015.7313894","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313894","url":null,"abstract":"This paper presents the highest measured read access frequency for a multi-ported register file (RF) fabricated in a low-power (LP) 1.2V TSMC 65nm low-Vt CMOS process. Active power is reduced with the use of low-capacitance dynamic local bitlines (LBLs). The dc noise robustness of low-Vt dynamic LBLs is enhanced by 94% compared to conventional low-Vt dynamic LBLs with novel gated inverter-based read port architecture. The 2-read, 1-write-ported 32-entry × 32-bit per word RF demonstrates measured 3.2GHz operation at 1.2V by consuming 44.2mW of active power and 197.5μW of leakage power. The RF is measured down to 0.4V.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79498134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313821
Y. Deval
{"title":"RFIC design by mathematics for next generation wireless access","authors":"Y. Deval","doi":"10.1109/ESSCIRC.2015.7313821","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313821","url":null,"abstract":"","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82296021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313822
Antonio A. D'Amico, M. Matteis, S. D’Amico, C. D. Berti, L. Crespi, A. Baschirotto
This paper presents a 4th-order low-pass continuous-time filter with 24MHz bandwidth. Using cross-coupled MOS transistors combined with capacitors and resistors, this architecture synthesizes two complex-conjugate-poles pairs. The filter is designed and optimized to feature high-linearity along all filter passband, and, in particular, at the cut-off frequency edge. The filter consumes 100μA with 1.8V voltage supply, and achieves 45μW/pole power consumption, 150μVRMS input-referred noise, 16dBm IIP3 with 2-3MHz input tones and 5dBm IIP3 near the cut frequency.
{"title":"A 4th-order 100μA diode-C-based filter with 5dBm-IIP3 at the 24MHz cut-off frequency","authors":"Antonio A. D'Amico, M. Matteis, S. D’Amico, C. D. Berti, L. Crespi, A. Baschirotto","doi":"10.1109/ESSCIRC.2015.7313822","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313822","url":null,"abstract":"This paper presents a 4th-order low-pass continuous-time filter with 24MHz bandwidth. Using cross-coupled MOS transistors combined with capacitors and resistors, this architecture synthesizes two complex-conjugate-poles pairs. The filter is designed and optimized to feature high-linearity along all filter passband, and, in particular, at the cut-off frequency edge. The filter consumes 100μA with 1.8V voltage supply, and achieves 45μW/pole power consumption, 150μVRMS input-referred noise, 16dBm IIP3 with 2-3MHz input tones and 5dBm IIP3 near the cut frequency.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80184282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313875
T. Kawajiri, Takahiro Moroto, H. Ishikuro
This paper describes a system of single-inductor-dual-output (SIDO) wireless power delivery for mobile applications. By updating control signal in the feedback loop by every switching clock cycle, fast tracking to the load change is realized while spurious emission is suppressed by using pseudorandom-sequence PWM (PRS-PWM). Transmitter and receiver chips were fabricated in 0.18μm CMOS process and mounted on the wireless power transfer test board. The system achieved response time shorter than 10μsec. Two output voltages are regulated at 8V and 16V, and maximum efficiency of 41% was achieved when the total output power is 500mW.
{"title":"A low EMI SIDO wireless power transfer system with 10μsec response time","authors":"T. Kawajiri, Takahiro Moroto, H. Ishikuro","doi":"10.1109/ESSCIRC.2015.7313875","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313875","url":null,"abstract":"This paper describes a system of single-inductor-dual-output (SIDO) wireless power delivery for mobile applications. By updating control signal in the feedback loop by every switching clock cycle, fast tracking to the load change is realized while spurious emission is suppressed by using pseudorandom-sequence PWM (PRS-PWM). Transmitter and receiver chips were fabricated in 0.18μm CMOS process and mounted on the wireless power transfer test board. The system achieved response time shorter than 10μsec. Two output voltages are regulated at 8V and 16V, and maximum efficiency of 41% was achieved when the total output power is 500mW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79072170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313828
Tong Zhang, M. Taghivand, J. Rudell
An integrated two-stage polyphase filters (PPFs) with feedback control is proposed for local oscillator (LO) quadrature generation at millimeter-wave band frequencies. The PPFs second stage utilizes triode-region NMOS transistors to implement variable resistors which are accurately controlled to minimize any IQ mismatch. A prototype quadrature signal generator for use in a homodyne 60GHz receiver is integrated in 28nm LP CMOS process. A worst-case measured phase and amplitude imbalance of 2o and 0.32dB across a frequency range of 55-70GHz is reported. The core IQ generator size is 20μ m × 40μ m while consuming 81 μW, which includes 9μW for the feedback control loop and 40A from 1.8V supply for the opamp. The input impedance is simulated to be 150Q in parallel with 18fF.
提出了一种带反馈控制的集成两级多相滤波器(PPFs)，用于毫米波本振(LO)正交产生。ppf的第二级利用三极管区NMOS晶体管实现可变电阻，精确控制以最小化任何IQ不匹配。采用28nm LP CMOS工艺集成了用于60GHz零差式接收机的正交信号发生器原型。在55-70GHz频率范围内，最坏情况下测量的相位和幅度不平衡分别为20和0.32dB。核心IQ发生器尺寸为20μ m × 40μ m，功耗为81 μW，其中反馈控制回路功耗为9μW，运放1.8V电源功耗为40A。模拟输入阻抗为150Q，并联18fF。
{"title":"A 55–70GHz two-stage tunable polyphase filter with feedback control for quadrature generation with <2° and <0.32dB phase/amplitude imbalance in 28nm CMOS process","authors":"Tong Zhang, M. Taghivand, J. Rudell","doi":"10.1109/ESSCIRC.2015.7313828","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313828","url":null,"abstract":"An integrated two-stage polyphase filters (PPFs) with feedback control is proposed for local oscillator (LO) quadrature generation at millimeter-wave band frequencies. The PPFs second stage utilizes triode-region NMOS transistors to implement variable resistors which are accurately controlled to minimize any IQ mismatch. A prototype quadrature signal generator for use in a homodyne 60GHz receiver is integrated in 28nm LP CMOS process. A worst-case measured phase and amplitude imbalance of 2o and 0.32dB across a frequency range of 55-70GHz is reported. The core IQ generator size is 20μ m × 40μ m while consuming 81 μW, which includes 9μW for the feedback control loop and 40A from 1.8V supply for the opamp. The input impedance is simulated to be 150Q in parallel with 18fF.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77477731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313912
M. Ghanad, C. Dehollain, Michael M. Green
A time-interleaved wireless power transmission technique is presented to avoid interference between power transmission, sensor readout and communication operations. A time-based voltage control loop is also proposed to increase wireless power transmission efficiency. The control loop adjusts the duration of power transfer frames based on the coupling factor between the coils of the base station and the implantable device. An implantable chip with average RF power dissipation of 29.5 μW is fabricated using 0.18 μm CMOS technology. The chip records local body temperature with accuracy of ±0.05°C.
{"title":"A 30 μW remotely-powered implant with time-based voltage regulation","authors":"M. Ghanad, C. Dehollain, Michael M. Green","doi":"10.1109/ESSCIRC.2015.7313912","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313912","url":null,"abstract":"A time-interleaved wireless power transmission technique is presented to avoid interference between power transmission, sensor readout and communication operations. A time-based voltage control loop is also proposed to increase wireless power transmission efficiency. The control loop adjusts the duration of power transfer frames based on the coupling factor between the coils of the base station and the implantable device. An implantable chip with average RF power dissipation of 29.5 μW is fabricated using 0.18 μm CMOS technology. The chip records local body temperature with accuracy of ±0.05°C.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87022021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313858
Fan Yang, P. Mok
A 65-nm external capacitor-less asynchronous digital low drop-out regulator (DLDO) with adaptive sizing and fast transient response is presented in this paper. Operating at a wide input voltage range from as low as 0.6V to 1V, this DLDO is capable of delivering a maximum current of 500mA with 50mV drop-out voltage. The proposed adaptive sizing featured by row-column-bit 3-dimensional (3D) power stage and its asynchronous adaptive digital pipeline control have enabled a fast transient response to nanoseconds' loading current change and a 200mV per 10ns reference voltage switching, as well as a fine resolution of 768 levels (~9.5 bits) with a 5mV output ripple. The quiescent current consumed by this DLDO at steady operation is as low as 300μA over the whole input range.
{"title":"A 0.6–1V input capacitor-less asynchronous digital LDO with fast transient response achieving 9.5b over 500mA loading range in 65-nm CMOS","authors":"Fan Yang, P. Mok","doi":"10.1109/ESSCIRC.2015.7313858","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313858","url":null,"abstract":"A 65-nm external capacitor-less asynchronous digital low drop-out regulator (DLDO) with adaptive sizing and fast transient response is presented in this paper. Operating at a wide input voltage range from as low as 0.6V to 1V, this DLDO is capable of delivering a maximum current of 500mA with 50mV drop-out voltage. The proposed adaptive sizing featured by row-column-bit 3-dimensional (3D) power stage and its asynchronous adaptive digital pipeline control have enabled a fast transient response to nanoseconds' loading current change and a 200mV per 10ns reference voltage switching, as well as a fine resolution of 768 levels (~9.5 bits) with a 5mV output ripple. The quiescent current consumed by this DLDO at steady operation is as low as 300μA over the whole input range.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87043324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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