Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616794
S. Trendelenburg, D. De Dorigo, F. Henrici, J. Becker, Y. Manoli
This work presents techniques for mapping various Gm-C filter topologies on a specialized field-programmable analog array (FPAA) for continuous-time filters. Through its unique hexagonal architecture, it is possible to map most well-known Gm-C filter topologies to the array, including cascaded biquads, simulated LC-ladders, as well as integrator feedback and feed-forward structures. Through tuning of the digitally programmable filter elements, the properties of the resulting filters, such as bandwidth, filter type or cutoff frequencies can be varied after the filter topology has been instantiated.
{"title":"Instantiation of higher order filters on a continuous-time field-programmable analog array","authors":"S. Trendelenburg, D. De Dorigo, F. Henrici, J. Becker, Y. Manoli","doi":"10.1109/MWSCAS.2008.4616794","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616794","url":null,"abstract":"This work presents techniques for mapping various Gm-C filter topologies on a specialized field-programmable analog array (FPAA) for continuous-time filters. Through its unique hexagonal architecture, it is possible to map most well-known Gm-C filter topologies to the array, including cascaded biquads, simulated LC-ladders, as well as integrator feedback and feed-forward structures. Through tuning of the digitally programmable filter elements, the properties of the resulting filters, such as bandwidth, filter type or cutoff frequencies can be varied after the filter topology has been instantiated.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125040764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616925
A. C. Parker, J. Joshi, Chih-Chieh Hsu, N.A.D. Singh
A neural dendritic computational circuit design is presented here. The circuit models the result of action potentials applied to biological synapses on a portion of a dendritic tree. The resultant excitatory post synaptic potentials (EPSPs) are combined in a dendritic tree that demonstrates linear, superlinear and sublinear summation of both spatially and temporally separated EPSPs. The synapse circuit models include neurotransmitter action, reuptake and membrane potentials. The output of the circuit is a combined Excitatory Post Synaptic Potential (EPSP). The circuit is simulated using carbon nanotube SPICE models. Variations of this design can be implemented to create a variety of dendritic computational subunits.
{"title":"A carbon nanotube implementation of temporal and spatial dendritic computations","authors":"A. C. Parker, J. Joshi, Chih-Chieh Hsu, N.A.D. Singh","doi":"10.1109/MWSCAS.2008.4616925","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616925","url":null,"abstract":"A neural dendritic computational circuit design is presented here. The circuit models the result of action potentials applied to biological synapses on a portion of a dendritic tree. The resultant excitatory post synaptic potentials (EPSPs) are combined in a dendritic tree that demonstrates linear, superlinear and sublinear summation of both spatially and temporally separated EPSPs. The synapse circuit models include neurotransmitter action, reuptake and membrane potentials. The output of the circuit is a combined Excitatory Post Synaptic Potential (EPSP). The circuit is simulated using carbon nanotube SPICE models. Variations of this design can be implemented to create a variety of dendritic computational subunits.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123011625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616737
Hugang Han, Bo Mo, Fenghui Yao
In general, the state feedback control gain can be obtained by solving certain linear matrix inequalities (LMIs) when using the Takagi-Sugeno (T-S) fuzzy model to develop a control system. In this paper, the reconstruction error between the real system to be controlled and its T-S fuzzy model, which consists of parameter uncertainties and external disturbance, is considered. As a result, we arrive at a new T-S fuzzy controller that has two parts: one is obtained by solving certain LMIs (fixed part) and another one is acquired by an adaptive law (variable part). The proposed controller can guarantee the control state to converge and uniformly bounded while maintaining all the signals involved stable.
{"title":"T-S fuzzy controller for a class of uncertain nonlinear systems","authors":"Hugang Han, Bo Mo, Fenghui Yao","doi":"10.1109/MWSCAS.2008.4616737","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616737","url":null,"abstract":"In general, the state feedback control gain can be obtained by solving certain linear matrix inequalities (LMIs) when using the Takagi-Sugeno (T-S) fuzzy model to develop a control system. In this paper, the reconstruction error between the real system to be controlled and its T-S fuzzy model, which consists of parameter uncertainties and external disturbance, is considered. As a result, we arrive at a new T-S fuzzy controller that has two parts: one is obtained by solving certain LMIs (fixed part) and another one is acquired by an adaptive law (variable part). The proposed controller can guarantee the control state to converge and uniformly bounded while maintaining all the signals involved stable.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123611224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616757
B. Leung
Comparisons of phase noise models based on time domain models and frequency domain models are presented. It is shown that time domain approach by this author, based on conventional time scaling and that incorporates multiple threshold crossing phenomenon, reflects the physical mechanism better. Moreover its phase noise expression does not blow up as offset frequency goes to zero. Finally compared to frequency domain methods the transient simulations needed to obtain the necessary parameters are simpler.
{"title":"Comparisons of phase noise models of CMOS ring oscillators","authors":"B. Leung","doi":"10.1109/MWSCAS.2008.4616757","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616757","url":null,"abstract":"Comparisons of phase noise models based on time domain models and frequency domain models are presented. It is shown that time domain approach by this author, based on conventional time scaling and that incorporates multiple threshold crossing phenomenon, reflects the physical mechanism better. Moreover its phase noise expression does not blow up as offset frequency goes to zero. Finally compared to frequency domain methods the transient simulations needed to obtain the necessary parameters are simpler.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114964365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616784
J. Gray, R. Robucci, P. Hasler
We present the methodology for implementing a computational memory element using a floating-gate pFET model suitable for the design and simulation of analog systems. A first-order physically inspired model of pFET hot-election injection is implemented in Verilog-A, fit to experimental data, and then applied to a proposed floating-gate circuit. The model parameters are fit directly to the drain current data from a measured floating-gate pFET, eliminating the need for estimating or measuring gate injection current. The model is used to examine the programming transient response of a proposed analog computational vector-matrix multiplier cell. The circuit eliminates power-supply ramping by using a negative voltage, avoids complex characterization by linearized the injection current, and reduces off-chip interaction with on-chip feedback. We discuss how our model and approach represent a pathway for accessible floating-gate design, simulation, and implementation.
{"title":"The design and simulation model of an analog floating-gate computational element for use in large-scale analog reconfigurable systems","authors":"J. Gray, R. Robucci, P. Hasler","doi":"10.1109/MWSCAS.2008.4616784","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616784","url":null,"abstract":"We present the methodology for implementing a computational memory element using a floating-gate pFET model suitable for the design and simulation of analog systems. A first-order physically inspired model of pFET hot-election injection is implemented in Verilog-A, fit to experimental data, and then applied to a proposed floating-gate circuit. The model parameters are fit directly to the drain current data from a measured floating-gate pFET, eliminating the need for estimating or measuring gate injection current. The model is used to examine the programming transient response of a proposed analog computational vector-matrix multiplier cell. The circuit eliminates power-supply ramping by using a negative voltage, avoids complex characterization by linearized the injection current, and reduces off-chip interaction with on-chip feedback. We discuss how our model and approach represent a pathway for accessible floating-gate design, simulation, and implementation.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123898341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616894
E. Azab, S. Mahmoud
A wide input voltage range differential difference operational floating amplifier is introduced. The proposed realization is based on the cascading connection of a differential difference transconductor (DDT) and a differential input balanced output current op-amp (DIBO). The proposed DDT is based on differential transconductor stage with rail-to-rail differential input voltage swing. The DIBO current op-amp consists of high gain transresistance amplification stage and high CMRR single input balanced output transconductor stage. The new DDOFA block has 74.17 MHz unity gain BW, DC gain of 57 dBmA/V and CMRR of 85.32 dB and rail-to-rail differential input voltage swing using CMOS 0.25 mum technology model.
{"title":"New CMOS realization of the differential difference operational floating amplifier with wide input voltage range","authors":"E. Azab, S. Mahmoud","doi":"10.1109/MWSCAS.2008.4616894","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616894","url":null,"abstract":"A wide input voltage range differential difference operational floating amplifier is introduced. The proposed realization is based on the cascading connection of a differential difference transconductor (DDT) and a differential input balanced output current op-amp (DIBO). The proposed DDT is based on differential transconductor stage with rail-to-rail differential input voltage swing. The DIBO current op-amp consists of high gain transresistance amplification stage and high CMRR single input balanced output transconductor stage. The new DDOFA block has 74.17 MHz unity gain BW, DC gain of 57 dBmA/V and CMRR of 85.32 dB and rail-to-rail differential input voltage swing using CMOS 0.25 mum technology model.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123957239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616935
A. Mvuma, S. Nishimura, T. Hinamoto
Tracking behavior of a gradient-based simplified algorithm for an adaptive infinite impulse response (IIR) notch filter with a sinusoidally-varying input signal frequency is presented in this paper. A first-order difference equation with respect to a steady-state instantaneous frequency tracking error is derived. The difference equation is used to derive tracking error and tracking mean square error (MSE) expressions based on the power spectral density (PSD) method. Extensive computer simulations are included to substantiate the analysis and show its limits.
{"title":"Tracking characteristics of an adaptive IIR notch filter for sinusoidal frequency variation","authors":"A. Mvuma, S. Nishimura, T. Hinamoto","doi":"10.1109/MWSCAS.2008.4616935","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616935","url":null,"abstract":"Tracking behavior of a gradient-based simplified algorithm for an adaptive infinite impulse response (IIR) notch filter with a sinusoidally-varying input signal frequency is presented in this paper. A first-order difference equation with respect to a steady-state instantaneous frequency tracking error is derived. The difference equation is used to derive tracking error and tracking mean square error (MSE) expressions based on the power spectral density (PSD) method. Extensive computer simulations are included to substantiate the analysis and show its limits.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126180488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616939
J. Gray, P. Hasler
Floating-gate charge storage is a key analog VLSI system technique. As the number of floating-gate elements in such VLSI systems increase, the relative area of the analog memory cell and its supporting circuitry become more critical. The compact floating-gate selection and isolation circuitry used in large-scale analog arrays is often based on a flawed assumption: that subthreshold conduction is the dominant source of parasitic charge movement associated with array isolation. The parasitic charge movement is primarily a combination of subthreshold conduction, PN-junction reverse bias current enhanced by gate-overlap, and Fowler-Nordheim tunneling. As a result, array isolation designed specifically to minimize subthreshold conduction can actually enhance the overall parasitic charge movement, leading to programming accuracy degradation. A procedure and experimental data demonstrating parasitic charge movement is shown for a device in an array fabricated on a 0.35 um process. Software and hardware hardware techniques for addressing and eliminating parasitic charge movement are discussed.
{"title":"Parasitic charge movement in floating-gate array programming","authors":"J. Gray, P. Hasler","doi":"10.1109/MWSCAS.2008.4616939","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616939","url":null,"abstract":"Floating-gate charge storage is a key analog VLSI system technique. As the number of floating-gate elements in such VLSI systems increase, the relative area of the analog memory cell and its supporting circuitry become more critical. The compact floating-gate selection and isolation circuitry used in large-scale analog arrays is often based on a flawed assumption: that subthreshold conduction is the dominant source of parasitic charge movement associated with array isolation. The parasitic charge movement is primarily a combination of subthreshold conduction, PN-junction reverse bias current enhanced by gate-overlap, and Fowler-Nordheim tunneling. As a result, array isolation designed specifically to minimize subthreshold conduction can actually enhance the overall parasitic charge movement, leading to programming accuracy degradation. A procedure and experimental data demonstrating parasitic charge movement is shown for a device in an array fabricated on a 0.35 um process. Software and hardware hardware techniques for addressing and eliminating parasitic charge movement are discussed.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"2005 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125808290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616818
B. Shastri, N. Kheder, D. Plant
We experimentally study the effect of channel impairments on the performance of a burst-mode receiver (BMRx) in a 622 Mb/s 20-km Gigabit-capable passive optical network (GPON) uplink. Specifically, we study the impact of mode-partition noise in the GPON uplink in terms of the bit-error rate (BER) and the packet loss ratio (PLR) performance of the system. Our receiver features automatic phase acquisition using a clock phase aligner (CPA), and forward-error correction using (255, 239) Reed-Solomon codes. The BMRx provides instantaneous (0 preamble bit) phase acquisition and a PLR < 10-6 for any phase step (plusmn2pi rads) between consecutive packets. The receiver also accomplishes a 3 dB coding gain at a BER = 10-10. The CPA makes use of a phase picking algorithm and an oversampling clock and data recovery circuit operated at twice the bit rate.
{"title":"Effect of channel impairments on the performance of burst-mode receivers in gigabit PON","authors":"B. Shastri, N. Kheder, D. Plant","doi":"10.1109/MWSCAS.2008.4616818","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616818","url":null,"abstract":"We experimentally study the effect of channel impairments on the performance of a burst-mode receiver (BMRx) in a 622 Mb/s 20-km Gigabit-capable passive optical network (GPON) uplink. Specifically, we study the impact of mode-partition noise in the GPON uplink in terms of the bit-error rate (BER) and the packet loss ratio (PLR) performance of the system. Our receiver features automatic phase acquisition using a clock phase aligner (CPA), and forward-error correction using (255, 239) Reed-Solomon codes. The BMRx provides instantaneous (0 preamble bit) phase acquisition and a PLR < 10-6 for any phase step (plusmn2pi rads) between consecutive packets. The receiver also accomplishes a 3 dB coding gain at a BER = 10-10. The CPA makes use of a phase picking algorithm and an oversampling clock and data recovery circuit operated at twice the bit rate.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129761134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616921
R. Wu, Chen Wang
A novel amplifier design technique based on negative impedance compensation has been proposed in our recent paper. In this paper, we investigate the stability of this amplifier system. The parameter space approach has been used to determine system parameters in the negative impedance circuit such that the stability of the amplifier system can be guaranteed in a certain region represented by those parameters. The simulation results have demonstrated that stable circuit behavior for the amplifier can be achieved.
{"title":"Stability analysis of an amplifier with negative impedance compensation","authors":"R. Wu, Chen Wang","doi":"10.1109/MWSCAS.2008.4616921","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616921","url":null,"abstract":"A novel amplifier design technique based on negative impedance compensation has been proposed in our recent paper. In this paper, we investigate the stability of this amplifier system. The parameter space approach has been used to determine system parameters in the negative impedance circuit such that the stability of the amplifier system can be guaranteed in a certain region represented by those parameters. The simulation results have demonstrated that stable circuit behavior for the amplifier can be achieved.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122470420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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