Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616824
H. Cao, R. Weber
We present a method for characterizing three-port (RF, IF, image) conversion scattering parameters for microwave mixers. A diplexer is used to separate the image signal from the IF signal. The de-embedding and un-terminating methods have been used for calculating the scattering-parameter matrix. The conversion scattering parameters have been obtained at different local-oscillator (LO) power levels for a commercial microwave mixer. We also show how the termination of the image signal will affect the conversion loss of the microwave mixer.
{"title":"Three-port conversion scattering parameters characterization for microwave mixers","authors":"H. Cao, R. Weber","doi":"10.1109/MWSCAS.2008.4616824","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616824","url":null,"abstract":"We present a method for characterizing three-port (RF, IF, image) conversion scattering parameters for microwave mixers. A diplexer is used to separate the image signal from the IF signal. The de-embedding and un-terminating methods have been used for calculating the scattering-parameter matrix. The conversion scattering parameters have been obtained at different local-oscillator (LO) power levels for a commercial microwave mixer. We also show how the termination of the image signal will affect the conversion loss of the microwave mixer.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131913440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616875
B. Degnan, P. Hasler, C. Twigg
Floating-gate transistors that have contacts to the lowest metal to the polysilicon floating-gate were fabricated to determine if the lowest metal flow alone could normalize charge across multiple floating gates. The metal contacts did not normalize charge for different numbers of contacts to polysilicon; however, a decreased variance of trapped charge was found when compared to polysilicon floating-gates that have no contacts to lowestmetal. The charge leakage from the floating-gate was negligible after one year, suggesting that layout may play a critical factor in leakage.
{"title":"Trapped charge characterization and removal on floating-gate transistors","authors":"B. Degnan, P. Hasler, C. Twigg","doi":"10.1109/MWSCAS.2008.4616875","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616875","url":null,"abstract":"Floating-gate transistors that have contacts to the lowest metal to the polysilicon floating-gate were fabricated to determine if the lowest metal flow alone could normalize charge across multiple floating gates. The metal contacts did not normalize charge for different numbers of contacts to polysilicon; however, a decreased variance of trapped charge was found when compared to polysilicon floating-gates that have no contacts to lowestmetal. The charge leakage from the floating-gate was negligible after one year, suggesting that layout may play a critical factor in leakage.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133224041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1049/iet-cds.2008.0324
An Hu, F. Yuan
This paper proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signaling. The proposed current-mode receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values for convenient phase comparison. The feedback at the front-end of the receiver minimizes the dependence of the input impedance of the receiver on the direction of the channel current so that signal-dependent impedance mismatch is minimized. Inter-signal timing skew is compensated by inserting a delay line for each channel so that a single sampling clock is needed for all channels. A 2-bit 1 Gbytes/s parallel link has been implemented in UMC-0.13 mum 1.2V CMOS technology and analyzed using SpectreRF with BSIM3V3 device models. Simulation results show that inter-signal timing skews can be effectively compensated using the proposed deskewing scheme.
{"title":"Inter-signal timing skew compensation of parallel links with current-mode incremental signaling","authors":"An Hu, F. Yuan","doi":"10.1049/iet-cds.2008.0324","DOIUrl":"https://doi.org/10.1049/iet-cds.2008.0324","url":null,"abstract":"This paper proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signaling. The proposed current-mode receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values for convenient phase comparison. The feedback at the front-end of the receiver minimizes the dependence of the input impedance of the receiver on the direction of the channel current so that signal-dependent impedance mismatch is minimized. Inter-signal timing skew is compensated by inserting a delay line for each channel so that a single sampling clock is needed for all channels. A 2-bit 1 Gbytes/s parallel link has been implemented in UMC-0.13 mum 1.2V CMOS technology and analyzed using SpectreRF with BSIM3V3 device models. Simulation results show that inter-signal timing skews can be effectively compensated using the proposed deskewing scheme.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117162085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616955
C. Shahnaz, W. Zhu, M. Ahmad
A new method based on temporal matching is presented in this paper for pitch determination from noisy speech signals. At first, a variable-length average magnitude sum function (VLAMSF) that exhibits a periodicity similar to the pitch period of the voiced speech, has been proposed. We argue that the discrete cosine transform (DCT) power spectrum of the VLAMSF is capable of revealing an estimate of a pitch-harmonic (PH) more accurately even in a heavy noisy scenario. Then, exploiting the extracted PH, we formulate an impulse train with a variable-period that is used to temporally match the periodicity of the proposed VLAMSF for pitch determination. It has been shown through extensive simulations using the Keele database that our new approach consistently outperforms the other existing methods especially at low signal-to-noise ratios (SNRs).
{"title":"A temporal matching method for pitch determination from noisy speech signals","authors":"C. Shahnaz, W. Zhu, M. Ahmad","doi":"10.1109/MWSCAS.2008.4616955","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616955","url":null,"abstract":"A new method based on temporal matching is presented in this paper for pitch determination from noisy speech signals. At first, a variable-length average magnitude sum function (VLAMSF) that exhibits a periodicity similar to the pitch period of the voiced speech, has been proposed. We argue that the discrete cosine transform (DCT) power spectrum of the VLAMSF is capable of revealing an estimate of a pitch-harmonic (PH) more accurately even in a heavy noisy scenario. Then, exploiting the extracted PH, we formulate an impulse train with a variable-period that is used to temporally match the periodicity of the proposed VLAMSF for pitch determination. It has been shown through extensive simulations using the Keele database that our new approach consistently outperforms the other existing methods especially at low signal-to-noise ratios (SNRs).","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121167217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616757
B. Leung
Comparisons of phase noise models based on time domain models and frequency domain models are presented. It is shown that time domain approach by this author, based on conventional time scaling and that incorporates multiple threshold crossing phenomenon, reflects the physical mechanism better. Moreover its phase noise expression does not blow up as offset frequency goes to zero. Finally compared to frequency domain methods the transient simulations needed to obtain the necessary parameters are simpler.
{"title":"Comparisons of phase noise models of CMOS ring oscillators","authors":"B. Leung","doi":"10.1109/MWSCAS.2008.4616757","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616757","url":null,"abstract":"Comparisons of phase noise models based on time domain models and frequency domain models are presented. It is shown that time domain approach by this author, based on conventional time scaling and that incorporates multiple threshold crossing phenomenon, reflects the physical mechanism better. Moreover its phase noise expression does not blow up as offset frequency goes to zero. Finally compared to frequency domain methods the transient simulations needed to obtain the necessary parameters are simpler.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114964365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616863
H. Ande, P. Busa, M. Balasubramanian, K. Campbell, R. J. Baker
A new approach to developing, fabricating, and testing chalcogenide-based multi-state phase-change nonvolatile memory (NVM) is presented. A test chip is fabricated through the MOSIS service. Then post processing, in the Boise State University lab, is performed on the chip to add the chalcogenide material that forms the NVM. Each memory bit consists of an NMOS access transistor and the chalcogenide material placed between the metal3 of the test chip, connected to the access device, and a common, to all memory bits, electrode. This paper describes the design of the memory bit and of the test structures used for reliability and radiation testing. Fabrication and post-processing of the memory are also discussed.
{"title":"A new approach to the design, fabrication, and testing of chalcogenide-based multi-state phase-change nonvolatile memory","authors":"H. Ande, P. Busa, M. Balasubramanian, K. Campbell, R. J. Baker","doi":"10.1109/MWSCAS.2008.4616863","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616863","url":null,"abstract":"A new approach to developing, fabricating, and testing chalcogenide-based multi-state phase-change nonvolatile memory (NVM) is presented. A test chip is fabricated through the MOSIS service. Then post processing, in the Boise State University lab, is performed on the chip to add the chalcogenide material that forms the NVM. Each memory bit consists of an NMOS access transistor and the chalcogenide material placed between the metal3 of the test chip, connected to the access device, and a common, to all memory bits, electrode. This paper describes the design of the memory bit and of the test structures used for reliability and radiation testing. Fabrication and post-processing of the memory are also discussed.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115242723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616895
Y. Haga, I. Kale
This paper presents a new design approach which can convert any CMOS operational amplifiers to have rail-to-rail common-mode input capability by utilizing few additional hardware elements. The proposed circuit can operate over a wide range of supply voltages from 1-volt to the maximum allowed for the CMOS process, without degrading the ac and dc performances of the amplifier in question over the rail-to-rail operation.
{"title":"Achieving rail-to-rail input operation using level-shift multiplexing technique for all CMOS op-amps","authors":"Y. Haga, I. Kale","doi":"10.1109/MWSCAS.2008.4616895","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616895","url":null,"abstract":"This paper presents a new design approach which can convert any CMOS operational amplifiers to have rail-to-rail common-mode input capability by utilizing few additional hardware elements. The proposed circuit can operate over a wide range of supply voltages from 1-volt to the maximum allowed for the CMOS process, without degrading the ac and dc performances of the amplifier in question over the rail-to-rail operation.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"1232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123354887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616737
Hugang Han, Bo Mo, Fenghui Yao
In general, the state feedback control gain can be obtained by solving certain linear matrix inequalities (LMIs) when using the Takagi-Sugeno (T-S) fuzzy model to develop a control system. In this paper, the reconstruction error between the real system to be controlled and its T-S fuzzy model, which consists of parameter uncertainties and external disturbance, is considered. As a result, we arrive at a new T-S fuzzy controller that has two parts: one is obtained by solving certain LMIs (fixed part) and another one is acquired by an adaptive law (variable part). The proposed controller can guarantee the control state to converge and uniformly bounded while maintaining all the signals involved stable.
{"title":"T-S fuzzy controller for a class of uncertain nonlinear systems","authors":"Hugang Han, Bo Mo, Fenghui Yao","doi":"10.1109/MWSCAS.2008.4616737","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616737","url":null,"abstract":"In general, the state feedback control gain can be obtained by solving certain linear matrix inequalities (LMIs) when using the Takagi-Sugeno (T-S) fuzzy model to develop a control system. In this paper, the reconstruction error between the real system to be controlled and its T-S fuzzy model, which consists of parameter uncertainties and external disturbance, is considered. As a result, we arrive at a new T-S fuzzy controller that has two parts: one is obtained by solving certain LMIs (fixed part) and another one is acquired by an adaptive law (variable part). The proposed controller can guarantee the control state to converge and uniformly bounded while maintaining all the signals involved stable.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123611224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616784
J. Gray, R. Robucci, P. Hasler
We present the methodology for implementing a computational memory element using a floating-gate pFET model suitable for the design and simulation of analog systems. A first-order physically inspired model of pFET hot-election injection is implemented in Verilog-A, fit to experimental data, and then applied to a proposed floating-gate circuit. The model parameters are fit directly to the drain current data from a measured floating-gate pFET, eliminating the need for estimating or measuring gate injection current. The model is used to examine the programming transient response of a proposed analog computational vector-matrix multiplier cell. The circuit eliminates power-supply ramping by using a negative voltage, avoids complex characterization by linearized the injection current, and reduces off-chip interaction with on-chip feedback. We discuss how our model and approach represent a pathway for accessible floating-gate design, simulation, and implementation.
{"title":"The design and simulation model of an analog floating-gate computational element for use in large-scale analog reconfigurable systems","authors":"J. Gray, R. Robucci, P. Hasler","doi":"10.1109/MWSCAS.2008.4616784","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616784","url":null,"abstract":"We present the methodology for implementing a computational memory element using a floating-gate pFET model suitable for the design and simulation of analog systems. A first-order physically inspired model of pFET hot-election injection is implemented in Verilog-A, fit to experimental data, and then applied to a proposed floating-gate circuit. The model parameters are fit directly to the drain current data from a measured floating-gate pFET, eliminating the need for estimating or measuring gate injection current. The model is used to examine the programming transient response of a proposed analog computational vector-matrix multiplier cell. The circuit eliminates power-supply ramping by using a negative voltage, avoids complex characterization by linearized the injection current, and reduces off-chip interaction with on-chip feedback. We discuss how our model and approach represent a pathway for accessible floating-gate design, simulation, and implementation.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123898341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616894
E. Azab, S. Mahmoud
A wide input voltage range differential difference operational floating amplifier is introduced. The proposed realization is based on the cascading connection of a differential difference transconductor (DDT) and a differential input balanced output current op-amp (DIBO). The proposed DDT is based on differential transconductor stage with rail-to-rail differential input voltage swing. The DIBO current op-amp consists of high gain transresistance amplification stage and high CMRR single input balanced output transconductor stage. The new DDOFA block has 74.17 MHz unity gain BW, DC gain of 57 dBmA/V and CMRR of 85.32 dB and rail-to-rail differential input voltage swing using CMOS 0.25 mum technology model.
{"title":"New CMOS realization of the differential difference operational floating amplifier with wide input voltage range","authors":"E. Azab, S. Mahmoud","doi":"10.1109/MWSCAS.2008.4616894","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616894","url":null,"abstract":"A wide input voltage range differential difference operational floating amplifier is introduced. The proposed realization is based on the cascading connection of a differential difference transconductor (DDT) and a differential input balanced output current op-amp (DIBO). The proposed DDT is based on differential transconductor stage with rail-to-rail differential input voltage swing. The DIBO current op-amp consists of high gain transresistance amplification stage and high CMRR single input balanced output transconductor stage. The new DDOFA block has 74.17 MHz unity gain BW, DC gain of 57 dBmA/V and CMRR of 85.32 dB and rail-to-rail differential input voltage swing using CMOS 0.25 mum technology model.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123957239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：