Pub Date : 2016-07-28DOI: 10.1109/MICROCOM.2016.7522410
M. Sinha, R. Mahapatra, B. Mondal, R. Ghosh
ZnO Microrods with average diameter of 350 nm were synthesized on FTO substrate using a hydrothermal reaction process at a low temperature of 90 °C. Experimental results reveal an ultra-high sensitivity about 568% to 100 ppm ethanol gas, a fast response of 1.77s and a recovery of 65.65s to ethanol.
{"title":"High sensitivity of gas sensing properties of ZnO microrods on FTO substrate","authors":"M. Sinha, R. Mahapatra, B. Mondal, R. Ghosh","doi":"10.1109/MICROCOM.2016.7522410","DOIUrl":"https://doi.org/10.1109/MICROCOM.2016.7522410","url":null,"abstract":"ZnO Microrods with average diameter of 350 nm were synthesized on FTO substrate using a hydrothermal reaction process at a low temperature of 90 °C. Experimental results reveal an ultra-high sensitivity about 568% to 100 ppm ethanol gas, a fast response of 1.77s and a recovery of 65.65s to ethanol.","PeriodicalId":118902,"journal":{"name":"2016 International Conference on Microelectronics, Computing and Communications (MicroCom)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128584139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-01-01DOI: 10.1109/MICROCOM.2016.7522571
P. Chanda, P. Subbarao
Steam boiler provides appropriate quality and quantity of steam to the turbine for power generation. In drum type boiler, water and steam flow in the drum is controlled in such a way that the water level in the drum is maintained fairly at a preset value. While very low water level in the drum may lead to starvation and explosion of boiler, too high level may cause carryover of water particle and damages the super-heaters. Therefore Drum level is an important parameter for safe operation of a boiler. Drum level in a drum type boiler is influenced by number of factors, such as sudden change in load demand and changed in heat input to the boiler etc. During Boiler Feed Pump (BFP) runback, the boiler steam generation is reduced through fuel cut off while steam out flow to the turbine is controlled by pressure controller. Under such circumstance, due to mismatch between steam out and feed water in, it becomes difficult in maintaining water level in the drum to its pre set value. This paper has suggested an innovative drum level control by adopting the concept of related rate variation. The related rate module uniquely co-relates two independent time varying parameters namely steam flow and feed water flow in real time and accordingly apply correction of steam flow to match steam and water flow during BFP runback. Simulation result shows real time correction of steam flow maintains drum level within its safe operating limit during BFP runback. The innovative related rate module can be used as a control block in the future boiler controls for coordination between many parameters varying independently with respect to time.
{"title":"Controlling drum level of a utility boiler during boiler feed pump runback using related rate concept","authors":"P. Chanda, P. Subbarao","doi":"10.1109/MICROCOM.2016.7522571","DOIUrl":"https://doi.org/10.1109/MICROCOM.2016.7522571","url":null,"abstract":"Steam boiler provides appropriate quality and quantity of steam to the turbine for power generation. In drum type boiler, water and steam flow in the drum is controlled in such a way that the water level in the drum is maintained fairly at a preset value. While very low water level in the drum may lead to starvation and explosion of boiler, too high level may cause carryover of water particle and damages the super-heaters. Therefore Drum level is an important parameter for safe operation of a boiler. Drum level in a drum type boiler is influenced by number of factors, such as sudden change in load demand and changed in heat input to the boiler etc. During Boiler Feed Pump (BFP) runback, the boiler steam generation is reduced through fuel cut off while steam out flow to the turbine is controlled by pressure controller. Under such circumstance, due to mismatch between steam out and feed water in, it becomes difficult in maintaining water level in the drum to its pre set value. This paper has suggested an innovative drum level control by adopting the concept of related rate variation. The related rate module uniquely co-relates two independent time varying parameters namely steam flow and feed water flow in real time and accordingly apply correction of steam flow to match steam and water flow during BFP runback. Simulation result shows real time correction of steam flow maintains drum level within its safe operating limit during BFP runback. The innovative related rate module can be used as a control block in the future boiler controls for coordination between many parameters varying independently with respect to time.","PeriodicalId":118902,"journal":{"name":"2016 International Conference on Microelectronics, Computing and Communications (MicroCom)","volume":"17 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131747555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-01-01DOI: 10.1109/MICROCOM.2016.7522456
A. Mal, Amit Krishna Dwivedi, A. Islam
This paper makes a critical investigation of six programmable delay-producing elements used in present day technology. In signal processing applications, these circuits are capable of incorporating a fixed duration of delay, while keeping the signal integrity intact as well. This comparative study among the six delay-producing elements aids the design engineers in selecting an appropriate delay generating element as per the applications desired. Performance estimation of these delay circuits has been performed at the transistor level. Individual waveforms compiled in the corresponding sections of this paper have been obtained from the extensive simulations executed on SPICE using Predictive Technology Model (PTM) @ 16-nm technology. Finally, significance and future scope of work in this area has been discussed in a nutshell and concluding remarks have been drawn based on the observations made.
{"title":"A comparative analysis of various programmable delay elements using predictive technology model","authors":"A. Mal, Amit Krishna Dwivedi, A. Islam","doi":"10.1109/MICROCOM.2016.7522456","DOIUrl":"https://doi.org/10.1109/MICROCOM.2016.7522456","url":null,"abstract":"This paper makes a critical investigation of six programmable delay-producing elements used in present day technology. In signal processing applications, these circuits are capable of incorporating a fixed duration of delay, while keeping the signal integrity intact as well. This comparative study among the six delay-producing elements aids the design engineers in selecting an appropriate delay generating element as per the applications desired. Performance estimation of these delay circuits has been performed at the transistor level. Individual waveforms compiled in the corresponding sections of this paper have been obtained from the extensive simulations executed on SPICE using Predictive Technology Model (PTM) @ 16-nm technology. Finally, significance and future scope of work in this area has been discussed in a nutshell and concluding remarks have been drawn based on the observations made.","PeriodicalId":118902,"journal":{"name":"2016 International Conference on Microelectronics, Computing and Communications (MicroCom)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116943691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/MICROCOM.2016.7522504
A. Prajapati, P. Dey, T. Das
A single quantum well Light Emitting Diode (LED) is designed from two different semiconductors and the main advantages of quantum well structure are high radiative efficiency, surface recombination etc. We have designed the device in order to observe the impact of mole fraction on power spectral density at different wave length by keeping the anode voltage fixed. A nearly lattice matched AlGaN-InGaN-GaN double hetero-structure semiconductor device has been simulated to get the maximum power spectral density at a particular wave length. For the anode voltage of 5V, at a mole fraction of x= 0.24 for Indium in InxGa1-xN, it is observed that a power spectral density of 9.31 W/cm-eV is obtained at a wave length of 452 nm. Observations were made for mole fraction varying from x=0.01 to 0.30.
{"title":"The effect of mole-fraction on power spectral density of single quantum well based InxGa1-xN/GaN blue light emitting diode","authors":"A. Prajapati, P. Dey, T. Das","doi":"10.1109/MICROCOM.2016.7522504","DOIUrl":"https://doi.org/10.1109/MICROCOM.2016.7522504","url":null,"abstract":"A single quantum well Light Emitting Diode (LED) is designed from two different semiconductors and the main advantages of quantum well structure are high radiative efficiency, surface recombination etc. We have designed the device in order to observe the impact of mole fraction on power spectral density at different wave length by keeping the anode voltage fixed. A nearly lattice matched AlGaN-InGaN-GaN double hetero-structure semiconductor device has been simulated to get the maximum power spectral density at a particular wave length. For the anode voltage of 5V, at a mole fraction of x= 0.24 for Indium in InxGa1-xN, it is observed that a power spectral density of 9.31 W/cm-eV is obtained at a wave length of 452 nm. Observations were made for mole fraction varying from x=0.01 to 0.30.","PeriodicalId":118902,"journal":{"name":"2016 International Conference on Microelectronics, Computing and Communications (MicroCom)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123307773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/MICROCOM.2016.7522603
Subodh Kanta Barik, K. Jaladi
The electrical machines with increased number of phases are being used in industry because of their reliableness, firmness, and safeness comparing with 3-phase induction machines and direct current machines. This paper compares the performance of a Five phase Induction Motor with different conduction modes such as 180°, 144°, 153°, and 171° in five phase voltage source Inverter. A comparison is made between characteristics of a five phase Induction motor with different loadings from no load to full load. The system is simulated considering an inverter fed to a mathematical model of five phase Induction motor. The advantages of multiphase induction motor have been analyzed and results of performance characteristics of a five phase induction motor are demonstrated.
{"title":"A comparative analysis of different conduction modes in VSI with five phase induction motor","authors":"Subodh Kanta Barik, K. Jaladi","doi":"10.1109/MICROCOM.2016.7522603","DOIUrl":"https://doi.org/10.1109/MICROCOM.2016.7522603","url":null,"abstract":"The electrical machines with increased number of phases are being used in industry because of their reliableness, firmness, and safeness comparing with 3-phase induction machines and direct current machines. This paper compares the performance of a Five phase Induction Motor with different conduction modes such as 180°, 144°, 153°, and 171° in five phase voltage source Inverter. A comparison is made between characteristics of a five phase Induction motor with different loadings from no load to full load. The system is simulated considering an inverter fed to a mathematical model of five phase Induction motor. The advantages of multiphase induction motor have been analyzed and results of performance characteristics of a five phase induction motor are demonstrated.","PeriodicalId":118902,"journal":{"name":"2016 International Conference on Microelectronics, Computing and Communications (MicroCom)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122829891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/MICROCOM.2016.7522488
D. Mukherjee, S. Mukhopadhyay, G. P. Biswas
This paper presents a parallel algorithm and its hardware architecture for implementing 2-D gray-scale morphological operations namely dilation and erosion using rectangular flat top structuring elements. The proposed architecture supports parallel extension whereby throughput and processing frame rate is enhanced. The architecture is fully generic and runtime programmable with respect to image size and structuring elements size respectively. The main advantage of the architecture is its low latency, lower internal memory requirements, higher processing frame rate and throughput which makes it more amenable to real time applications. Additionally, it makes use of stream processing which eliminates the need for buffering image data, whereby memory overhead is minimized. The architecture has been synthesized using Xilinx Design Suite 14.2 ISE and prototyped on Virtex 5 FPGA Board and verified using xilinx ISIM Simulator. The proposed architecture has been tested for images of varied gray-scale geometric dimension and the results shows satisfactory performance.
本文提出了一种利用矩形平顶结构元实现二维灰度形态运算即扩张和侵蚀的并行算法及其硬件结构。提出的架构支持并行扩展，从而提高吞吐量和处理帧速率。在图像大小和结构元素大小方面，该体系结构是完全通用和运行时可编程的。该架构的主要优点是它的低延迟，更低的内存需求，更高的处理帧率和吞吐量，这使得它更适合实时应用。此外，它利用流处理消除了缓冲图像数据的需要，从而使内存开销最小化。该架构使用Xilinx Design Suite 14.2 ISE进行了综合，并在Virtex 5 FPGA板上进行了原型设计，并使用Xilinx ISIM模拟器进行了验证。对不同灰度几何尺寸的图像进行了测试，结果令人满意。
{"title":"FPGA based parallel implementation of morphological filters","authors":"D. Mukherjee, S. Mukhopadhyay, G. P. Biswas","doi":"10.1109/MICROCOM.2016.7522488","DOIUrl":"https://doi.org/10.1109/MICROCOM.2016.7522488","url":null,"abstract":"This paper presents a parallel algorithm and its hardware architecture for implementing 2-D gray-scale morphological operations namely dilation and erosion using rectangular flat top structuring elements. The proposed architecture supports parallel extension whereby throughput and processing frame rate is enhanced. The architecture is fully generic and runtime programmable with respect to image size and structuring elements size respectively. The main advantage of the architecture is its low latency, lower internal memory requirements, higher processing frame rate and throughput which makes it more amenable to real time applications. Additionally, it makes use of stream processing which eliminates the need for buffering image data, whereby memory overhead is minimized. The architecture has been synthesized using Xilinx Design Suite 14.2 ISE and prototyped on Virtex 5 FPGA Board and verified using xilinx ISIM Simulator. The proposed architecture has been tested for images of varied gray-scale geometric dimension and the results shows satisfactory performance.","PeriodicalId":118902,"journal":{"name":"2016 International Conference on Microelectronics, Computing and Communications (MicroCom)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116725436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/MICROCOM.2016.7522531
S. Garg, A. Garg, S. Bansal, A. Chaudhary, A. Singh, S. R. Kasjoo
In this paper, 2D computer simulations based on Silvaco TCAD (Atlas) have been employed to showcase the effect of different dielectric materials on the I-V characteristics of a novel nanoelectronic diode fabricated out of 2DEG materials such as GaN and InGaAs. Being a potential terahertz detector, it is further demonstrated that how these materials affect the parasitic and conductive properties of the devices at very high frequencies.
{"title":"Effect of filling dielectric in etched trenches of novel unipolar nanodiode","authors":"S. Garg, A. Garg, S. Bansal, A. Chaudhary, A. Singh, S. R. Kasjoo","doi":"10.1109/MICROCOM.2016.7522531","DOIUrl":"https://doi.org/10.1109/MICROCOM.2016.7522531","url":null,"abstract":"In this paper, 2D computer simulations based on Silvaco TCAD (Atlas) have been employed to showcase the effect of different dielectric materials on the I-V characteristics of a novel nanoelectronic diode fabricated out of 2DEG materials such as GaN and InGaAs. Being a potential terahertz detector, it is further demonstrated that how these materials affect the parasitic and conductive properties of the devices at very high frequencies.","PeriodicalId":118902,"journal":{"name":"2016 International Conference on Microelectronics, Computing and Communications (MicroCom)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129498623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/MICROCOM.2016.7522438
Namrata Yadav, Abhishek Pandey, V. Nath
This paper is enunciated a LNA with high gain and minimum noise performance for Global Positioning System (GPS) application. The CMOS Low Noise amplifier implementation is designed and simulated via cadence using UMC 90 nm library. The topology is single ended LNAs designed which uses cascaded transistor for isolation; the common source transistor is driven by common gate transistor. To have objective for good voltage gain with minimum noise figure, cascoding input matching is done using source degeneration technique. Transistors are operated in sub threshold region. At 1.57 GHz frequency, parameters like power gain, input matching, output matching, isolation, stability are examined by S-parameters. The voltage gain of LNA is 31 dB. The noise figure is 0.533 dB, 1dB compression point is -16.95 dBm and IIP3 is 2.91 dBm. The LNA is having power consumption as 8.7 mW for 1.5 V supply.
{"title":"Design of CMOS low noise amplifier for 1.57GHz","authors":"Namrata Yadav, Abhishek Pandey, V. Nath","doi":"10.1109/MICROCOM.2016.7522438","DOIUrl":"https://doi.org/10.1109/MICROCOM.2016.7522438","url":null,"abstract":"This paper is enunciated a LNA with high gain and minimum noise performance for Global Positioning System (GPS) application. The CMOS Low Noise amplifier implementation is designed and simulated via cadence using UMC 90 nm library. The topology is single ended LNAs designed which uses cascaded transistor for isolation; the common source transistor is driven by common gate transistor. To have objective for good voltage gain with minimum noise figure, cascoding input matching is done using source degeneration technique. Transistors are operated in sub threshold region. At 1.57 GHz frequency, parameters like power gain, input matching, output matching, isolation, stability are examined by S-parameters. The voltage gain of LNA is 31 dB. The noise figure is 0.533 dB, 1dB compression point is -16.95 dBm and IIP3 is 2.91 dBm. The LNA is having power consumption as 8.7 mW for 1.5 V supply.","PeriodicalId":118902,"journal":{"name":"2016 International Conference on Microelectronics, Computing and Communications (MicroCom)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129521307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/MICROCOM.2016.7522462
K. Banerjee, S. K. Paul
This research paper introduces a fully controllable negative inductor and two R-L Immittance simulator using Differential Voltage Current Conveyor (DVCC) and some passive components. One of the immittance simulators is a parallel RL and other is series R and L. All the three simulators use two resistors and one capacitor. Workability of all the simulators are tested by 0.5μm CMOS Technology.
{"title":"Negative inductance and immittance simulators employing differential voltage current conveyor","authors":"K. Banerjee, S. K. Paul","doi":"10.1109/MICROCOM.2016.7522462","DOIUrl":"https://doi.org/10.1109/MICROCOM.2016.7522462","url":null,"abstract":"This research paper introduces a fully controllable negative inductor and two R-L Immittance simulator using Differential Voltage Current Conveyor (DVCC) and some passive components. One of the immittance simulators is a parallel RL and other is series R and L. All the three simulators use two resistors and one capacitor. Workability of all the simulators are tested by 0.5μm CMOS Technology.","PeriodicalId":118902,"journal":{"name":"2016 International Conference on Microelectronics, Computing and Communications (MicroCom)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128734960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/MICROCOM.2016.7522411
S. Pradhan, V. Rai, A. Chakraborty
To solve the serious problem of threshold loss that causes non-full-swing at the out-put of 1-bit full adder, an arrangement in which all the transistors are forced to operate in sub-threshold regime is proposed in this paper. But this will in turn bring additional area and delay overhead. In this work, full swing at the output of 1-bit full adder is retained with reduced area and delay overhead. An additional capacitor working in the differential voltage mode will be replacing the transistor that is used to reduce the threshold loss problem at the output of 9T based full adder as discussed in this paper. Previous works related to this domain concerns about reduction of power of only 1-bit adder. The work targets power and area reduction of 1/4/8/16 bit adders. Proposed adder shows maximum total power saving of 46.87 % and 25.99 % with respect to 8T and 9T adder configurations respectively.
{"title":"Design of high speed and low power full adder in sub-threshold region","authors":"S. Pradhan, V. Rai, A. Chakraborty","doi":"10.1109/MICROCOM.2016.7522411","DOIUrl":"https://doi.org/10.1109/MICROCOM.2016.7522411","url":null,"abstract":"To solve the serious problem of threshold loss that causes non-full-swing at the out-put of 1-bit full adder, an arrangement in which all the transistors are forced to operate in sub-threshold regime is proposed in this paper. But this will in turn bring additional area and delay overhead. In this work, full swing at the output of 1-bit full adder is retained with reduced area and delay overhead. An additional capacitor working in the differential voltage mode will be replacing the transistor that is used to reduce the threshold loss problem at the output of 9T based full adder as discussed in this paper. Previous works related to this domain concerns about reduction of power of only 1-bit adder. The work targets power and area reduction of 1/4/8/16 bit adders. Proposed adder shows maximum total power saving of 46.87 % and 25.99 % with respect to 8T and 9T adder configurations respectively.","PeriodicalId":118902,"journal":{"name":"2016 International Conference on Microelectronics, Computing and Communications (MicroCom)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128986086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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