Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486228
H. Higuchi, Y. Matsunaga
This paper proposes a new implicit algorithm for excluding dominated compatibles. The algorithm utilizes a novel notion of signatures of compatibles to exclude dominated compatibles efficiently. Though this dominance check is weaker than the conventional one, experimental results show that in many cases the number of excluded compatibles is the same as that by class sets. The proposed method computes prime compatibles more efficiently than conventional methods for many tested large ISFSM's.
{"title":"Implicit prime compatible generation for minimizing incompletely specified finite state machines","authors":"H. Higuchi, Y. Matsunaga","doi":"10.1109/ASPDAC.1995.486228","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486228","url":null,"abstract":"This paper proposes a new implicit algorithm for excluding dominated compatibles. The algorithm utilizes a novel notion of signatures of compatibles to exclude dominated compatibles efficiently. Though this dominance check is weaker than the conventional one, experimental results show that in many cases the number of excluded compatibles is the same as that by class sets. The proposed method computes prime compatibles more efficiently than conventional methods for many tested large ISFSM's.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121896689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486194
How-Rern Lin, TingTing Hwang
This paper describes methods for reducing power consumption. We propose using gate sizing technique to reduce power for circuits that have already satisfied the timing constraint. Replacement of gates on noncritical paths with smaller templates is used in reducing the dissipated power of a circuit. We find that not only gates on noncritical paths can be down-sized, but also gates on critical paths can be down-sized. A power reduction algorithm by means of single gate resizing as well as multiple gates resizing will be proposed. In addition, to identify gates to be resized, a path-oriented method in calculating slack time with false path taken into consideration will be also proposed. During the slack time computation, in order to prevent long false path from becoming sensitizable and thus increasing the circuit delay, slack constraint will be set for gales. Results on a set of circuits from MCNC benchmark set demonstrate that our power reduction algorithm can reduce about 10% more power, on the average, than a previously proposed gate sizing algorithm.
{"title":"Power reduction by gate sizing with path-oriented slack calculation","authors":"How-Rern Lin, TingTing Hwang","doi":"10.1109/ASPDAC.1995.486194","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486194","url":null,"abstract":"This paper describes methods for reducing power consumption. We propose using gate sizing technique to reduce power for circuits that have already satisfied the timing constraint. Replacement of gates on noncritical paths with smaller templates is used in reducing the dissipated power of a circuit. We find that not only gates on noncritical paths can be down-sized, but also gates on critical paths can be down-sized. A power reduction algorithm by means of single gate resizing as well as multiple gates resizing will be proposed. In addition, to identify gates to be resized, a path-oriented method in calculating slack time with false path taken into consideration will be also proposed. During the slack time computation, in order to prevent long false path from becoming sensitizable and thus increasing the circuit delay, slack constraint will be set for gales. Results on a set of circuits from MCNC benchmark set demonstrate that our power reduction algorithm can reduce about 10% more power, on the average, than a previously proposed gate sizing algorithm.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"23 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125845966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486200
V. Moshnyaga, F. Ohbayashi, K. Tamaru
Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach for integrated scheduling and interconnect binding of bus-segmented data-paths. Experiments show that the approach provides better results than existing methods and is quite flexible.
{"title":"A scheduling algorithm for synthesis of bus-partitioned architectures","authors":"V. Moshnyaga, F. Ohbayashi, K. Tamaru","doi":"10.1109/ASPDAC.1995.486200","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486200","url":null,"abstract":"Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach for integrated scheduling and interconnect binding of bus-segmented data-paths. Experiments show that the approach provides better results than existing methods and is quite flexible.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129384840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486225
A. Motohara, S. Takeoka, Toshinori Hosokawa, M. Ohta, Yuji Takai, M. Matsumoto, M. Muraoka
An approach to top down design for testability using register-transfer level (RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented.
{"title":"Design for testability using register-transfer level partial scan selection","authors":"A. Motohara, S. Takeoka, Toshinori Hosokawa, M. Ohta, Yuji Takai, M. Matsumoto, M. Muraoka","doi":"10.1109/ASPDAC.1995.486225","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486225","url":null,"abstract":"An approach to top down design for testability using register-transfer level (RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129852724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486219
Jong Tae Lee, Jaemin Kim, Jae-Cheol Son
This paper presents an architectural simulator called VIDEOFLOW software tools for developing programmable DSP chip set for various video codec standards. This DSP chip set consists of the Image Compression Coprocessor (ICC) and Motion Estimation Coprocessor (ICC), which provide an easy solution for implementing the major digital video codec algorithms. The ICC/MEC simulation components are 100 percent bit accurate and closely approximate the timing of the actual chips. In addition, the simulation tool provides users with the ICC/MEC system simulation, debugging, and various performance monitors. This tool can also be used to define and modify the architectural specification for future product line of the ICC and MEC.
{"title":"Architectural simulation for a programmable DSP chip set","authors":"Jong Tae Lee, Jaemin Kim, Jae-Cheol Son","doi":"10.1109/ASPDAC.1995.486219","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486219","url":null,"abstract":"This paper presents an architectural simulator called VIDEOFLOW software tools for developing programmable DSP chip set for various video codec standards. This DSP chip set consists of the Image Compression Coprocessor (ICC) and Motion Estimation Coprocessor (ICC), which provide an easy solution for implementing the major digital video codec algorithms. The ICC/MEC simulation components are 100 percent bit accurate and closely approximate the timing of the actual chips. In addition, the simulation tool provides users with the ICC/MEC system simulation, debugging, and various performance monitors. This tool can also be used to define and modify the architectural specification for future product line of the ICC and MEC.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131969497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486193
W. Shen, Jiing-Yuan Lin, F. Wang
The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power consumption. In this paper, based on the input signal probabilities and transition densities, we propose a set of simple transistor reordering rules for both basic and complex CMOS gates to minimize the transition counts at the internal nodes. The most attractive feature of this approach is that not only the power consumption is reduced efficiently, but also the other performances are not degraded. Experimental results show that this technique typically reduces the power by about 10% in average, but in some cases the improvement is even 35%.
{"title":"Transistor reordering rules for power reduction in CMOS gates","authors":"W. Shen, Jiing-Yuan Lin, F. Wang","doi":"10.1109/ASPDAC.1995.486193","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486193","url":null,"abstract":"The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power consumption. In this paper, based on the input signal probabilities and transition densities, we propose a set of simple transistor reordering rules for both basic and complex CMOS gates to minimize the transition counts at the internal nodes. The most attractive feature of this approach is that not only the power consumption is reduced efficiently, but also the other performances are not degraded. Experimental results show that this technique typically reduces the power by about 10% in average, but in some cases the improvement is even 35%.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127991632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486220
Gyeong-Lyong Park, K. Chang, Jae Seok Kim, K. Kim
We present a system-level verification methodology which is used to verify the design of CDMA (Code Division Multiple Access) modem ASIC. To make the system-level verification feasible, the models for modulator of base station, fading channel and AGC loop were developed under the C environment. Behavioral modeling of the microcontroller was also carried out using VHDL to provide the ASIC with realistic input data, and the netlist of CDMA modem ASIC is loaded on to a hardware accelerator, which is interfaced with a VHDL simulator. Finally, simulation was performed by executing an actual CDMA call processing software. This method was proved to be effective in both discovering in advance malfunctions of ASIC when embedded in the system and reducing simulation time by a factor of as much as 20 in the case of gate-level simulation. The designed ASIC which consists of 90,000 gates and 29K SRAMs is now successfully working in the real mobile-station on its first fab-out.
{"title":"System-level verification of CDMA modem ASIC","authors":"Gyeong-Lyong Park, K. Chang, Jae Seok Kim, K. Kim","doi":"10.1109/ASPDAC.1995.486220","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486220","url":null,"abstract":"We present a system-level verification methodology which is used to verify the design of CDMA (Code Division Multiple Access) modem ASIC. To make the system-level verification feasible, the models for modulator of base station, fading channel and AGC loop were developed under the C environment. Behavioral modeling of the microcontroller was also carried out using VHDL to provide the ASIC with realistic input data, and the netlist of CDMA modem ASIC is loaded on to a hardware accelerator, which is interfaced with a VHDL simulator. Finally, simulation was performed by executing an actual CDMA call processing software. This method was proved to be effective in both discovering in advance malfunctions of ASIC when embedded in the system and reducing simulation time by a factor of as much as 20 in the case of gate-level simulation. The designed ASIC which consists of 90,000 gates and 29K SRAMs is now successfully working in the real mobile-station on its first fab-out.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131319848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486207
Wen-Jong Fang, A. Wu, Tsing-Gen Lee
In this paper, we present EMPAR, an interactive synthesis environment for hardware emulations. EMPAR provides an open-ended design environment for the development of hardware emulators, which is capable of supporting: (1) a variety of EM architectures (2) a variety of EM synthesis algorithms, (3) interactive control by the user, and (4) design quality analysis. An X-window based graphical user interface has been developed to support a variety of interactive design tasks. The key features in EMPAR are: (1) it is open-ended so that arbitrary algorithms and tools can be built on top of it and (2) it is fully interactive and leaves the control to the designer. EMPAR can be used as a design environment for existing hardware emulators as well as a test bed for the evaluation and development of new hardware-emulator architectures and synthesis algorithms.
{"title":"EMPAR: an interactive synthesis environment for hardware emulations","authors":"Wen-Jong Fang, A. Wu, Tsing-Gen Lee","doi":"10.1109/ASPDAC.1995.486207","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486207","url":null,"abstract":"In this paper, we present EMPAR, an interactive synthesis environment for hardware emulations. EMPAR provides an open-ended design environment for the development of hardware emulators, which is capable of supporting: (1) a variety of EM architectures (2) a variety of EM synthesis algorithms, (3) interactive control by the user, and (4) design quality analysis. An X-window based graphical user interface has been developed to support a variety of interactive design tasks. The key features in EMPAR are: (1) it is open-ended so that arbitrary algorithms and tools can be built on top of it and (2) it is fully interactive and leaves the control to the designer. EMPAR can be used as a design environment for existing hardware emulators as well as a test bed for the evaluation and development of new hardware-emulator architectures and synthesis algorithms.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126321535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486244
R. Drechsler, B. Becker
In many applications of Computer Aided Design (CAD) of Integrated Circuits (ICs) the problems that have to be solved are NP-hard. Thus, exact algorithms are only applicable to small problem instances and many authors have presented heuristics to obtain solutions (non-optimal in general) for larger instances of these hard problems. In this paper we present a model for Genetic Algorithms (GA) to learn heuristics starting from a given set of basic operations. The difference to other previous applications of GAs in CAD of ICs is that the GA does not solve the problem directly. Rather, it develops strategies for solving the problem. To demonstrate the efficiency of our approach experimental results for a specific problem are presented.
{"title":"Learning heuristics by genetic algorithms","authors":"R. Drechsler, B. Becker","doi":"10.1109/ASPDAC.1995.486244","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486244","url":null,"abstract":"In many applications of Computer Aided Design (CAD) of Integrated Circuits (ICs) the problems that have to be solved are NP-hard. Thus, exact algorithms are only applicable to small problem instances and many authors have presented heuristics to obtain solutions (non-optimal in general) for larger instances of these hard problems. In this paper we present a model for Genetic Algorithms (GA) to learn heuristics starting from a given set of basic operations. The difference to other previous applications of GAs in CAD of ICs is that the GA does not solve the problem directly. Rather, it develops strategies for solving the problem. To demonstrate the efficiency of our approach experimental results for a specific problem are presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132596924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486222
Jin-Tai Yan
In this paper, a region definition and ordering assignment (RDAOA) algorithm for minimizing the number of switchboxes is proposed. The time complexity of the algorithm is proved to be in O(n) time, where n is the number of line segments in a given floorplan graph. Finally, several examples have been tested on the proposed algorithm and other published algorithms, and the experimental results show that our algorithm defines fewer switchboxes than other algorithms.
{"title":"Region definition and ordering assignment with the minimization of the number of switchboxes","authors":"Jin-Tai Yan","doi":"10.1109/ASPDAC.1995.486222","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486222","url":null,"abstract":"In this paper, a region definition and ordering assignment (RDAOA) algorithm for minimizing the number of switchboxes is proposed. The time complexity of the algorithm is proved to be in O(n) time, where n is the number of line segments in a given floorplan graph. Finally, several examples have been tested on the proposed algorithm and other published algorithms, and the experimental results show that our algorithm defines fewer switchboxes than other algorithms.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"10 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132238239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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