Reducing total power consumption in high performance microprocessors can be achieved by limiting the amount of logic involved in decoding, scheduling and executing each instruction. One of the solutions to this problem involves the use of a microarchitecture based on an Execution Cache (EC) whose role is to cache already done work for later reuse. In this paper, we explore the design space for such a microarchitecture, looking at how the cache size, associativity and replacement algorithm affect the overall performance and power efficiency. We also look at the scalability of this solution across next process generations, evaluating the energy efficiency of such caching mechanisms in the presence of increasing leakage power. Over a spectrum of SPEC2000 benchmarks, an average of 35% energy reduction is achieved for technologies ranging from 130nm to 90nm and 65nm, at the expense of a negligible performance hit.
{"title":"Impact of technology scaling on energy aware execution cache-based microarchitectures","authors":"Emil Talpes, Diana Marculescu","doi":"10.1145/1013235.1013253","DOIUrl":"https://doi.org/10.1145/1013235.1013253","url":null,"abstract":"Reducing total power consumption in high performance microprocessors can be achieved by limiting the amount of logic involved in decoding, scheduling and executing each instruction. One of the solutions to this problem involves the use of a microarchitecture based on an Execution Cache (EC) whose role is to cache already done work for later reuse. In this paper, we explore the design space for such a microarchitecture, looking at how the cache size, associativity and replacement algorithm affect the overall performance and power efficiency. We also look at the scalability of this solution across next process generations, evaluating the energy efficiency of such caching mechanisms in the presence of increasing leakage power. Over a spectrum of SPEC2000 benchmarks, an average of 35% energy reduction is achieved for technologies ranging from 130nm to 90nm and 65nm, at the expense of a negligible performance hit.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133012950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this framework are compared to BSlM results and are found to he more accurate in comparison to those obtained from existing statistical models. Using this framework, a quantitative analysis of the relative sensitivities of subthreshold leakage to P-T-V variations has been presented. For the first time, the effects of die-to-die channel length and temperature variations on subthreshold leakage are studied in combination with all within-die variations. It has been shown that for accurate estimation of subthreshold leakage, it is important to consider die-to-die temperature variations which can significantly increase the leakage power due to electrothermal couplings between power and temperature. Furthermore, the full-chip leakage power distribution arising due to both within-die and die-to-die P-T-V is calculated, which is subsequently used to estimate the leakage constrained yield under the impact of these variations. The calculations show that the yield is significantly lowered under the impact of within-die and die-to-die process and temperature variations.
{"title":"Subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations","authors":"Songqing Zhang, V. Wason, K. Banerjee","doi":"10.1145/1013235.1013278","DOIUrl":"https://doi.org/10.1145/1013235.1013278","url":null,"abstract":"This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this framework are compared to BSlM results and are found to he more accurate in comparison to those obtained from existing statistical models. Using this framework, a quantitative analysis of the relative sensitivities of subthreshold leakage to P-T-V variations has been presented. For the first time, the effects of die-to-die channel length and temperature variations on subthreshold leakage are studied in combination with all within-die variations. It has been shown that for accurate estimation of subthreshold leakage, it is important to consider die-to-die temperature variations which can significantly increase the leakage power due to electrothermal couplings between power and temperature. Furthermore, the full-chip leakage power distribution arising due to both within-die and die-to-die P-T-V is calculated, which is subsequently used to estimate the leakage constrained yield under the impact of these variations. The calculations show that the yield is significantly lowered under the impact of within-die and die-to-die process and temperature variations.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114319487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min
For low-cost RFID systems, the design of passive tags is a key issue in anti-collision protocols where lower power consumption allows a longer working distance between tags and the reader. In this paper, we look at anti-collision protocols in tags' processing for their power optimization. We propose a new criterion, which takes into account both energy consumption and time complexity, to evaluate anti-collision protocols. An improved protocol is also presented for power savings.
{"title":"Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems","authors":"F. Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min","doi":"10.1145/1013235.1013321","DOIUrl":"https://doi.org/10.1145/1013235.1013321","url":null,"abstract":"For low-cost RFID systems, the design of passive tags is a key issue in anti-collision protocols where lower power consumption allows a longer working distance between tags and the reader. In this paper, we look at anti-collision protocols in tags' processing for their power optimization. We propose a new criterion, which takes into account both energy consumption and time complexity, to evaluate anti-collision protocols. An improved protocol is also presented for power savings.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116798089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a method that uses data buffers to smoothen request variations and to create long idleness for power management. This method considers the power consumed by the buffers and assigns an energy penalty for buffer underflow. Our approach provides analytic formulas for calculating the optimal buffer sizes and the amount of data to store in the buffers. We use video prefetching as a case study and obtain power savings of more than 74% for MPEG-1 and 34% for MPEG-2 videos.
{"title":"Dynamic power management for streaming data","authors":"N. Pettis, Le Cai, Yung-Hsiang Lu","doi":"10.1145/1013235.1013256","DOIUrl":"https://doi.org/10.1145/1013235.1013256","url":null,"abstract":"This paper presents a method that uses data buffers to smoothen request variations and to create long idleness for power management. This method considers the power consumed by the buffers and assigns an energy penalty for buffer underflow. Our approach provides analytic formulas for calculating the optimal buffer sizes and the amount of data to store in the buffers. We use video prefetching as a case study and obtain power savings of more than 74% for MPEG-1 and 34% for MPEG-2 videos.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126303477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a technique called "workload decomposition" in which the CPU workload is decomposed in two parts: on-chip and off-chip. The on-chip workload signifies the CPU clock cycles that are required to execute instructions in the CPU whereas the off-chip workload captures the number of external memory access clock cycles that are required to perform external memory transactions. When combined with a dynamic voltage and frequency scaling (DVFS) technique to minimize the energy consumption, this workload decomposition method results in higher energy savings. The workload decomposition itself is performed at run time based on statistics reported by a performance monitoring unit (PMU) without a need for application profiling or compiler support. We have implemented the proposed DVFS with workload decomposition technique on the BitsyX platform, an Intel PXA255-based platform manufactured by ADS Inc., and performed detailed energy measurements. These measurements show that, for a number of widely used software applications, a CPU energy saving of 80% can be achieved for memory-bound programs while satisfying the user-specified timing constraints.
{"title":"Dynamic voltage and frequency scaling based on workload decomposition","authors":"Kihwan Choi, R. Soma, Massoud Pedram","doi":"10.1145/1013235.1013282","DOIUrl":"https://doi.org/10.1145/1013235.1013282","url":null,"abstract":"This paper presents a technique called \"workload decomposition\" in which the CPU workload is decomposed in two parts: on-chip and off-chip. The on-chip workload signifies the CPU clock cycles that are required to execute instructions in the CPU whereas the off-chip workload captures the number of external memory access clock cycles that are required to perform external memory transactions. When combined with a dynamic voltage and frequency scaling (DVFS) technique to minimize the energy consumption, this workload decomposition method results in higher energy savings. The workload decomposition itself is performed at run time based on statistics reported by a performance monitoring unit (PMU) without a need for application profiling or compiler support. We have implemented the proposed DVFS with workload decomposition technique on the BitsyX platform, an Intel PXA255-based platform manufactured by ADS Inc., and performed detailed energy measurements. These measurements show that, for a number of widely used software applications, a CPU energy saving of 80% can be achieved for memory-bound programs while satisfying the user-specified timing constraints.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121022213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mobile, battery-powered devices such as personal digital assistants and web-enabled mobile phones have successfully emerged as new access points to the world's digital infrastructure. However, the growing gap between device capabilities and battery technology requires novel techniques that extend battery life. Key to the success of such techniques, is our ability to accurately predict the power consumption of a program. In this paper we investigate the degree to which battery dissipation induced by program execution can be measured by application-level software tools and predicted by a compiler and runtime system. We present a novel technique with which we can accurately estimate whole-program power-consumption for an arbitrary program by composing battery dissipation rates of benchmarks. We empirically evaluate our technique using an iPAQ hand-held device and a number of MiBench and other programs.
{"title":"Application-level prediction of battery dissipation","authors":"C. Krintz, Ye Wen, R. Wolski","doi":"10.1145/1013235.1013292","DOIUrl":"https://doi.org/10.1145/1013235.1013292","url":null,"abstract":"Mobile, battery-powered devices such as personal digital assistants and web-enabled mobile phones have successfully emerged as new access points to the world's digital infrastructure. However, the growing gap between device capabilities and battery technology requires novel techniques that extend battery life. Key to the success of such techniques, is our ability to accurately predict the power consumption of a program. In this paper we investigate the degree to which battery dissipation induced by program execution can be measured by application-level software tools and predicted by a compiler and runtime system. We present a novel technique with which we can accurately estimate whole-program power-consumption for an arbitrary program by composing battery dissipation rates of benchmarks. We empirically evaluate our technique using an iPAQ hand-held device and a number of MiBench and other programs.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133506852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. With the introduction of Intel/spl reg/ Centrino/spl trade/ Mobile Technology in 2003, Intel redefined mobile computing to deliver the outstanding mobile performance, integrated wireless capability, while enabling extended battery life and thin and light designs that end users demand. In developing Intel Centrino Mobile Technology, Intel took an aggressive goal of enabling at least 3.5 hours (210 minutes) of battery life given typical usage of "thin and light" class notebooks with 6-cell lithium ion batteries. Compared with Intel/spl reg/ Pentium/spl reg/ 4 processor-M-based systems, this would be at least an hour more battery life. This goal was exceeded by the majority of the Intel Centrino mobile technology-based notebooks introduced at the launch in March 2003, with these notebooks delivering some of the longest battery run times available on mobile PCs. However, the industry is facing new challenges. Current battery technologies are topping out in capacity, while demands for new mobile PC capabilities and higher performance are driving higher average power consumption. This talk will address the opportunity to innovate on lower power silicon and platform designs as well as higher density and renewable power sources to enable 8-hour or greater battery life for "all-day" computing. Techniques used today to deliver lower average power at the silicon as well as platform levels will be discussed, (e.g., voltage and frequency scaling techniques are use in today's silicon to provide performance-on-demand while consuming lowest average power when the processor is idle, lower power display technologies such as LTPS reduce power by at least 30% over conventional displays) as well as alternative battery chemistries that may deliver higher capacity and renewable/quick rechargeable sources will also be discussed.
{"title":"Battery life challenges on future mobile notebook platforms","authors":"S. Thakkar","doi":"10.1145/1013235.1013238","DOIUrl":"https://doi.org/10.1145/1013235.1013238","url":null,"abstract":"Summary form only given. With the introduction of Intel/spl reg/ Centrino/spl trade/ Mobile Technology in 2003, Intel redefined mobile computing to deliver the outstanding mobile performance, integrated wireless capability, while enabling extended battery life and thin and light designs that end users demand. In developing Intel Centrino Mobile Technology, Intel took an aggressive goal of enabling at least 3.5 hours (210 minutes) of battery life given typical usage of \"thin and light\" class notebooks with 6-cell lithium ion batteries. Compared with Intel/spl reg/ Pentium/spl reg/ 4 processor-M-based systems, this would be at least an hour more battery life. This goal was exceeded by the majority of the Intel Centrino mobile technology-based notebooks introduced at the launch in March 2003, with these notebooks delivering some of the longest battery run times available on mobile PCs. However, the industry is facing new challenges. Current battery technologies are topping out in capacity, while demands for new mobile PC capabilities and higher performance are driving higher average power consumption. This talk will address the opportunity to innovate on lower power silicon and platform designs as well as higher density and renewable power sources to enable 8-hour or greater battery life for \"all-day\" computing. Techniques used today to deliver lower average power at the silicon as well as platform levels will be discussed, (e.g., voltage and frequency scaling techniques are use in today's silicon to provide performance-on-demand while consuming lowest average power when the processor is idle, lower power display technologies such as LTPS reduce power by at least 30% over conventional displays) as well as alternative battery chemistries that may deliver higher capacity and renewable/quick rechargeable sources will also be discussed.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132281731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Traditionally, dynamic voltage scaling (DVS) techniques have focused on minimizing the processor energy consumption as opposed to the entire system energy consumption. The slowdown resulting from DVS can increase the energy consumption of components like memory and network interfaces. Furthermore, the leakage power consumption is increasing with the scaling device technology and must also be taken into account. In this work, we consider energy efficient slowdown in a real-time task system. We present an algorithm to compute task slowdown factors based on the contribution of the processor leakage and standby energy consumption of the resources in the system. Our simulation experiments using randomly generated task sets show on an average 10% energy gains over traditional dynamic voltage scaling. We further combine slowdown with procrastination scheduling which increases the average energy savings to 15%. We show that our scheduling approach minimizes the total static and dynamic energy consumption of the systemwide resources.
{"title":"Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems","authors":"R. Jejurikar, Rajesh K. Gupta","doi":"10.1145/1013235.1013261","DOIUrl":"https://doi.org/10.1145/1013235.1013261","url":null,"abstract":"Traditionally, dynamic voltage scaling (DVS) techniques have focused on minimizing the processor energy consumption as opposed to the entire system energy consumption. The slowdown resulting from DVS can increase the energy consumption of components like memory and network interfaces. Furthermore, the leakage power consumption is increasing with the scaling device technology and must also be taken into account. In this work, we consider energy efficient slowdown in a real-time task system. We present an algorithm to compute task slowdown factors based on the contribution of the processor leakage and standby energy consumption of the resources in the system. Our simulation experiments using randomly generated task sets show on an average 10% energy gains over traditional dynamic voltage scaling. We further combine slowdown with procrastination scheduling which increases the average energy savings to 15%. We show that our scheduling approach minimizes the total static and dynamic energy consumption of the systemwide resources.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124007678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. It is common to differentiate between two ways of building a nanodevice: a top-down approach where we start from something big and chisel out what we want and a bottom-up approach where we start from something small like atoms or molecules and assemble what we want. When it comes to describing electrical resistance, the standard approach could be called a "top-down" one where we start from large complex resistors and work our way down to molecules primarily because our understanding has evolved in this top-down fashion. However, it is instructive to take a bottom-up view of the subject starting from the conductance of something really small, like a molecule, and then discussing the issues that arise as we move to bigger conductors. This is the subject of this tutorial lecture (S. Datta, Nanotechnology, vol. 15, p. S433, 2004). Remarkably enough, no serious quantum mechanics is needed to understand electrical conduction through something really small, except for unusual things like the Kondo effect that are seen only for a special range of parameters. The presentation begins with (1) energy level diagrams, (2) shows that the broadening that accompanies coupling limits the conductance to a maximum of (q¿2/h) per level, (3) describes how a change in the shape of the self-consistent potential profile can turn a symmetric current-voltage characteristic into a rectifying one, (4) shows that many interesting effects in "nanoelectronics" can be understood in terms of a simple model, and (5) introduces the nonequilibrium Green's function (NEGF) formalism as a sophisticated version of this simple model with ordinary numbers replaced by appropriate matrices. Finally the distinction between the self-consistent field regime and the Coulomb blockade regime and the issues involved in modeling each of these regimes are described.
只提供摘要形式。构建纳米器件的两种方法通常是不同的:一种是自上而下的方法，我们从大的东西开始，凿出我们想要的东西;另一种是自下而上的方法，我们从原子或分子这样的小的东西开始，组装我们想要的东西。当涉及到描述电阻时，标准的方法可以被称为“自上而下”的方法，我们从大型复杂的电阻开始，一直到分子，主要是因为我们的理解是在这种自上而下的方式中发展起来的。然而，从一个非常小的东西的电导率开始，比如一个分子，然后讨论当我们移动到更大的导体时出现的问题，这是有益的。这是本教程的主题(S. Datta, Nanotechnology, vol. 15, p. S433, 2004)。值得注意的是，不需要严肃的量子力学来理解通过非常小的物体的导电，除了像近藤效应这样的不寻常的东西，它只能在特殊的参数范围内看到。演示从(1)能级图开始，(2)表明，伴随着耦合的展宽将电导限制在每级(q¿2/h)的最大值，(3)描述了自一致电位分布形状的变化如何将对称的电流-电压特性转变为整流特性，(4)表明“纳米电子学”中的许多有趣的效应可以用一个简单的模型来理解。(5)引入非平衡格林函数(NEGF)形式主义作为这个简单模型的复杂版本，用适当的矩阵代替普通数字。最后介绍了自洽场和库仑封锁场的区别，以及对这两种情况进行建模所涉及的问题。
{"title":"Understanding nanoscale conductors","authors":"S. Datta","doi":"10.1145/1013235.1013240","DOIUrl":"https://doi.org/10.1145/1013235.1013240","url":null,"abstract":"Summary form only given. It is common to differentiate between two ways of building a nanodevice: a top-down approach where we start from something big and chisel out what we want and a bottom-up approach where we start from something small like atoms or molecules and assemble what we want. When it comes to describing electrical resistance, the standard approach could be called a \"top-down\" one where we start from large complex resistors and work our way down to molecules primarily because our understanding has evolved in this top-down fashion. However, it is instructive to take a bottom-up view of the subject starting from the conductance of something really small, like a molecule, and then discussing the issues that arise as we move to bigger conductors. This is the subject of this tutorial lecture (S. Datta, Nanotechnology, vol. 15, p. S433, 2004). Remarkably enough, no serious quantum mechanics is needed to understand electrical conduction through something really small, except for unusual things like the Kondo effect that are seen only for a special range of parameters. The presentation begins with (1) energy level diagrams, (2) shows that the broadening that accompanies coupling limits the conductance to a maximum of (q¿2/h) per level, (3) describes how a change in the shape of the self-consistent potential profile can turn a symmetric current-voltage characteristic into a rectifying one, (4) shows that many interesting effects in \"nanoelectronics\" can be understood in terms of a simple model, and (5) introduces the nonequilibrium Green's function (NEGF) formalism as a sophisticated version of this simple model with ordinary numbers replaced by appropriate matrices. Finally the distinction between the self-consistent field regime and the Coulomb blockade regime and the issues involved in modeling each of these regimes are described.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116014364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cells to measure on-chip temperature and leakage. Using the dependence of leakage currents to temperature, we measure varying decay (discharge) times of the 4T cell at different temperatures. Thus, decaying 4T sensors provide a digital pulse whose frequency depends on temperature. Because of the sensors' very small size, we can easily embed them in many structures thus obtaining both redundancy and a fine-grain thermal picture of the chip. A significant advantage of our sensor design is that it is insensitive to process variations at high temperatures. It is also relatively robust to noise. We propose mechanisms to measure temperature that exploit the sensor's small size and speed to increase measurement reliability. Decaying 4T sensors also provide a measurement of the level of leakage at their sensing area, allowing us to adjust leakage-control policies. Our 4T sensors are significantly smaller, faster, more reliable, and power efficient compared to the best previously proposed designs enabling new approaches to architectural-level thermal and leakage management.
{"title":"4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors","authors":"S. Kaxiras, Polychronis Xekalakis","doi":"10.1145/1013235.1013268","DOIUrl":"https://doi.org/10.1145/1013235.1013268","url":null,"abstract":"We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cells to measure on-chip temperature and leakage. Using the dependence of leakage currents to temperature, we measure varying decay (discharge) times of the 4T cell at different temperatures. Thus, decaying 4T sensors provide a digital pulse whose frequency depends on temperature. Because of the sensors' very small size, we can easily embed them in many structures thus obtaining both redundancy and a fine-grain thermal picture of the chip. A significant advantage of our sensor design is that it is insensitive to process variations at high temperatures. It is also relatively robust to noise. We propose mechanisms to measure temperature that exploit the sensor's small size and speed to increase measurement reliability. Decaying 4T sensors also provide a measurement of the level of leakage at their sensing area, allowing us to adjust leakage-control policies. Our 4T sensors are significantly smaller, faster, more reliable, and power efficient compared to the best previously proposed designs enabling new approaches to architectural-level thermal and leakage management.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120968599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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