Power consumption is an important design issue of current embedded systems. It has been shown that the instruction cache accounts for a significant portion of the power dissipation of the whole chip. Several studies propose to add a cache (L0 cache) that is very small relative to the conventional L1 cache on chip for power optimization since a smaller cache has lower load capacitance. However, energy savings often come at the cost of performance degradation. In this paper, we propose a novel instruction cache architecture, the HotSpot cache, that achieves energy savings without sacrificing performance. The HotSpot cache identifies frequently accessed instructions dynamically and stores them in the L0 cache. Other instructions are placed only in the L1 cache. A steering mechanism is employed to direct an instruction to its allocated cache in the instruction fetch stage. The simulation results show that the HotSpot cache can achieve 52% instruction cache energy reduction on the average for a set of multimedia applications without performance degradation.
{"title":"HotSpot cache: joint temporal and spatial locality exploitation for I-cache energy reduction","authors":"Chia-Lin Yang, Chien-Hao Lee","doi":"10.1145/1013235.1013270","DOIUrl":"https://doi.org/10.1145/1013235.1013270","url":null,"abstract":"Power consumption is an important design issue of current embedded systems. It has been shown that the instruction cache accounts for a significant portion of the power dissipation of the whole chip. Several studies propose to add a cache (L0 cache) that is very small relative to the conventional L1 cache on chip for power optimization since a smaller cache has lower load capacitance. However, energy savings often come at the cost of performance degradation. In this paper, we propose a novel instruction cache architecture, the HotSpot cache, that achieves energy savings without sacrificing performance. The HotSpot cache identifies frequently accessed instructions dynamically and stores them in the L0 cache. Other instructions are placed only in the L1 cache. A steering mechanism is employed to direct an instruction to its allocated cache in the instruction fetch stage. The simulation results show that the HotSpot cache can achieve 52% instruction cache energy reduction on the average for a set of multimedia applications without performance degradation.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127673419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The integrated circuit manufacturing process has inevitable imperfections and fluctuations that result in ever-growing systematic and random variations in the electrical parameters of active and passive devices fabricated. The impact of such variations on various aspects of chip performance has been the subject of numerous papers, and techniques for analyzing and dealing with such variability, broadly labelled design for manufacturability, are emerging as the next hot topic in this area. The focus of much of the current work in this area has been on timing, but it is well known that modern integrated circuits are very heavily power limited and that static and dynamic power have emerged as first class design objectives. In this paper, we review the various sources of process variability, and relate them to variability in the various parts of the power delivery subsystem. Specifically, we address variability in the following areas: 1. static (leakage) power; 2. dynamic power; 3. on-chip power grid; 4. on-chip decoupling capacitance; 5. package power grid; 6. workload. It is important to model all these sources of variability with the correct balance of effort and accuracy, thus it is important to get broad bounds on each of the sources in order to insure that the appropriate level of modeling and analysis investment is made in order to bound or worst-case each component without undue pessimism. It is also important to have a first order understanding of the technology trends in each of these sources of variability. This will allow the designer and CAD tool developer to anticipate future problem areas and plan work arounds as needed.
{"title":"The impact of variability on power","authors":"S. Nassif","doi":"10.1145/1013235.1013241","DOIUrl":"https://doi.org/10.1145/1013235.1013241","url":null,"abstract":"Summary form only given. The integrated circuit manufacturing process has inevitable imperfections and fluctuations that result in ever-growing systematic and random variations in the electrical parameters of active and passive devices fabricated. The impact of such variations on various aspects of chip performance has been the subject of numerous papers, and techniques for analyzing and dealing with such variability, broadly labelled design for manufacturability, are emerging as the next hot topic in this area. The focus of much of the current work in this area has been on timing, but it is well known that modern integrated circuits are very heavily power limited and that static and dynamic power have emerged as first class design objectives. In this paper, we review the various sources of process variability, and relate them to variability in the various parts of the power delivery subsystem. Specifically, we address variability in the following areas: 1. static (leakage) power; 2. dynamic power; 3. on-chip power grid; 4. on-chip decoupling capacitance; 5. package power grid; 6. workload. It is important to model all these sources of variability with the correct balance of effort and accuracy, thus it is important to get broad bounds on each of the sources in order to insure that the appropriate level of modeling and analysis investment is made in order to bound or worst-case each component without undue pessimism. It is also important to have a first order understanding of the technology trends in each of these sources of variability. This will allow the designer and CAD tool developer to anticipate future problem areas and plan work arounds as needed.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129917859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present a circuit technique that supports a super-drowsy mode with a single-V/sub DD/. In addition, we perform a detailed working set analysis for various cache line update policies for placing lines in a drowsy state. The analysis presents a policy for an instruction cache and shows it is as good as or better than more complex schemes proposed in the past. Furthermore, as air alternative to using high-threshold devices to reduce the bitline leakage through access transistors in drowsy caches, we propose a gated bitline precharge technique. A single threshold process is now sufficient. The gated precharge employs a simple but effective predictor that almost completely hides any performance loss incurred by the transitions between sub-banks. A 64-entry predictor with 3 bits per entry reduces the run-time increase by 78%, which is as effective as previous proposals that used content addressable predictors with 40 bits per entry. Overall, the combination of the proposed techniques reduces the leakage power by 72% with negligible (0.4%) run-time increase.
{"title":"Single-V/sub DD/ and single-V/sub T/ super-drowsy techniques for low-leakage high-performance instruction caches","authors":"N. Kim, K. Flautner, D. Blaauw, T. Mudge","doi":"10.1145/1013235.1013254","DOIUrl":"https://doi.org/10.1145/1013235.1013254","url":null,"abstract":"In this paper, we present a circuit technique that supports a super-drowsy mode with a single-V/sub DD/. In addition, we perform a detailed working set analysis for various cache line update policies for placing lines in a drowsy state. The analysis presents a policy for an instruction cache and shows it is as good as or better than more complex schemes proposed in the past. Furthermore, as air alternative to using high-threshold devices to reduce the bitline leakage through access transistors in drowsy caches, we propose a gated bitline precharge technique. A single threshold process is now sufficient. The gated precharge employs a simple but effective predictor that almost completely hides any performance loss incurred by the transitions between sub-banks. A 64-entry predictor with 3 bits per entry reduces the run-time increase by 78%, which is as effective as previous proposals that used content addressable predictors with 40 bits per entry. Overall, the combination of the proposed techniques reduces the leakage power by 72% with negligible (0.4%) run-time increase.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129998265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dynamic supply voltage scaling (DVS) is one of the best ways to reduce the energy consumption of a device when there is a super-linear relationship between energy and supply voltage, and a pseudo-linear relationship between delay and supply voltage. However, most DVS schemes scale the clock frequency of the supply-voltage-clock-scalable (SVCS) CPU only and do not address the energy consumption of the memory. The memory is generally non-supply-voltage-scalable (NSVS), but its energy consumption is variable to its clock frequency and the total execution time. Thus, DVS for an SVCS CPU cannot achieve an optimal system-wide energy saving without consideration of the memory, as far as it is controlled by an SVCS CPU. We introduce an energy-optimal frequency assignment, for both an SVCS CPU and a synchronous NSVS memory, which optimizes the system-wide energy consumption. We derive the energy-optimal clock frequencies for an SVCS CPU and a synchronous NSVS memory, as a function of the number of processor clock cycles, the number of memory accesses and the hardware energy model. Our technique modifies the frequency assignment of the CPU and the memory used in previous DVS schemes, which ignore the memory energy. It enables the system-wide energy-optimal settings and achieves additional 50% energy reduction over previous DVS schemes. This technique can also be applicable to synchronous NSVS peripheral devices.
{"title":"Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling","authors":"Youngjin Cho, N. Chang","doi":"10.1145/1013235.1013327","DOIUrl":"https://doi.org/10.1145/1013235.1013327","url":null,"abstract":"Dynamic supply voltage scaling (DVS) is one of the best ways to reduce the energy consumption of a device when there is a super-linear relationship between energy and supply voltage, and a pseudo-linear relationship between delay and supply voltage. However, most DVS schemes scale the clock frequency of the supply-voltage-clock-scalable (SVCS) CPU only and do not address the energy consumption of the memory. The memory is generally non-supply-voltage-scalable (NSVS), but its energy consumption is variable to its clock frequency and the total execution time. Thus, DVS for an SVCS CPU cannot achieve an optimal system-wide energy saving without consideration of the memory, as far as it is controlled by an SVCS CPU. We introduce an energy-optimal frequency assignment, for both an SVCS CPU and a synchronous NSVS memory, which optimizes the system-wide energy consumption. We derive the energy-optimal clock frequencies for an SVCS CPU and a synchronous NSVS memory, as a function of the number of processor clock cycles, the number of memory accesses and the hardware energy model. Our technique modifies the frequency assignment of the CPU and the memory used in previous DVS schemes, which ignore the memory energy. It enables the system-wide energy-optimal settings and achieves additional 50% energy reduction over previous DVS schemes. This technique can also be applicable to synchronous NSVS peripheral devices.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130486051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel rail-to-rail and fast continuous-time common-mode feedback (CMFB) strategy is presented for low-voltage switched-opamp (SO) circuits. The threshold voltage change due to bulk signal is used to measure the output voltage. To satisfy speed requirements, averaging common-mode (CM) level and amplifying error signal are realized in a single block. Finally, the measured CM level is controlled by applying an error-voltage dependent current to the output nodes. As a design example, a modified low-voltage switched-opamp in a cascade 2-1 delta-sigma modulator adopting the proposed technique is presented. SPICE simulation using a 0.18 /spl mu/m technology and V/sub DD/=0.9 V is provided which confirms the expected accuracy and speed of the CMFB circuitry.
{"title":"A novel continuous-time common-mode feedback for low-voltage switched-OPAMP","authors":"M. Ali-Bakhshian, K. Sadeghi","doi":"10.1145/1013235.1013308","DOIUrl":"https://doi.org/10.1145/1013235.1013308","url":null,"abstract":"A novel rail-to-rail and fast continuous-time common-mode feedback (CMFB) strategy is presented for low-voltage switched-opamp (SO) circuits. The threshold voltage change due to bulk signal is used to measure the output voltage. To satisfy speed requirements, averaging common-mode (CM) level and amplifying error signal are realized in a single block. Finally, the measured CM level is controlled by applying an error-voltage dependent current to the output nodes. As a design example, a modified low-voltage switched-opamp in a cascade 2-1 delta-sigma modulator adopting the proposed technique is presented. SPICE simulation using a 0.18 /spl mu/m technology and V/sub DD/=0.9 V is provided which confirms the expected accuracy and speed of the CMFB circuitry.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121046505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In an attempt to enable the cost-effective production of low and mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectures. These architectures represent a departure from traditional standard-cell-based ASIC designs in favor of techniques which present more physical and structural regularity. This paper presents circuits which provide power-performance flexibility in this regular, structured ASIC environment. These circuits, which employ gate sizing and voltage scaling for energy efficiency, enable delay-constrained power optimization to be performed for structured ASIC designs.
{"title":"Creating a power-aware structured ASIC","authors":"R. Taylor, H. Schmit","doi":"10.1145/1013235.1013260","DOIUrl":"https://doi.org/10.1145/1013235.1013260","url":null,"abstract":"In an attempt to enable the cost-effective production of low and mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectures. These architectures represent a departure from traditional standard-cell-based ASIC designs in favor of techniques which present more physical and structural regularity. This paper presents circuits which provide power-performance flexibility in this regular, structured ASIC environment. These circuits, which employ gate sizing and voltage scaling for energy efficiency, enable delay-constrained power optimization to be performed for structured ASIC designs.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130906918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhigang Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, H. Jacobson, P. Bose
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for power gating execution units is then evaluated, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-of-order superscalar processor model. The power gating potential of the floating-point and fixed-point units of this processor is then evaluated using three different techniques to detect opportunities for entering sleep mode; ideal, time-based, and branch-misprediction-guided. Our results show that using the time-based approach, floating-point units can be put to sleep for up to 28% of the execution cycles at a performance loss of 2%. For the more difficult to power-gate fixed-point units, the branch misprediction guided technique allows the fixed-point units to be put to sleep for up to 40% more of the execution cycles compared to the simpler time-based technique, with similar performance impact. Overall, our experiments demonstrate that architectural techniques can be used effectively in power-gating execution units.
{"title":"Microarchitectural techniques for power gating of execution units","authors":"Zhigang Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, H. Jacobson, P. Bose","doi":"10.1145/1013235.1013249","DOIUrl":"https://doi.org/10.1145/1013235.1013249","url":null,"abstract":"Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for power gating execution units is then evaluated, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-of-order superscalar processor model. The power gating potential of the floating-point and fixed-point units of this processor is then evaluated using three different techniques to detect opportunities for entering sleep mode; ideal, time-based, and branch-misprediction-guided. Our results show that using the time-based approach, floating-point units can be put to sleep for up to 28% of the execution cycles at a performance loss of 2%. For the more difficult to power-gate fixed-point units, the branch misprediction guided technique allows the fixed-point units to be put to sleep for up to 40% more of the execution cycles compared to the simpler time-based technique, with similar performance impact. Overall, our experiments demonstrate that architectural techniques can be used effectively in power-gating execution units.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131061190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Gregori, Yunlei Li, Huijuan Li, Jin Liu, F. Maloberti
This paper describes a power conversion and data recovery system for a microwave powered sensor platform. A patch microwave antenna, a matching filter and a rectifier make the system front-end and implement the RF-to-DC conversion of power carrier. The efficiency of the power conversion is as high as 47% with an input power level 250 /spl Omega/W at 2.45 GHz. Then, a 0.18 /spl Omega/m CMOS integrated circuit extracts the clock and the digital data. A modified pulse amplitude modulation scheme is used to modulate the data on the 2.45 GHz carrier frequency for combined data and power transmission; this scheme allows very low power consumption of the entire IC to be less than 10 /spl Omega/W and making the system suitable for an autonomous wireless connected sensor module.
{"title":"2.45 GHz power and data transmission for a low-power autonomous sensors platform","authors":"S. Gregori, Yunlei Li, Huijuan Li, Jin Liu, F. Maloberti","doi":"10.1145/1013235.1013303","DOIUrl":"https://doi.org/10.1145/1013235.1013303","url":null,"abstract":"This paper describes a power conversion and data recovery system for a microwave powered sensor platform. A patch microwave antenna, a matching filter and a rectifier make the system front-end and implement the RF-to-DC conversion of power carrier. The efficiency of the power conversion is as high as 47% with an input power level 250 /spl Omega/W at 2.45 GHz. Then, a 0.18 /spl Omega/m CMOS integrated circuit extracts the clock and the digital data. A modified pulse amplitude modulation scheme is used to modulate the data on the 2.45 GHz carrier frequency for combined data and power transmission; this scheme allows very low power consumption of the entire IC to be less than 10 /spl Omega/W and making the system suitable for an autonomous wireless connected sensor module.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131723231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Six 10GHz MOS VCOs were designed and fabricated in the IBM 6RF 0.25um CMOS process. Their oscillation frequency, output amplitude and phase noise performance are measured and compared, and the results confirm that replacing shielded-ground inductors with high-resistivity substrate inductors improves phase noise performance. Capacitive source degeneration has also been identified as a performance limiting mechanism in MOS based VCOs rather than performance enhancing as in BJT based VCOs.
采用IBM 6RF 0.25um CMOS工艺设计并制造了6个10GHz MOS vco。测量和比较了它们的振荡频率、输出幅值和相位噪声性能，结果证实用高电阻率衬底电感代替屏蔽接地电感改善了相位噪声性能。电容源退化也被认为是MOS型压控振荡器的性能限制机制，而不是BJT型压控振荡器的性能增强机制。
{"title":"A comparative study of MOS VCOs for low voltage high performance operation","authors":"J. Zhan, J. Duster, K. Kornegay","doi":"10.1145/1013235.1013297","DOIUrl":"https://doi.org/10.1145/1013235.1013297","url":null,"abstract":"Six 10GHz MOS VCOs were designed and fabricated in the IBM 6RF 0.25um CMOS process. Their oscillation frequency, output amplitude and phase noise performance are measured and compared, and the results confirm that replacing shielded-ground inductors with high-resistivity substrate inductors improves phase noise performance. Capacitive source degeneration has also been identified as a performance limiting mechanism in MOS based VCOs rather than performance enhancing as in BJT based VCOs.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124080710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we propose a new algorithm for reducing the energy dissipation of a wireless ad-hoc network. We first show that the performance and energy dissipation is a function of the probability of packet collision, which can be varied by changing the minimum contention window (CW/sub min/) parameter. Then we propose all algorithm, based on the IEEE 802.11 protocol, which can dynamically adjust CW/sub min/ for better performance and power. Experimental results show that, comparing to the original protocol, the proposed method can save 30% to 60% energy dissipation, and achieve similar or better performance.
{"title":"ESACW: an adaptive algorithm for transmission power reduction in wireless networks","authors":"Hang Su, Peiliang Qiu, Qinru Qiu","doi":"10.1145/1013235.1013262","DOIUrl":"https://doi.org/10.1145/1013235.1013262","url":null,"abstract":"In this paper we propose a new algorithm for reducing the energy dissipation of a wireless ad-hoc network. We first show that the performance and energy dissipation is a function of the probability of packet collision, which can be varied by changing the minimum contention window (CW/sub min/) parameter. Then we propose all algorithm, based on the IEEE 802.11 protocol, which can dynamically adjust CW/sub min/ for better performance and power. Experimental results show that, comparing to the original protocol, the proposed method can save 30% to 60% energy dissipation, and achieve similar or better performance.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124333092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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