Digital circuits operated in the sub-threshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultra-low power and medium frequency of operation. It is possible to implement sub-threshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, a Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the sub-threshold domain. In this paper, we propose device designs apt for sub-threshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the sub-threshold region.
{"title":"Device optimization for ultra-low power digital sub-threshold operation","authors":"B. Paul, A. Raychowdhury, K. Roy","doi":"10.1145/1013235.1013266","DOIUrl":"https://doi.org/10.1145/1013235.1013266","url":null,"abstract":"Digital circuits operated in the sub-threshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultra-low power and medium frequency of operation. It is possible to implement sub-threshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, a Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the sub-threshold domain. In this paper, we propose device designs apt for sub-threshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the sub-threshold region.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121640406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Caches contribute to much of a microprocessor system's power and energy consumption. We have developed a new cache architecture, called a way-halting cache, that reduces energy while imposing no performance overhead. Our way-halting cache is a four-way set-associative cache that stores the four lowest-order bits of all ways' tags into a fully associative memory, which we call the halt tag array. The look-up in the hall tag array is done in parallel with, and is no slower than, the set-index decoding. The hall tag array pre-determines which tags cannot match due to their low-order four bits mismatching. Further accesses to ways with known mismatching tags are then halted, thus saving power. Our halt tag array has an additional feature of using static logic only, rather than dynamic logic used in highly associative caches. We provide data from experiments on 17 benchmarks drawn from MediaBench and Spec 2000, based on our layouts in 0.18 micron CMOS technology, On average, 55% savings of memory-access related energy were obtained over a conventional four-way set-associative cache. We show that energy savings are greater than previous methods, and nearly twice that of highly-associative caches, while imposing no performance overhead and only 2% cache area overhead.
{"title":"A way-halting cache for low-energy high-performance systems","authors":"Chuanjun Zhang, F. Vahid, Jun Yang, W. Najjar","doi":"10.1145/1013235.1013272","DOIUrl":"https://doi.org/10.1145/1013235.1013272","url":null,"abstract":"Caches contribute to much of a microprocessor system's power and energy consumption. We have developed a new cache architecture, called a way-halting cache, that reduces energy while imposing no performance overhead. Our way-halting cache is a four-way set-associative cache that stores the four lowest-order bits of all ways' tags into a fully associative memory, which we call the halt tag array. The look-up in the hall tag array is done in parallel with, and is no slower than, the set-index decoding. The hall tag array pre-determines which tags cannot match due to their low-order four bits mismatching. Further accesses to ways with known mismatching tags are then halted, thus saving power. Our halt tag array has an additional feature of using static logic only, rather than dynamic logic used in highly associative caches. We provide data from experiments on 17 benchmarks drawn from MediaBench and Spec 2000, based on our layouts in 0.18 micron CMOS technology, On average, 55% savings of memory-access related energy were obtained over a conventional four-way set-associative cache. We show that energy savings are greater than previous methods, and nearly twice that of highly-associative caches, while imposing no performance overhead and only 2% cache area overhead.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115689593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a class of low-power codes, called Limited Intra-Word Transition (LIWT) codes, suitable for the digital interface to Liquid Crystal Displays (LCD). The proposed technique exploits the existing inter-pixel correlation of typical images, by transmitting an encoded representation of the difference between adjacent pixels. Since all standard LCD transmission protocols are serial, the LIWT specifically targets the minimization of intra-word transitions. The application of the encoding to a series of standard images resulted in transitions savings over 60% on average with respect to two standard TMDS and LVDS protocols.
{"title":"Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces","authors":"S. Salerno, Alberto Bocca, E. Macii, M. Poncino","doi":"10.1145/1013235.1013288","DOIUrl":"https://doi.org/10.1145/1013235.1013288","url":null,"abstract":"We propose a class of low-power codes, called Limited Intra-Word Transition (LIWT) codes, suitable for the digital interface to Liquid Crystal Displays (LCD). The proposed technique exploits the existing inter-pixel correlation of typical images, by transmitting an encoded representation of the difference between adjacent pixels. Since all standard LCD transmission protocols are serial, the LIWT specifically targets the minimization of intra-word transitions. The application of the encoding to a series of standard images resulted in transitions savings over 60% on average with respect to two standard TMDS and LVDS protocols.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123395374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu
In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 /spl mu/m process parameters, the results show that INL < /spl plusmn/0.4 LSB and DNL < /spl plusmn/0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.
{"title":"A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach","authors":"Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu","doi":"10.1145/1013235.1013300","DOIUrl":"https://doi.org/10.1145/1013235.1013300","url":null,"abstract":"In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 /spl mu/m process parameters, the results show that INL < /spl plusmn/0.4 LSB and DNL < /spl plusmn/0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":"4 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120972473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by deep-submicron technologies can be alleviated by using a multiple voltage/multiple frequency island design style, otherwise called the globally asynchronous, locally synchronous (GALS) design paradigm. This paper proposes a clustered architecture that enables application-adaptive energy efficiency through the use of dynamic voltage scaling for application code that is rendered non-critical for the overall performance, at run-time. As opposed to task scheduling using dynamic voltage scaling (DVS) that exploits workload variations across applications, our approach targets workload variations within the same application, while on-the fly classifying code as critical or noncritical and adapting to changes in the criticality of such code portions. Our results show that application adaptive variable voltage/variable frequency clustered architectures are up to 22% better in energy and 11% better in energy-delay product than their non-adaptive counterparts, while providing up to 31% more energy savings when compared to DVS applied globally.
{"title":"Application adaptive energy efficient clustered architectures","authors":"Diana Marculescu","doi":"10.1145/1013235.1013318","DOIUrl":"https://doi.org/10.1145/1013235.1013318","url":null,"abstract":"As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by deep-submicron technologies can be alleviated by using a multiple voltage/multiple frequency island design style, otherwise called the globally asynchronous, locally synchronous (GALS) design paradigm. This paper proposes a clustered architecture that enables application-adaptive energy efficiency through the use of dynamic voltage scaling for application code that is rendered non-critical for the overall performance, at run-time. As opposed to task scheduling using dynamic voltage scaling (DVS) that exploits workload variations across applications, our approach targets workload variations within the same application, while on-the fly classifying code as critical or noncritical and adapting to changes in the criticality of such code portions. Our results show that application adaptive variable voltage/variable frequency clustered architectures are up to 22% better in energy and 11% better in energy-delay product than their non-adaptive counterparts, while providing up to 31% more energy savings when compared to DVS applied globally.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116561996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Leakage power for extremely scaled (L/sub eff/ = 25 nm) double-gate devices is examined. Numerical two-dimensional simulation results for double-gate CMOS device/circuit power are presented from physics principle, identifying that double-gate technology is an ideal candidate for low-power applications. Unique double-gate device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design tradeoffs for double-gate CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for double-gate device are analyzed considering state dependency, showing that leakage current is reduced by a factor of over 10X, compared with conventional bulk-Si counterpart.
{"title":"Nanoscale CMOS circuit leakage power reduction by double-gate device","authors":"Keunwoo Kim, K. Das, R. Joshi, C. Chuang","doi":"10.1145/1013235.1013267","DOIUrl":"https://doi.org/10.1145/1013235.1013267","url":null,"abstract":"Leakage power for extremely scaled (L/sub eff/ = 25 nm) double-gate devices is examined. Numerical two-dimensional simulation results for double-gate CMOS device/circuit power are presented from physics principle, identifying that double-gate technology is an ideal candidate for low-power applications. Unique double-gate device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design tradeoffs for double-gate CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for double-gate device are analyzed considering state dependency, showing that leakage current is reduced by a factor of over 10X, compared with conventional bulk-Si counterpart.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130568198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modeling and estimation of switching activities remain to be important problems in low-power design and fault analysis. A probabilistic Bayesian network based switching model can explicitly model all spatio-temporal dependency relationships in a combinational circuit, resulting in zero-error estimates. However, the space-time requirements of exact estimation schemes, based on this model, increase with circuit complexity. This paper explores a non-simulative, importance sampling based, probabilistic estimation strategy that scales well with circuit complexity. It has the any-time aspect of simulation and the input pattern independence of probabilistic models.
{"title":"Any-time probabilistic switching model using Bayesian networks","authors":"Shiva Shankar Ramani, S. Bhanja","doi":"10.1145/1013235.1013263","DOIUrl":"https://doi.org/10.1145/1013235.1013263","url":null,"abstract":"Modeling and estimation of switching activities remain to be important problems in low-power design and fault analysis. A probabilistic Bayesian network based switching model can explicitly model all spatio-temporal dependency relationships in a combinational circuit, resulting in zero-error estimates. However, the space-time requirements of exact estimation schemes, based on this model, increase with circuit complexity. This paper explores a non-simulative, importance sampling based, probabilistic estimation strategy that scales well with circuit complexity. It has the any-time aspect of simulation and the input pattern independence of probabilistic models.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132065072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a comprehensive qualitative and analytical analysis of the effect of relative delay on the dissipated energy of coupled lines. Closed form expressions modeling the effect of relative delay on the dissipated energy, and the Miller coupling factor, MCF, are also presented. Skewing the worst switching case is shown to provide up to 50% reduction in energy dissipation. This observation was implemented in a low-power bus scheme, DLBS, which leads to a power reduction of up to 25%.
{"title":"Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses","authors":"M. Ghoneima, Y. Ismail","doi":"10.1145/1013235.1013257","DOIUrl":"https://doi.org/10.1145/1013235.1013257","url":null,"abstract":"This paper presents a comprehensive qualitative and analytical analysis of the effect of relative delay on the dissipated energy of coupled lines. Closed form expressions modeling the effect of relative delay on the dissipated energy, and the Miller coupling factor, MCF, are also presented. Skewing the worst switching case is shown to provide up to 50% reduction in energy dissipation. This observation was implemented in a low-power bus scheme, DLBS, which leads to a power reduction of up to 25%.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130414650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Raghunathan, T. Pering, R. Want, Alex Nguyen, P. Jensen
A detailed power analysis of a multi-radio mobile platform highlights the complex tradeoffs between the computation, storage, and communication subsystems. The particular mobile device, which does not include an LCD or other on-board display, can be used as a source for audio or video media files or a source/sink for secure data transfers. A version of the device has been augmented with fine-grained power monitoring capability and used to obtain detailed measurements of power dissipation in the various subsystems. Analysis of these measurements sheds light on the power consumption characteristics of different applications, thereby providing hints to system designers about potential areas for optimization. Specifically, this work contrasts the power efficiency of the various wireless technologies supported by the system.
{"title":"Experience with a low power wireless mobile computing platform","authors":"V. Raghunathan, T. Pering, R. Want, Alex Nguyen, P. Jensen","doi":"10.1145/1013235.1013322","DOIUrl":"https://doi.org/10.1145/1013235.1013322","url":null,"abstract":"A detailed power analysis of a multi-radio mobile platform highlights the complex tradeoffs between the computation, storage, and communication subsystems. The particular mobile device, which does not include an LCD or other on-board display, can be used as a source for audio or video media files or a source/sink for secure data transfers. A version of the device has been augmented with fine-grained power monitoring capability and used to obtain detailed measurements of power dissipation in the various subsystems. Analysis of these measurements sheds light on the power consumption characteristics of different applications, thereby providing hints to system designers about potential areas for optimization. Specifically, this work contrasts the power efficiency of the various wireless technologies supported by the system.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116760336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Verhelst, W. Vereecken, M. Steyaert, W. Dehaene
This paper compares different receiver architectures for UWB radio communication in the 3.1-5GHz band, targeting data rates up to 10Mbps, in terms of their BER performance and power consumption. A receiver, in which some correlations are carried out in the analog domain seems to outperform a fully digital receiver, commonly suggested for baseband UWB. This paper proves that for equal processing gain requirements the partially analog receiver consumes 7 times less power per received bit than the fully digital one.
{"title":"Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps","authors":"M. Verhelst, W. Vereecken, M. Steyaert, W. Dehaene","doi":"10.1145/1013235.1013305","DOIUrl":"https://doi.org/10.1145/1013235.1013305","url":null,"abstract":"This paper compares different receiver architectures for UWB radio communication in the 3.1-5GHz band, targeting data rates up to 10Mbps, in terms of their BER performance and power consumption. A receiver, in which some correlations are carried out in the analog domain seems to outperform a fully digital receiver, commonly suggested for baseband UWB. This paper proves that for equal processing gain requirements the partially analog receiver consumes 7 times less power per received bit than the fully digital one.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127728451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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