Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415583
Changning Luo, Jianping Hu
This paper presents an improved single-phase adiabatic circuit for CAL (Clocked Adiabatic Logic). In the improved CAL circuits, the auxiliary clock uses the sinusoidal wave to recycle the charge of auxiliary clock lines, while the auxiliary clock of conventional CAL circuits adopts the square wave. Pre-adiabatic flip-flops and sequential circuits based on improved CAL circuits are proposed. With TSMC 0.18 mum CMOS process, the energy loss of the proposed circuits is greatly reduced compared to the conventional CAL circuits and the CMOS implementation.
{"title":"Single-phase adiabatic flip-flops and sequential circuits using improved CAL circuits","authors":"Changning Luo, Jianping Hu","doi":"10.1109/ICASIC.2007.4415583","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415583","url":null,"abstract":"This paper presents an improved single-phase adiabatic circuit for CAL (Clocked Adiabatic Logic). In the improved CAL circuits, the auxiliary clock uses the sinusoidal wave to recycle the charge of auxiliary clock lines, while the auxiliary clock of conventional CAL circuits adopts the square wave. Pre-adiabatic flip-flops and sequential circuits based on improved CAL circuits are proposed. With TSMC 0.18 mum CMOS process, the energy loss of the proposed circuits is greatly reduced compared to the conventional CAL circuits and the CMOS implementation.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124814129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 2.5-Gb/s current-mode logic (CML) transceiver is implemented in 0.13 - mum CMOS technology for serial inter-chip interconnection. To compensate the channel attenuation and other impairments, pre-emphasis circuit is included at the transmitter and equalizer at the receiver. 6-GHz 3 dB bandwidth is achieved through the use of active inductors instead of online spiral inductors. DC offset compensate circuits are employed in the output and input buffers to keep the common mode voltage stable. Layout simulation demonstrates the effectiveness of the transceiver. This transceiver consumes only 160 mw of power with 2.5v power supply. The die area of transmitter and receiver are 0.015 mm2, 0.01 mm2 respectively. The transceiver can be operated at 2.5-Gb/s with 100 mv receiver sensitivity.
{"title":"A 2.5-Gb/s 0.13-μm CMOS current mode logic transceiver with pre-emphasis and equalization","authors":"Zhenyu Zhao, Jianjun Wang, Shaoqing Li, Jihua Chen","doi":"10.1109/ICASIC.2007.4415643","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415643","url":null,"abstract":"A 2.5-Gb/s current-mode logic (CML) transceiver is implemented in 0.13 - mum CMOS technology for serial inter-chip interconnection. To compensate the channel attenuation and other impairments, pre-emphasis circuit is included at the transmitter and equalizer at the receiver. 6-GHz 3 dB bandwidth is achieved through the use of active inductors instead of online spiral inductors. DC offset compensate circuits are employed in the output and input buffers to keep the common mode voltage stable. Layout simulation demonstrates the effectiveness of the transceiver. This transceiver consumes only 160 mw of power with 2.5v power supply. The die area of transmitter and receiver are 0.015 mm2, 0.01 mm2 respectively. The transceiver can be operated at 2.5-Gb/s with 100 mv receiver sensitivity.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126086296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415578
Na Bai, Fang Lu, Jim Yang, Longxing Shi
System simulations seek to strike a balance between accuracy and performance. This paper elaborates on the realization of a system simulator. The SystemC-based platform provides the simulation environment for the target application and the cycle-accurate performance evaluation for the optimization methodology. Compared with the result of the actual prototyping simulation, the maximal evaluation error of the simulator is less than 0.02% and the simulating speed is 800 times faster than actual prototyping simulation.
{"title":"Design and realization of a system simulator","authors":"Na Bai, Fang Lu, Jim Yang, Longxing Shi","doi":"10.1109/ICASIC.2007.4415578","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415578","url":null,"abstract":"System simulations seek to strike a balance between accuracy and performance. This paper elaborates on the realization of a system simulator. The SystemC-based platform provides the simulation environment for the target application and the cycle-accurate performance evaluation for the optimization methodology. Compared with the result of the actual prototyping simulation, the maximal evaluation error of the simulator is less than 0.02% and the simulating speed is 800 times faster than actual prototyping simulation.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125265007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415858
Haohang Su, Yimen Zhang, Yuming Zhang, Jincai Man
An effective method is proposed based on compressed BiCGStab approaches to perform static and transient simulations for large-scale power and ground network circuits and a good result is obtained. Extensive experimental results on large-scale power and ground network show that presented method is over two orders faster than HSPICE in transient simulations. Furthermore, our algorithm reduces over 95% of memory usage than HSPICE and 75% of memory usage than ICCG while the accuracy is not compromised.
{"title":"A compressed BiCGStab algorithm for power and ground network analysis","authors":"Haohang Su, Yimen Zhang, Yuming Zhang, Jincai Man","doi":"10.1109/ICASIC.2007.4415858","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415858","url":null,"abstract":"An effective method is proposed based on compressed BiCGStab approaches to perform static and transient simulations for large-scale power and ground network circuits and a good result is obtained. Extensive experimental results on large-scale power and ground network show that presented method is over two orders faster than HSPICE in transient simulations. Furthermore, our algorithm reduces over 95% of memory usage than HSPICE and 75% of memory usage than ICCG while the accuracy is not compromised.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125417633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415562
Liu Hong-jin, Shao Yang, Zhang Tie-jun, Wang Dong-hui, Hou Chao-huan
A highly efficient VLSI architecture for the (9/7) 2-D DWT based on a lifting scheme is presented in the paper. The proposed architecture processes the row and column transforms simultaneously, eliminates the memory buffer for the column transform coefficients. The hardware utilization is improved up to 100% by processing two independent data streams together using shared arithmetic functional blocks. And the embedded boundary extension circuit is exploited to optimize the architecture. Compared to previous architectures, the proposed architecture has more efficiency on critical path, power consumption, temporal storage usage and hardware utilization.
{"title":"A novel VLSI architecture for 2-D discrete wavelet transform","authors":"Liu Hong-jin, Shao Yang, Zhang Tie-jun, Wang Dong-hui, Hou Chao-huan","doi":"10.1109/ICASIC.2007.4415562","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415562","url":null,"abstract":"A highly efficient VLSI architecture for the (9/7) 2-D DWT based on a lifting scheme is presented in the paper. The proposed architecture processes the row and column transforms simultaneously, eliminates the memory buffer for the column transform coefficients. The hardware utilization is improved up to 100% by processing two independent data streams together using shared arithmetic functional blocks. And the embedded boundary extension circuit is exploited to optimize the architecture. Compared to previous architectures, the proposed architecture has more efficiency on critical path, power consumption, temporal storage usage and hardware utilization.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125689078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An adaptive slope compensation circuit applied to buck DC-DC converters is presented in this paper. Based on the basic theory of slope compensation, the conditional expression of the loop stability is gained. According to the conditional expression, using feed-forward control of the input voltage and the feed-back control of the output voltage, the slope compensation is provided with adaptivity, which makes the system stable with the variation of duty cycle all the time. In addition, the proposed slope compensation circuit improves the system's loading capacity and transient response in high duty cycle. The circuit is designed on the base of Samsung BCH4 process, and its performances have been verified by Hspice simulation.
{"title":"An adaptive slope compensation circuit for buck DC-DC converter","authors":"Yanming Li, Xinquan Lai, Chen Fuji, Yuan Bing, Xinzhang Jia","doi":"10.1109/ICASIC.2007.4415704","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415704","url":null,"abstract":"An adaptive slope compensation circuit applied to buck DC-DC converters is presented in this paper. Based on the basic theory of slope compensation, the conditional expression of the loop stability is gained. According to the conditional expression, using feed-forward control of the input voltage and the feed-back control of the output voltage, the slope compensation is provided with adaptivity, which makes the system stable with the variation of duty cycle all the time. In addition, the proposed slope compensation circuit improves the system's loading capacity and transient response in high duty cycle. The circuit is designed on the base of Samsung BCH4 process, and its performances have been verified by Hspice simulation.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127036673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents two components of an indirect modulation transmitter: a low-cost pseudo-Gaussian filter (PGF) and a modified third-order sigma-delta modulator (SDM) for WLAN 802.11a/b/g or Bluetooth. The PGF is a Gaussian filter quantized with 4 bits and is implemented using look up table method. The SDM is a modified feed forward third order modulator with local feedback to enhance signal-to-noise ratio (SNR). With a reference clock of 16 Mhz frequency, the components are designed to work at a transmission rate of up to 1 Msymbols/s. Simulation results show that the circuits work well and the noise is less than -90 dB at 3 Mhz offset frequency. The combination of the two circuits is implemented in 0.18-um CMOS technology, occupying an area of 147 um X 147 um.
本文介绍了间接调制发射机的两个组成部分:用于WLAN 802.11a/b/g或蓝牙的低成本伪高斯滤波器(PGF)和改进的三阶sigma-delta调制器(SDM)。PGF是一个量子化的4位高斯滤波器，采用查表法实现。SDM是一种改进的前馈三阶调制器，具有局部反馈以提高信噪比。参考时钟频率为16mhz，这些组件被设计成以高达1msymbols /s的传输速率工作。仿真结果表明，该电路工作良好，在3mhz偏置频率下噪声小于-90 dB。两个电路的组合采用0.18 um CMOS技术实现，占用147 um X 147 um的面积。
{"title":"A pseudo-Gaussian filter and sigma-delta modulator for IEEE 802.11a/b/g transmitter","authors":"Chenchang Zhan, Shiwei Cheng, Xiaofang Zhou, Dian Zhou","doi":"10.1109/ICASIC.2007.4415650","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415650","url":null,"abstract":"This paper presents two components of an indirect modulation transmitter: a low-cost pseudo-Gaussian filter (PGF) and a modified third-order sigma-delta modulator (SDM) for WLAN 802.11a/b/g or Bluetooth. The PGF is a Gaussian filter quantized with 4 bits and is implemented using look up table method. The SDM is a modified feed forward third order modulator with local feedback to enhance signal-to-noise ratio (SNR). With a reference clock of 16 Mhz frequency, the components are designed to work at a transmission rate of up to 1 Msymbols/s. Simulation results show that the circuits work well and the noise is less than -90 dB at 3 Mhz offset frequency. The combination of the two circuits is implemented in 0.18-um CMOS technology, occupying an area of 147 um X 147 um.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116024429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415780
Kun Wang, Huaxi Gu, Changshan Wang
Direct Interconnection networks have been employed in network on chip (NoC). Provision of quality of service(QoS) in direct Interconnection networks is a challenging problem and receives much attention recently. Traditional switching mechanisms such as, store and forward, wormhole switching, and virtual cut-through switching cannot meet QoS demands for real-time applications in NoC. To solve such problem, we study a hybrid switching mechanism which can guarantee the quality of service for the real-time applications. The implementation is discussed in details and simulated by OPNET software under various traffic loads. The results show that the hybrid switching can provide good performance for real-time applications compared with that of the traditional single switching mechanism.
{"title":"Study on hybrid switching mechanism in network on chip","authors":"Kun Wang, Huaxi Gu, Changshan Wang","doi":"10.1109/ICASIC.2007.4415780","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415780","url":null,"abstract":"Direct Interconnection networks have been employed in network on chip (NoC). Provision of quality of service(QoS) in direct Interconnection networks is a challenging problem and receives much attention recently. Traditional switching mechanisms such as, store and forward, wormhole switching, and virtual cut-through switching cannot meet QoS demands for real-time applications in NoC. To solve such problem, we study a hybrid switching mechanism which can guarantee the quality of service for the real-time applications. The implementation is discussed in details and simulated by OPNET software under various traffic loads. The results show that the hybrid switching can provide good performance for real-time applications compared with that of the traditional single switching mechanism.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114501897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415857
Xiaochun Li, J. Mao, W. Yin
Based on Fourier series analysis, an analytical model of dynamic power of distributed RLC trees is presented. In the model, the dynamic power consumption is approximated by the summation of the first several odd-order components. Each component is calculated by an iterative algorithm of the input admittance function of the tree with no approximation. The error of the model with five components is less than 5% and arbitrarily desired accurate results can be obtained by including appropriate number of components. The model is significantly much faster than SPICE and its computation complexity is linear with the number of components and branches in the tree.
{"title":"Dynamic power consumption of distributed RLC trees","authors":"Xiaochun Li, J. Mao, W. Yin","doi":"10.1109/ICASIC.2007.4415857","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415857","url":null,"abstract":"Based on Fourier series analysis, an analytical model of dynamic power of distributed RLC trees is presented. In the model, the dynamic power consumption is approximated by the summation of the first several odd-order components. Each component is calculated by an iterative algorithm of the input admittance function of the tree with no approximation. The error of the model with five components is less than 5% and arbitrarily desired accurate results can be obtained by including appropriate number of components. The model is significantly much faster than SPICE and its computation complexity is linear with the number of components and branches in the tree.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114591832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICASIC.2007.4415595
C. Huang, Y.H. Yang, D. Huang, Y.Z. Xu, Y.F. Zhao, D. Bai, J. Xu, D.G. Liu, G.H. Li, R. Yang, P. Xu
With the announcement of Intel and IBM to provide 45 nm CPUs, the semiconductor industry has been engaged in the research and development work of 32 nm node CMOS technology. In this paper, we present our development work on the design theory and fabrication process integration of 32 nm node Ge, Si and Si1-xGex "vertical dual carrier field effect transistor" (VDCFET) ASIC for switching and small signal communication applications. The effective channel length of our 32 nm node Ge, Si and Si1-xGex switching VDCFET have been reduced to 9 nm. The effective channel length of our 32 nm node Ge, Si and Si1-xGex communication small signal VDCFET has been reduced to 5 nm. The merits of these Ge, Si and Si1-xGex 32 nm node VDCFET shall be compared.
{"title":"Design theory and fabrication process integration of 32nm node Si, Ge and Si1-xGex vertical dual carrier field effect transistor SOC for switching and communication applications","authors":"C. Huang, Y.H. Yang, D. Huang, Y.Z. Xu, Y.F. Zhao, D. Bai, J. Xu, D.G. Liu, G.H. Li, R. Yang, P. Xu","doi":"10.1109/ICASIC.2007.4415595","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415595","url":null,"abstract":"With the announcement of Intel and IBM to provide 45 nm CPUs, the semiconductor industry has been engaged in the research and development work of 32 nm node CMOS technology. In this paper, we present our development work on the design theory and fabrication process integration of 32 nm node Ge, Si and Si<sub>1-x</sub>Ge<sub>x</sub> \"vertical dual carrier field effect transistor\" (VDCFET) ASIC for switching and small signal communication applications. The effective channel length of our 32 nm node Ge, Si and Si<sub>1-x</sub>Ge<sub>x</sub> switching VDCFET have been reduced to 9 nm. The effective channel length of our 32 nm node Ge, Si and Si<sub>1-x</sub>Ge<sub>x</sub> communication small signal VDCFET has been reduced to 5 nm. The merits of these Ge, Si and Si<sub>1-x</sub>Ge<sub>x</sub> 32 nm node VDCFET shall be compared.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117100405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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