Pub Date : 2009-11-01DOI: 10.1109/ICSCS.2009.5412527
S. B. Attia, S. Salhi, M. Ksouri, J. Bernussou
This paper concerns dynamic output feedback design of discrete-time linear switched systems using switched Lyapunov functions (SLF). A new characterization of stability H∞ performance for the switched system under arbitrary switching is first given. The various conditions are given through a family of LMI (linear matrix inequalities) parameterized by a scalar variable which offers an additional degree of freedom, enabling, at the expense of a relatively small degree of complexity in the numerical treatment (one line search), to provide better results compared to previous results. The control is defined as a switched dynamic output feedback which guarantees stability and H∞ performance for the closed-loop system. A numerical example is presented to illustrate the effectiveness of the proposed conditions.
{"title":"Improved LMI formulation for robust dynamic output feedback controller design of discrete-time switched systems via switched Lyapunov function","authors":"S. B. Attia, S. Salhi, M. Ksouri, J. Bernussou","doi":"10.1109/ICSCS.2009.5412527","DOIUrl":"https://doi.org/10.1109/ICSCS.2009.5412527","url":null,"abstract":"This paper concerns dynamic output feedback design of discrete-time linear switched systems using switched Lyapunov functions (SLF). A new characterization of stability H∞ performance for the switched system under arbitrary switching is first given. The various conditions are given through a family of LMI (linear matrix inequalities) parameterized by a scalar variable which offers an additional degree of freedom, enabling, at the expense of a relatively small degree of complexity in the numerical treatment (one line search), to provide better results compared to previous results. The control is defined as a switched dynamic output feedback which guarantees stability and H∞ performance for the closed-loop system. A numerical example is presented to illustrate the effectiveness of the proposed conditions.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114091771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/ICSCS.2009.5412569
C. Majek, R. Severino, T. Taris, Y. Deval, A. Mariano, J. Bégueret, D. Belot
This paper presents a comparative study between two mm-wave technologies from STMicroelectronics: 130 nm BiCMOS and 65 nm CMOS-SOI, through the implementation of a single stage LNA at 60 GHz. Both distributed and lumped design approaches are investigated to work out the best trade-off between silicon saving and performances. The two circuits achieve respectively 12 dB and 6 dB gain, 3.6 dB and 4.5 dB noise figure under 2.5V and 1.2V supply voltage for BiCMOS9MW and CMOS-SOI technologies. The LNA are based on cascode topology with a specific interstage matching for ft and fmax improvement. The current density and transistor sizing are set to perform the lowest NF at 60 GHz, the current consumption is 3.7 mA and 13 mA for BiCMOS9MW and CMOS-SOI LNA respectively.
{"title":"60 GHz cascode LNA with interstage matching: performance comparison between 130nm BiCMOS and 65nm CMOS-SOI technologies","authors":"C. Majek, R. Severino, T. Taris, Y. Deval, A. Mariano, J. Bégueret, D. Belot","doi":"10.1109/ICSCS.2009.5412569","DOIUrl":"https://doi.org/10.1109/ICSCS.2009.5412569","url":null,"abstract":"This paper presents a comparative study between two mm-wave technologies from STMicroelectronics: 130 nm BiCMOS and 65 nm CMOS-SOI, through the implementation of a single stage LNA at 60 GHz. Both distributed and lumped design approaches are investigated to work out the best trade-off between silicon saving and performances. The two circuits achieve respectively 12 dB and 6 dB gain, 3.6 dB and 4.5 dB noise figure under 2.5V and 1.2V supply voltage for BiCMOS9MW and CMOS-SOI technologies. The LNA are based on cascode topology with a specific interstage matching for ft and fmax improvement. The current density and transistor sizing are set to perform the lowest NF at 60 GHz, the current consumption is 3.7 mA and 13 mA for BiCMOS9MW and CMOS-SOI LNA respectively.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114795599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/ICSCS.2009.5412232
H. Gottlob, M. Schmidt, H. Kurz
In this work we present a gate-first process platform for device integration of gadolinium (Gd) based high-k dielectrics and metal gate electrodes. Epitaxial Gd2O3 and GdSiO high-k layers have been integrated with titanium nitride (TiN) gates. Thermal stability of the gate stacks is investigated in detail. Especially the metal inserted polysilicon approach using TiN enables high temperature processing.
{"title":"Gate-first integration of Gd-based high-k dielectrics with metal gate electrodes","authors":"H. Gottlob, M. Schmidt, H. Kurz","doi":"10.1109/ICSCS.2009.5412232","DOIUrl":"https://doi.org/10.1109/ICSCS.2009.5412232","url":null,"abstract":"In this work we present a gate-first process platform for device integration of gadolinium (Gd) based high-k dielectrics and metal gate electrodes. Epitaxial Gd2O3 and GdSiO high-k layers have been integrated with titanium nitride (TiN) gates. Thermal stability of the gate stacks is investigated in detail. Especially the metal inserted polysilicon approach using TiN enables high temperature processing.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123880839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/ICSCS.2009.5414158
M. L. Tounsi, M. Yagoub
This paper deals with the analysis of anisotropy effects on the dispersion parameters of multilayer microwave circuits with ferrite substrates. Since ferrites present a biaxial anisotropy, spectral analysis of multilayered configurations with such substrates is not generalized yet but restricted to some particular cases of tensors. The proposed general analysis was carried out by the spectral domain approach method (S.D.A) and takes into account for the first time the electrical aspect of anisotropy. The computed results are in good agreement with those available in the literature.
{"title":"Spectral-domain modeling of anisotropy in ferrite microwave circuits with multilayer configuration","authors":"M. L. Tounsi, M. Yagoub","doi":"10.1109/ICSCS.2009.5414158","DOIUrl":"https://doi.org/10.1109/ICSCS.2009.5414158","url":null,"abstract":"This paper deals with the analysis of anisotropy effects on the dispersion parameters of multilayer microwave circuits with ferrite substrates. Since ferrites present a biaxial anisotropy, spectral analysis of multilayered configurations with such substrates is not generalized yet but restricted to some particular cases of tensors. The proposed general analysis was carried out by the spectral domain approach method (S.D.A) and takes into account for the first time the electrical aspect of anisotropy. The computed results are in good agreement with those available in the literature.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116968061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/ICSCS.2009.5412594
N. M. Ismail, M. Othman
This paper presents 4-bit integer N CMOS programmable frequency divider with high speed and low power consumption. It is based on a 15/16 dual-modulus prescaler, and programmable asynchronous and synchronous dividers. It works up to 3.4 GHz frequency clock and consumes 0.7 mW. It is tested in PLL for 2.4GHz band Zigbee standard. All results are taken from simulating extracted layout. It is implemented using Silterra 0.18-µm CMOS process, and voltage supply 1.8V.
{"title":"CMOS programmable divider for Zigbee frequency synthesizer","authors":"N. M. Ismail, M. Othman","doi":"10.1109/ICSCS.2009.5412594","DOIUrl":"https://doi.org/10.1109/ICSCS.2009.5412594","url":null,"abstract":"This paper presents 4-bit integer N CMOS programmable frequency divider with high speed and low power consumption. It is based on a 15/16 dual-modulus prescaler, and programmable asynchronous and synchronous dividers. It works up to 3.4 GHz frequency clock and consumes 0.7 mW. It is tested in PLL for 2.4GHz band Zigbee standard. All results are taken from simulating extracted layout. It is implemented using Silterra 0.18-µm CMOS process, and voltage supply 1.8V.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117193614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/ICSCS.2009.5412578
S. B. Chaabane, F. Fnaiech, M. Sayadi, E. Brassart
This paper describes a new color image segmentation method based on data fusion techniques. The used methodology modeling in the Dempster-Shafer evidence theory is in general successful, for representing the information extracted from image as measures of belief. The proposed method addresses the information modelization problem and the color image segmentation within the context of Dempster-Shafer theory. The mass functions are computed from the probability that a pixel belong to a region. The mass functions are then combined with the Dempster rules of combination, and the maximum of mass function is used for decision-making. The computation of conflict between images, the modelization of both uncertainty and imprecision, the possible introduction of a priori information, witch are powerful aspects of the evidence theory and witch have a great influence on the final decision, are exploited in color image segmentation. We present quantitative and comparative results concerning color medical images.
{"title":"Relevance of the Dempster-Shafer evidence theory for image segmentation","authors":"S. B. Chaabane, F. Fnaiech, M. Sayadi, E. Brassart","doi":"10.1109/ICSCS.2009.5412578","DOIUrl":"https://doi.org/10.1109/ICSCS.2009.5412578","url":null,"abstract":"This paper describes a new color image segmentation method based on data fusion techniques. The used methodology modeling in the Dempster-Shafer evidence theory is in general successful, for representing the information extracted from image as measures of belief. The proposed method addresses the information modelization problem and the color image segmentation within the context of Dempster-Shafer theory. The mass functions are computed from the probability that a pixel belong to a region. The mass functions are then combined with the Dempster rules of combination, and the maximum of mass function is used for decision-making. The computation of conflict between images, the modelization of both uncertainty and imprecision, the possible introduction of a priori information, witch are powerful aspects of the evidence theory and witch have a great influence on the final decision, are exploited in color image segmentation. We present quantitative and comparative results concerning color medical images.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115142890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/ICSCS.2009.5412597
Houssem Maghrebi, J. Danger, Florent Flament, S. Guilley, L. Sauvage
This paper presents hardware implementations of a DES cryptoprocessor with masking countermeasures and their evaluation against side-channel attacks (SCAs) in FPGAs. The masking protection has been mainly studied from a theoretical viewpoint without any thorough test in a noisy real world designs. In this study the masking countermeasure is tested with first-order and higher-order SCAs on a fully-fledged DES. Beside a classical implementation of the DES substitution boxes (S-Boxes) a simple structure called Universal Substitution boxes with Masking (USM) is proposed. It meets the constraint of low complexity as state-of-the-art masked S-Boxes are mostly built from large look-up tables or complex calculations with combinatorial logic gates. However attacks on USM has underlined some security weaknesses. ROM masked implementation exhibits greater robustness as it cannot be attacked with first-order DPA. Nevertheless any masking implementation remains sensitive to Higher-Order Differential Power Analysis (HO-DPA) as shown in a proposed attack. This attack is based on a variance analysis of the observed power consumption and it clearly shows the vulnerabilities of masking countermeasures.
{"title":"Evaluation of countermeasure implementations based on Boolean masking to thwart side-channel attacks","authors":"Houssem Maghrebi, J. Danger, Florent Flament, S. Guilley, L. Sauvage","doi":"10.1109/ICSCS.2009.5412597","DOIUrl":"https://doi.org/10.1109/ICSCS.2009.5412597","url":null,"abstract":"This paper presents hardware implementations of a DES cryptoprocessor with masking countermeasures and their evaluation against side-channel attacks (SCAs) in FPGAs. The masking protection has been mainly studied from a theoretical viewpoint without any thorough test in a noisy real world designs. In this study the masking countermeasure is tested with first-order and higher-order SCAs on a fully-fledged DES. Beside a classical implementation of the DES substitution boxes (S-Boxes) a simple structure called Universal Substitution boxes with Masking (USM) is proposed. It meets the constraint of low complexity as state-of-the-art masked S-Boxes are mostly built from large look-up tables or complex calculations with combinatorial logic gates. However attacks on USM has underlined some security weaknesses. ROM masked implementation exhibits greater robustness as it cannot be attacked with first-order DPA. Nevertheless any masking implementation remains sensitive to Higher-Order Differential Power Analysis (HO-DPA) as shown in a proposed attack. This attack is based on a variance analysis of the observed power consumption and it clearly shows the vulnerabilities of masking countermeasures.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123502736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/MMS.2009.5409817
S. Tedjini, S. Gaoua, R. Touhami, M. Yagoub, A. Bellaouar
In this paper, an improved version of the digital calibration method for carrier leakage, which is caused by the DC offset on direct conversion transmitter, is proposed. We have used a power detector for estimating the DC offset. After, we have injected a compensation voltage for eliminating this DC offset. In order to validate our technique, a new direct conversion transmitter that operates at 2GHz, is proposed. The simulation and the implementation of the calibration were performed using the Agilent - ADS software.
{"title":"Carrier leakage calibration in DCT","authors":"S. Tedjini, S. Gaoua, R. Touhami, M. Yagoub, A. Bellaouar","doi":"10.1109/MMS.2009.5409817","DOIUrl":"https://doi.org/10.1109/MMS.2009.5409817","url":null,"abstract":"In this paper, an improved version of the digital calibration method for carrier leakage, which is caused by the DC offset on direct conversion transmitter, is proposed. We have used a power detector for estimating the DC offset. After, we have injected a compensation voltage for eliminating this DC offset. In order to validate our technique, a new direct conversion transmitter that operates at 2GHz, is proposed. The simulation and the implementation of the calibration were performed using the Agilent - ADS software.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127589128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/ICSCS.2009.5412541
Bumman Kim, Jinsung Choi, D. Kang, Dongsu Kim
This paper presents an optimized envelope tracking operation of Doherty amplifier. By modulating the supply voltage of the carrier amplifier, while that of the peaking amplifier is fixed, the supply modulator provides just a half of the current for the same PA output power. It results in a reduced chip size and the crest factor of the supply modulating signal is reduced by 6dB, enhancing the efficiency of the supply modulator. The designed ET transmitter consisting of the Doherty amplifier and the supply modulator are fabricated in 2um HBT and 0.13um CMOS processes, respectively. It presents the efficiency improvement over a broad output power region. Especially, at the 16dB backed off power level, more than 23% of PAE is achieved. For WiBro application, it shows the PAE of 38.6% at the output power of 24.22dBm with the gain of 24.62dB. The EVM is 3.64%.
{"title":"Optimized envelope tracking operation of Doherty power amplifier","authors":"Bumman Kim, Jinsung Choi, D. Kang, Dongsu Kim","doi":"10.1109/ICSCS.2009.5412541","DOIUrl":"https://doi.org/10.1109/ICSCS.2009.5412541","url":null,"abstract":"This paper presents an optimized envelope tracking operation of Doherty amplifier. By modulating the supply voltage of the carrier amplifier, while that of the peaking amplifier is fixed, the supply modulator provides just a half of the current for the same PA output power. It results in a reduced chip size and the crest factor of the supply modulating signal is reduced by 6dB, enhancing the efficiency of the supply modulator. The designed ET transmitter consisting of the Doherty amplifier and the supply modulator are fabricated in 2um HBT and 0.13um CMOS processes, respectively. It presents the efficiency improvement over a broad output power region. Especially, at the 16dB backed off power level, more than 23% of PAE is achieved. For WiBro application, it shows the PAE of 38.6% at the output power of 24.22dBm with the gain of 24.62dB. The EVM is 3.64%.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130037471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/ICSCS.2009.5414185
A. Brambilla, G. Gruosso, G. S. Gajani
In this paper the harmonic balance method is considered in conjunction with the probe insertion technique. In general, the nonlinear equations modeling the circuit in the frequency domain are solved with the Newton iterative method. Conventional probe insertion technique has become popular and implemented in commercial analog simulators, since in many cases it shows better convergence behaviour of the Newton method and, therefore, of the harmonic balance one applied to autonomous circuits. The conventional probe technique, which is based on the insertion of a single probe, is here considered in detail, improved and extended through the insertion of two distinct probes working at two different frequencies with non necessarily an integer ratio. This improved version is exploited to compute the steady state working condition of coupled oscillators that operate in a pulling condition and that can switch to a locking one according to variations of circuit parameters.
{"title":"Multi-probe harmonic balance method to simulate coupled oscillators","authors":"A. Brambilla, G. Gruosso, G. S. Gajani","doi":"10.1109/ICSCS.2009.5414185","DOIUrl":"https://doi.org/10.1109/ICSCS.2009.5414185","url":null,"abstract":"In this paper the harmonic balance method is considered in conjunction with the probe insertion technique. In general, the nonlinear equations modeling the circuit in the frequency domain are solved with the Newton iterative method. Conventional probe insertion technique has become popular and implemented in commercial analog simulators, since in many cases it shows better convergence behaviour of the Newton method and, therefore, of the harmonic balance one applied to autonomous circuits. The conventional probe technique, which is based on the insertion of a single probe, is here considered in detail, improved and extended through the insertion of two distinct probes working at two different frequencies with non necessarily an integer ratio. This improved version is exploited to compute the steady state working condition of coupled oscillators that operate in a pulling condition and that can switch to a locking one according to variations of circuit parameters.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121367186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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