Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524869
Maryna Miroshnyk, Sergii Poroshyn, A. Shkil, E. Kulak, I. Filippenko, D. Kucherenko, Yuriy Pakhomov, Salfetnikova Juliia, M. Goga
In this work it is offered to use patterns of automata-based programming for designing logical control devices on the basis of finite state machines. To describe the functioning algorithm of the automatic logical control device, it is suggested to use the temporal state diagram, which takes into account real time delays for each states of finite states machine. During designing a state machine based on FPGA platform, the functioning algorithm is described in the VHDL hardware description language, and the device is synthesized in the CAD XILINX ISE, and, when the design of finite state machine based on the microcontroller (family MCS 51), the functioning algorithm is described on the subset of the C language using the Keil development tool.
{"title":"Design of Logical Control Units Based on Finite State Machines' Patterns","authors":"Maryna Miroshnyk, Sergii Poroshyn, A. Shkil, E. Kulak, I. Filippenko, D. Kucherenko, Yuriy Pakhomov, Salfetnikova Juliia, M. Goga","doi":"10.1109/EWDTS.2018.8524869","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524869","url":null,"abstract":"In this work it is offered to use patterns of automata-based programming for designing logical control devices on the basis of finite state machines. To describe the functioning algorithm of the automatic logical control device, it is suggested to use the temporal state diagram, which takes into account real time delays for each states of finite states machine. During designing a state machine based on FPGA platform, the functioning algorithm is described in the VHDL hardware description language, and the device is synthesized in the CAD XILINX ISE, and, when the design of finite state machine based on the microcontroller (family MCS 51), the functioning algorithm is described on the subset of the C language using the Keil development tool.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524803
A. Ogurtsov, M. Krasnov, O. Martynov
The article describes various approaches to the functional tests used by the independent test laboratories for incoming inspection of FPGAs used in the aerospace industry. Proposed solution is based on the various approaches to the functional test, such as methods Iterative Logic Arrays (ILA) used together with automated test equipment (ATE) for testing internal programmable logic of the FPGA, as well as the Built-in Self- Test BIST approaches used for testing embedded FPGA cores. Described functional tests are used for confirmation that FPGAs are fault-free and can be used in the developed equipment.
{"title":"Incoming Inspection of FPGAs","authors":"A. Ogurtsov, M. Krasnov, O. Martynov","doi":"10.1109/EWDTS.2018.8524803","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524803","url":null,"abstract":"The article describes various approaches to the functional tests used by the independent test laboratories for incoming inspection of FPGAs used in the aerospace industry. Proposed solution is based on the various approaches to the functional test, such as methods Iterative Logic Arrays (ILA) used together with automated test equipment (ATE) for testing internal programmable logic of the FPGA, as well as the Built-in Self- Test BIST approaches used for testing embedded FPGA cores. Described functional tests are used for confirmation that FPGAs are fault-free and can be used in the developed equipment.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114425451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524693
Mahroo Zandrahimi, P. Debaud, Armand Castillejo, Z. Al-Ars
Application of manufacturing testing during the production process of integrated circuits is considered essential to ensure the quality of the devices used in the field. However, it is desirable to use the information gathered during the test process to add value to other aspects of the manufacturing process. This paper proposes a method to use path delay (PDLY) test patterns, not only to validate the functionality of the devices, but also as an alternative solution for performance estimation, that can be used for offline adaptive voltage scaling. This approach has many advantages over the currently used industrial performance estimation methods, so-called performance monitoring boxes (PMBs). Using simulation of ISCAS'99 benchmarks with 28nm FD-SOI libraries, the paper shows that the PDLY based approach reduces the inaccuracy of performance prediction from 2.32% (achieved by the classic PMB approach) to 1.85%, without the need for any on-chip monitors.
{"title":"Cost Effective Adaptive Voltage Scaling Using Path Delay Fault Testing","authors":"Mahroo Zandrahimi, P. Debaud, Armand Castillejo, Z. Al-Ars","doi":"10.1109/EWDTS.2018.8524693","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524693","url":null,"abstract":"Application of manufacturing testing during the production process of integrated circuits is considered essential to ensure the quality of the devices used in the field. However, it is desirable to use the information gathered during the test process to add value to other aspects of the manufacturing process. This paper proposes a method to use path delay (PDLY) test patterns, not only to validate the functionality of the devices, but also as an alternative solution for performance estimation, that can be used for offline adaptive voltage scaling. This approach has many advantages over the currently used industrial performance estimation methods, so-called performance monitoring boxes (PMBs). Using simulation of ISCAS'99 benchmarks with 28nm FD-SOI libraries, the paper shows that the PDLY based approach reduces the inaccuracy of performance prediction from 2.32% (achieved by the classic PMB approach) to 1.85%, without the need for any on-chip monitors.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114919087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524689
S. Kalabanov, R. Shagiev, R. Ishmuratov
The article describes an automated system of remote data collection from industrial machines at enterprises for the purpose of operative control of equipment loading (utilization rate) and analysis of the reasons for their idle time, as well as the measurement of power consumption. The data transmission system is based on Power Line Communication (data transmission via power lines). The principle of system construction is considered, its remote (peripheral) devices and the central control unit are described. The structural-functional diagrams, main technical characteristics and features of hardware and software implementation of the developed devices of the data acquisition system are given.
{"title":"Automated Data Acquisition System from Industrial Machines","authors":"S. Kalabanov, R. Shagiev, R. Ishmuratov","doi":"10.1109/EWDTS.2018.8524689","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524689","url":null,"abstract":"The article describes an automated system of remote data collection from industrial machines at enterprises for the purpose of operative control of equipment loading (utilization rate) and analysis of the reasons for their idle time, as well as the measurement of power consumption. The data transmission system is based on Power Line Communication (data transmission via power lines). The principle of system construction is considered, its remote (peripheral) devices and the central control unit are described. The structural-functional diagrams, main technical characteristics and features of hardware and software implementation of the developed devices of the data acquisition system are given.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116367715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524709
D. Zaporozhets, D. Zaruba, E. Kuliev
The paper deals with a modified ant algorithm for the determination of critical connections in VLSI using as an example a traveling salesman problem. This algorithm is a part of the swarm intelligence method, which is one of the bioinspired approaches that describe the collective behavior of a decentralized self-organizing system. It consists of a set of agents (ants) interacting with each other and with the environment. The paper presents the statement of the traveling salesman problem. The described modified ant algorithm allows to obtain sets of quasi-optimal solutions in polynomial time. Series of tests and experiments made it possible to specify theoretical estimates of the algorithms' time complexity and their behavior for graphs with different structures. The time complexity is represented as O(nlogn) at the best case, O(n3) at the worst case.
{"title":"Ant Algorithm for Determining of Critical Connections in VLSI","authors":"D. Zaporozhets, D. Zaruba, E. Kuliev","doi":"10.1109/EWDTS.2018.8524709","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524709","url":null,"abstract":"The paper deals with a modified ant algorithm for the determination of critical connections in VLSI using as an example a traveling salesman problem. This algorithm is a part of the swarm intelligence method, which is one of the bioinspired approaches that describe the collective behavior of a decentralized self-organizing system. It consists of a set of agents (ants) interacting with each other and with the environment. The paper presents the statement of the traveling salesman problem. The described modified ant algorithm allows to obtain sets of quasi-optimal solutions in polynomial time. Series of tests and experiments made it possible to specify theoretical estimates of the algorithms' time complexity and their behavior for graphs with different structures. The time complexity is represented as O(nlogn) at the best case, O(n3) at the worst case.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131913442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524754
V. Bogolyubov, L. Bakhtieva
The analysis of the operation of a microelectromechanical system under conditions of parametric modulation of the static stiffness of the rotor in the coherent mode of excitation of its oscillations has carried out. The corresponding mathematical model have constructed, numerical experiments have carried out. Based on this results a method of extending the functional capabilities of navigation devices has proposed.
{"title":"Parametrically Excited Microelectromechanical System in Navigation Problems","authors":"V. Bogolyubov, L. Bakhtieva","doi":"10.1109/EWDTS.2018.8524754","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524754","url":null,"abstract":"The analysis of the operation of a microelectromechanical system under conditions of parametric modulation of the static stiffness of the rotor in the coherent mode of excitation of its oscillations has carried out. The corresponding mathematical model have constructed, numerical experiments have carried out. Based on this results a method of extending the functional capabilities of navigation devices has proposed.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134410980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524746
O. Medvedeva, S. Mustafina
The application of interval analysis methods in the mathematical modeling of technical systems and the solution of the optimal control problem makes it possible to take into account the uncertainty in the initial data. A mathematical model of the xylene isomerization process with interval kinetic parameters was developed. On the basis of the Pontryagin maximum principle, the problem of finding the optimum temperature for the process is solved. A computational experiment was performed to find the dependence of the optimal solution on the variation of the kinetic parameters.
{"title":"Using of Interval Analysis Algorithms for Technical Systems Optimization Problem Solving","authors":"O. Medvedeva, S. Mustafina","doi":"10.1109/EWDTS.2018.8524746","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524746","url":null,"abstract":"The application of interval analysis methods in the mathematical modeling of technical systems and the solution of the optimal control problem makes it possible to take into account the uncertainty in the initial data. A mathematical model of the xylene isomerization process with interval kinetic parameters was developed. On the basis of the Pontryagin maximum principle, the problem of finding the optimum temperature for the process is solved. A computational experiment was performed to find the dependence of the optimal solution on the variation of the kinetic parameters.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133332498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524618
Sergey Masin
Wireless sensor networks (WSN) organized according to the IoT paradigm become more and more claimed in different sectors of economy. Power consumption and time of autonomous operating for wireless sensors are the key factors at designing reliable and sustainable systems. Mathematical models describing different physical and behavior aspects of the WSN play important role at the design automation. The important characteristics for several low-power communication standards and technologies are considered and compared. The features of wireless communication standards such as BLE, ZigBee, SIGFOX and LoRaWAN used for WSN implementation are demonstrated. The model describing the LoRaWAncommunication between end-devices and the network server in the Class A which can be used for the design automation purpose to select the effective architecture of the WSN and lifetime evaluation for the sensors is proposed.
{"title":"A Model of LoRaWAN Communication in Class A for Design Automation of Wireless Sensor Networks Based on the IoT Paradigm","authors":"Sergey Masin","doi":"10.1109/EWDTS.2018.8524618","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524618","url":null,"abstract":"Wireless sensor networks (WSN) organized according to the IoT paradigm become more and more claimed in different sectors of economy. Power consumption and time of autonomous operating for wireless sensors are the key factors at designing reliable and sustainable systems. Mathematical models describing different physical and behavior aspects of the WSN play important role at the design automation. The important characteristics for several low-power communication standards and technologies are considered and compared. The features of wireless communication standards such as BLE, ZigBee, SIGFOX and LoRaWAN used for WSN implementation are demonstrated. The model describing the LoRaWAncommunication between end-devices and the network server in the Class A which can be used for the design automation purpose to select the effective architecture of the WSN and lifetime evaluation for the sensors is proposed.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124645315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524644
N. Levchenko, A. Okunev, D. Zmejev
The article presents one of the problems solved in the design of the parallel dataflow computing system that implements the dataflow computing model with the dynamically formed context. Hardware content addressable memory of the matching processor of this system allows effective implementation of the basic principles of the dataflow computing model and should not be overflowed in the process of solving the task. The reasons that can cause an overflow of the content addressable memory of the PDCS are described, as well as the main options for solving this problem.
{"title":"Solutions to Problem of CAM Overflow in the Parallel Dataflow Computing System “Buran”","authors":"N. Levchenko, A. Okunev, D. Zmejev","doi":"10.1109/EWDTS.2018.8524644","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524644","url":null,"abstract":"The article presents one of the problems solved in the design of the parallel dataflow computing system that implements the dataflow computing model with the dynamically formed context. Hardware content addressable memory of the matching processor of this system allows effective implementation of the basic principles of the dataflow computing model and should not be overflowed in the process of solving the task. The reasons that can cause an overflow of the content addressable memory of the PDCS are described, as well as the main options for solving this problem.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125673584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/EWDTS.2018.8524851
I. Komilov
This research is aimed at the elaboration of a mockup interference canceller in the user's navigation equipment receiver. Such canceller with the help of signals non-linear processing will allow cancelling interferences with a random angular modulation that are much more powerful than navigation signals. The operation of the device being elaborated will consist in a significant increase of the signal/interference ratio at its output. In the end, it will result in the improvement of the navigation receiver immunity to interferences. The article dwells on the issues of the interference canceller realization in a standard navigation receiver by means of the analogue processing. We performed the analysis of the variants of the integration of the device being elaborated in the navigation receiver. The experimental investigation showed that the interference canceller allows increasing the interference-to-signal threshold ratio by 35 dB both for narrow-band and wide-band interference.
{"title":"Design and Test of an Interference Canceller for a GPS/GLONASS User's Navigation Equipment","authors":"I. Komilov","doi":"10.1109/EWDTS.2018.8524851","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524851","url":null,"abstract":"This research is aimed at the elaboration of a mockup interference canceller in the user's navigation equipment receiver. Such canceller with the help of signals non-linear processing will allow cancelling interferences with a random angular modulation that are much more powerful than navigation signals. The operation of the device being elaborated will consist in a significant increase of the signal/interference ratio at its output. In the end, it will result in the improvement of the navigation receiver immunity to interferences. The article dwells on the issues of the interference canceller realization in a standard navigation receiver by means of the analogue processing. We performed the analysis of the variants of the integration of the device being elaborated in the navigation receiver. The experimental investigation showed that the interference canceller allows increasing the interference-to-signal threshold ratio by 35 dB both for narrow-band and wide-band interference.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127173626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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