Pub Date : 2025-06-26DOI: 10.1109/TCSI.2025.3581988
Fujin Jia;Quanxin Zhu
This paper investigates the non-overshooting tracking conditions for n-th order nonlinear systems with unmeasurable states. By designing state observers, the problem of unmeasurable states is addressed. The key to non-overshooting control (OC) is how to design appropriate controller to ensure the system is not only stable but also effectively solves the non-OC problem. Based on backstepping, a square root gain control algorithm is proposed in this paper, which ensures global asymptotic stability of the closed-loop system. Meanwhile, two main conclusions are drawn in non-OC: 1) If the initial values of the system states are equal to the initial values of the observer states, the conditions obtained by the proposed algorithm can achieve non-OC, i.e., the system overshoot is zero. Non-OC conditions for $n=1$ , $n=2$ , $n=3$ , and $ngeq 4$ order systems are obtained, respectively. And the conditions are relatively rich. Therefore, compared with existing algorithms, this algorithm not only ensures zero system overshoot, but also reduces conservatism; 2) If the initial values of the system states are not equal to the initial values of the observer states, the conditions obtained by this algorithm can achieve mean-non-OC, i.e., the system overshoot can be adjusted to any small value. In terms of simulation, the stability performance algorithm, non-OC algorithm, and mean-non-OC algorithm were verified using the mathematical models of the DC servo motor systems and Chua’s circuit system. Simulation results show that these control algorithms are effective. It also compares existing related results, highlighting the superiority of the algorithm presented in this paper.
{"title":"Nonovershooting Tracking Control for Nonlinear Output Feedback Systems With Application to DC Motor","authors":"Fujin Jia;Quanxin Zhu","doi":"10.1109/TCSI.2025.3581988","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3581988","url":null,"abstract":"This paper investigates the non-overshooting tracking conditions for <italic>n</i>-th order nonlinear systems with unmeasurable states. By designing state observers, the problem of unmeasurable states is addressed. The key to non-overshooting control (OC) is how to design appropriate controller to ensure the system is not only stable but also effectively solves the non-OC problem. Based on backstepping, a square root gain control algorithm is proposed in this paper, which ensures global asymptotic stability of the closed-loop system. Meanwhile, two main conclusions are drawn in non-OC: 1) If the initial values of the system states are equal to the initial values of the observer states, the conditions obtained by the proposed algorithm can achieve non-OC, i.e., the system overshoot is zero. Non-OC conditions for <inline-formula> <tex-math>$n=1$ </tex-math></inline-formula>, <inline-formula> <tex-math>$n=2$ </tex-math></inline-formula>, <inline-formula> <tex-math>$n=3$ </tex-math></inline-formula>, and <inline-formula> <tex-math>$ngeq 4$ </tex-math></inline-formula> order systems are obtained, respectively. And the conditions are relatively rich. Therefore, compared with existing algorithms, this algorithm not only ensures zero system overshoot, but also reduces conservatism; 2) If the initial values of the system states are not equal to the initial values of the observer states, the conditions obtained by this algorithm can achieve mean-non-OC, i.e., the system overshoot can be adjusted to any small value. In terms of simulation, the stability performance algorithm, non-OC algorithm, and mean-non-OC algorithm were verified using the mathematical models of the DC servo motor systems and Chua’s circuit system. Simulation results show that these control algorithms are effective. It also compares existing related results, highlighting the superiority of the algorithm presented in this paper.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 12","pages":"8383-8395"},"PeriodicalIF":5.2,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145600706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Load frequency control is essential for maintaining power system stability, especially under uncertainties and input delays. This paper proposes a reinforcement learning-based dual-channel dynamic event-triggered fixed-time load frequency control approach for uncertain multi-area power systems with input delays. A non-singular fast terminal sliding mode technique is employed to guarantee that the tracking error converges within a fixed time. To address system uncertainties and input delays, actor neural networks are designed to estimate the modeling uncertainties and provide compensation, and critic neural networks evaluate execution costs. To further enhance efficiency, a dual-channel event-triggered mechanism is designed, reducing communication overhead through independent dynamic event-triggering strategies for control input and output channels. The stability of the proposed method is rigorously analyzed using the Lyapunov method. Simulation results demonstrate faster convergence, reduced communication costs, and improved frequency stability compared to existing methods.
{"title":"Data-Driven Event-Triggered Fixed-Time Load Frequency Control for Multi-Area Power Systems With Input Delays","authors":"Yuhao Chen;Huarong Zhao;Masaki Ogura;Hongnian Yu;Li Peng","doi":"10.1109/TCSI.2025.3580122","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3580122","url":null,"abstract":"Load frequency control is essential for maintaining power system stability, especially under uncertainties and input delays. This paper proposes a reinforcement learning-based dual-channel dynamic event-triggered fixed-time load frequency control approach for uncertain multi-area power systems with input delays. A non-singular fast terminal sliding mode technique is employed to guarantee that the tracking error converges within a fixed time. To address system uncertainties and input delays, actor neural networks are designed to estimate the modeling uncertainties and provide compensation, and critic neural networks evaluate execution costs. To further enhance efficiency, a dual-channel event-triggered mechanism is designed, reducing communication overhead through independent dynamic event-triggering strategies for control input and output channels. The stability of the proposed method is rigorously analyzed using the Lyapunov method. Simulation results demonstrate faster convergence, reduced communication costs, and improved frequency stability compared to existing methods.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 12","pages":"8492-8504"},"PeriodicalIF":5.2,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145600668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a double-sided Z-configuration-based compensation network for an inductive power transfer (IPT) system for electric vehicles (EVs) with detailed analysis and optimization factors as an alternative to the double-sided LCC configuration. The contributions of the proposed article are as follows: (a) a double-sided Z-compensation configuration is developed, which provides a lower voltage and current stress on the passive components in comparison with double-sided LCC compensation; it has inherent zero phase angle properties for minimizing losses and improving system efficiency; (b) the Z-Z configuration achieves a load-independent constant voltage output and constant transmitting current; (c) additionally, the optimized compensation factors for the primary and secondary sides are derived for maximum inter-coil efficiency. It is evident that fine-tuning the compensation factors can minimize copper losses and ensure high efficiency over a wide load range, achieving up to 93.37% efficiency at optimal conditions. Experimental results from the 1 kW laboratory prototype validate the proposed designs, demonstrating comparable power transfer performance with lower losses and an effective and alternative solution for double-sided LCC-LCC-based higher-power IPT systems.
{"title":"A Symmetrical Impedance Compensation Configuration for Optimized IPT Systems","authors":"Monika Dabkara;P. Saravana Prakash;Arun Kumar Verma","doi":"10.1109/TCSI.2025.3581773","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3581773","url":null,"abstract":"This paper presents a double-sided Z-configuration-based compensation network for an inductive power transfer (IPT) system for electric vehicles (EVs) with detailed analysis and optimization factors as an alternative to the double-sided LCC configuration. The contributions of the proposed article are as follows: (a) a double-sided Z-compensation configuration is developed, which provides a lower voltage and current stress on the passive components in comparison with double-sided LCC compensation; it has inherent zero phase angle properties for minimizing losses and improving system efficiency; (b) the Z-Z configuration achieves a load-independent constant voltage output and constant transmitting current; (c) additionally, the optimized compensation factors for the primary and secondary sides are derived for maximum inter-coil efficiency. It is evident that fine-tuning the compensation factors can minimize copper losses and ensure high efficiency over a wide load range, achieving up to 93.37% efficiency at optimal conditions. Experimental results from the 1 kW laboratory prototype validate the proposed designs, demonstrating comparable power transfer performance with lower losses and an effective and alternative solution for double-sided LCC-LCC-based higher-power IPT systems.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 12","pages":"8505-8513"},"PeriodicalIF":5.2,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145600691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-20DOI: 10.1109/TCSI.2025.3580265
Hongbing Xia;Anders Lindquist;Chaoxu Mu;Changyin Sun
Decentralized secure control faces significant challenges in handling unknown mismatched interconnections and reducing fault-tolerant delays. To address these issues, this paper proposes a synergetic learning-based decentralized secure tracking control scheme for nonlinear interconnected systems with multiple actuator faults. Replacing actual states with desired ones in the coupled system relaxes the assumption of requiring a known upper bound for interconnections, and a neural network observer is designed to estimate the replaced interconnections. To reduce fault-tolerant delays, the secure tracking control problem is reformulated as an adversarial evolution problem between fault signals and control inputs, eliminating the need for fault compensation. To achieve optimal tracking control, an augmented subsystem is constructed by integrating the dynamics of tracking error and the reference trajectory. A modified cost function is designed for the augmented subsystem, and a critic network with two cooperative updating laws is developed to solve the Hamilton–Jacobi–Isaacs equation, providing a synergetic approximate solution for the control input and fault assistance signal. It is proven that the tracking error converges to a small neighborhood of the equilibrium. Simulation results demonstrate the effectiveness of the proposed approach.
{"title":"Decentralized Secure Tracking Control for Nonlinear Interconnected Systems: A Synergetic Learning-Based Strategy","authors":"Hongbing Xia;Anders Lindquist;Chaoxu Mu;Changyin Sun","doi":"10.1109/TCSI.2025.3580265","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3580265","url":null,"abstract":"Decentralized secure control faces significant challenges in handling unknown mismatched interconnections and reducing fault-tolerant delays. To address these issues, this paper proposes a synergetic learning-based decentralized secure tracking control scheme for nonlinear interconnected systems with multiple actuator faults. Replacing actual states with desired ones in the coupled system relaxes the assumption of requiring a known upper bound for interconnections, and a neural network observer is designed to estimate the replaced interconnections. To reduce fault-tolerant delays, the secure tracking control problem is reformulated as an adversarial evolution problem between fault signals and control inputs, eliminating the need for fault compensation. To achieve optimal tracking control, an augmented subsystem is constructed by integrating the dynamics of tracking error and the reference trajectory. A modified cost function is designed for the augmented subsystem, and a critic network with two cooperative updating laws is developed to solve the Hamilton–Jacobi–Isaacs equation, providing a synergetic approximate solution for the control input and fault assistance signal. It is proven that the tracking error converges to a small neighborhood of the equilibrium. Simulation results demonstrate the effectiveness of the proposed approach.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 12","pages":"8370-8382"},"PeriodicalIF":5.2,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145600698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In comparison to 4G, 5G wireless needs to support a broader range of applications. Therefore, both low-density parity-check (LDPC) codes and polar codes have been standardized by 5G new radio (NR) to fulfill the requirements of data channel and control channel, respectively. Usually, LDPC/polar decodings are implemented by separate hardware, leading to low area efficiency. Though decoders which can handle both codes have been proposed, how to compromise between throughput and efficiency has always been a persistent dilemma due to the absence of a unified and smooth integration methodology. To this end, by fully utilizing the common parts of graph-theoretic algorithms for both codes, this paper presents a unified decoder (UniDec) which is fully compatible with 5G NR LDPC/polar codes. This UniDec enables three key approaches: 1) unified processing nodes for both codes, 2) configurable permutation networks with multi-parallelism, and 3) flexible scheduling for 5G NR parameter configuration, guaranteeing both high data throughput and area efficiency. Implemented in 40nm CMOS, the UniDec attains a maximum of $33.64times $ throughput and $5.98times $ area efficiency compared to its multi-mode counterparts. Even compared with the state-of-the-art (SOA) dedicated ones, the UniDec still maintains a competitive edge in terms of throughput, energy, and area efficiency. It is noted that this methodology can be generalized to other factor-graph based signal processing algorithms.
与4G相比，5G无线需要支持更广泛的应用。因此，低密度校验码（LDPC）和极码（polar code）已经被5G新无线电（NR）标准化，分别满足数据信道和控制信道的要求。通常，LDPC/极性解码由单独的硬件实现，导致低面积效率。虽然已经提出了可以同时处理两种码的解码器，但由于缺乏统一的、流畅的集成方法，如何在吞吐量和效率之间折衷一直是一个困扰人们的难题。为此，本文充分利用两种码的图论算法的共性，提出了一种与5G NR LDPC/极码完全兼容的统一解码器（UniDec）。该UniDec实现了三个关键途径：1)两种编码的统一处理节点；2)具有多并行性的可配置排列网络；3)5G NR参数配置的灵活调度，保证了高数据吞吐量和区域效率。在40nm CMOS中实现的UniDec与多模同类产品相比，最大吞吐量为33.64倍，面积效率为5.98倍。即使与最先进（SOA）的专用设备相比，UniDec在吞吐量、能源和面积效率方面仍然保持竞争优势。值得注意的是，这种方法可以推广到其他基于因子图的信号处理算法。
{"title":"UniDec: A Unified Factor-Graph-Based Decoder Fully Compatible With 5G NR LDPC/Polar Codes","authors":"Houren Ji;Yi Zhang;Yutai Sun;Yongming Huang;Xiaohu You;Chuan Zhang","doi":"10.1109/TCSI.2025.3575534","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3575534","url":null,"abstract":"In comparison to 4G, 5G wireless needs to support a broader range of applications. Therefore, both low-density parity-check (LDPC) codes and polar codes have been standardized by 5G new radio (NR) to fulfill the requirements of data channel and control channel, respectively. Usually, LDPC/polar decodings are implemented by separate hardware, leading to low area efficiency. Though decoders which can handle both codes have been proposed, how to compromise between throughput and efficiency has always been a persistent dilemma due to the absence of a unified and smooth integration methodology. To this end, by fully utilizing the common parts of graph-theoretic algorithms for both codes, this paper presents a unified decoder (UniDec) which is fully compatible with 5G NR LDPC/polar codes. This UniDec enables three key approaches: <italic>1) unified processing nodes for both codes</i>, <italic>2) configurable permutation networks with multi-parallelism</i>, and <italic>3) flexible scheduling for 5G NR parameter configuration</i>, guaranteeing both high data throughput and area efficiency. Implemented in 40nm CMOS, the UniDec attains a maximum of <inline-formula> <tex-math>$33.64times $ </tex-math></inline-formula> throughput and <inline-formula> <tex-math>$5.98times $ </tex-math></inline-formula> area efficiency compared to its multi-mode counterparts. Even compared with the state-of-the-art (SOA) dedicated ones, the UniDec still maintains a competitive edge in terms of throughput, energy, and area efficiency. It is noted that this methodology can be generalized to other factor-graph based signal processing algorithms.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4235-4247"},"PeriodicalIF":5.2,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-06DOI: 10.1109/TCSI.2025.3575567
Jun Zhang;Weizhi Bian;Hao Zhang
In comparison to H.265/HEVC, H.266/VVC introduces a novel quantization tool—dependent quantization, which significantly reduces the rate while maintaining the same video quality. However, due to the quantization process of the transform coefficients being highly dependent on the quantization results of the preceding coefficients, the computational parallelism is low, making it unsuitable for hardware pipeline processing and difficult to achieve real-time encoding. To enhance parallelism, this paper optimizes the rate estimation algorithm based on dependent quantization and designs a multi-quantization state parallel quantization structure, implementing a pipeline-based dependent quantization hardware architecture. The main contributions of this paper are as follows: 1) A hardware-friendly rate estimation algorithm is proposed for calculating the quantization level rate-distortion cost, eliminating the dependency on context templates. 2) A multi state parallel quantization hardware structure is designed to improve the quantization parallelism. Among the multiple generated quantization paths, the shortest quantization path is output by comparing the cumulative rate-distortion cost. Additionally, two trellis memories are introduced during the quantization level output phase, using a ping-pong operation to maximize the output throughput of the quantization module. 3)An 8-stage pipeline computation architecture is proposed for dependent quantization, and the dependent quantization hardware module is implemented, with a computing performance capable of quantizing one transform coefficient per cycle. Experimental results show that the dependent quantization hardware module designed in this paper achieves a maximum frequency of 276MHz, with encoding average speed reaching $3840times 2160$ @31.4,83.5,164.5,242.8fps under QP = 22,27,32,37 conditions. In both All Intra and Random Access configurations, the Bjontegaard Delta Bitrate (BDBR) only increases by 0.81% and 0.85% compared to the standard reference software VTM18.0, respectively. Compared to existing hardware quantization schemes, our approach offers outstanding quantization efficiency and quantization speed.
{"title":"A Low-Latency, Highly-Pipelined Hardware Architecture for H.266/VVC Dependent Quantization","authors":"Jun Zhang;Weizhi Bian;Hao Zhang","doi":"10.1109/TCSI.2025.3575567","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3575567","url":null,"abstract":"In comparison to H.265/HEVC, H.266/VVC introduces a novel quantization tool—dependent quantization, which significantly reduces the rate while maintaining the same video quality. However, due to the quantization process of the transform coefficients being highly dependent on the quantization results of the preceding coefficients, the computational parallelism is low, making it unsuitable for hardware pipeline processing and difficult to achieve real-time encoding. To enhance parallelism, this paper optimizes the rate estimation algorithm based on dependent quantization and designs a multi-quantization state parallel quantization structure, implementing a pipeline-based dependent quantization hardware architecture. The main contributions of this paper are as follows: 1) A hardware-friendly rate estimation algorithm is proposed for calculating the quantization level rate-distortion cost, eliminating the dependency on context templates. 2) A multi state parallel quantization hardware structure is designed to improve the quantization parallelism. Among the multiple generated quantization paths, the shortest quantization path is output by comparing the cumulative rate-distortion cost. Additionally, two trellis memories are introduced during the quantization level output phase, using a ping-pong operation to maximize the output throughput of the quantization module. 3)An 8-stage pipeline computation architecture is proposed for dependent quantization, and the dependent quantization hardware module is implemented, with a computing performance capable of quantizing one transform coefficient per cycle. Experimental results show that the dependent quantization hardware module designed in this paper achieves a maximum frequency of 276MHz, with encoding average speed reaching <inline-formula> <tex-math>$3840times 2160$ </tex-math></inline-formula>@31.4,83.5,164.5,242.8fps under QP = 22,27,32,37 conditions. In both All Intra and Random Access configurations, the Bjontegaard Delta Bitrate (BDBR) only increases by 0.81% and 0.85% compared to the standard reference software VTM18.0, respectively. Compared to existing hardware quantization schemes, our approach offers outstanding quantization efficiency and quantization speed.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4040-4051"},"PeriodicalIF":5.2,"publicationDate":"2025-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-05DOI: 10.1109/TCSI.2025.3575276
Qi Hu;Lijun Fu;Fan Ma
In renewable highly integrated power system, reactive current injection of renewable generating units is important to the security operation of power system during grid fault, which is usually required by LVRT (low voltage ride through) grid code. Keeping stability during LVRT is the precondition for the current injection. However, in high impedance AC grid, the strengthened interaction of renewable generating units and AC grid may deteriorate the stability, resulting in current injection failure. In this paper, the small signal synchronizing stability of PLL (phase locked loop) based WTC (wind turbine converter) during current injection to low voltage grid fault is studied. First, a synchronizing dynamic model is developed, in which PLL is modelled in the form of rotor motion and current injection control adjusts the equivalent driving force similar as governor in SG (synchronous generator). Based on the developed model, two categories of instability issues are identified. One is the nonexistence of equilibrium point related with K-factor, grid impedance and grid voltage sag. The other is the insufficiency of damping. Current injection control may introduce negative damping to PLL’s equivalent motion in some cases, bringing synchronizing oscillation instability. Finally, simulated results are presented to verify the analytical results.
{"title":"Small Signal Synchronizing Stability of PLL-Based Wind Turbine Converter During Current Injection to Low Voltage Grid Fault","authors":"Qi Hu;Lijun Fu;Fan Ma","doi":"10.1109/TCSI.2025.3575276","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3575276","url":null,"abstract":"In renewable highly integrated power system, reactive current injection of renewable generating units is important to the security operation of power system during grid fault, which is usually required by LVRT (low voltage ride through) grid code. Keeping stability during LVRT is the precondition for the current injection. However, in high impedance AC grid, the strengthened interaction of renewable generating units and AC grid may deteriorate the stability, resulting in current injection failure. In this paper, the small signal synchronizing stability of PLL (phase locked loop) based WTC (wind turbine converter) during current injection to low voltage grid fault is studied. First, a synchronizing dynamic model is developed, in which PLL is modelled in the form of rotor motion and current injection control adjusts the equivalent driving force similar as governor in SG (synchronous generator). Based on the developed model, two categories of instability issues are identified. One is the nonexistence of equilibrium point related with K-factor, grid impedance and grid voltage sag. The other is the insufficiency of damping. Current injection control may introduce negative damping to PLL’s equivalent motion in some cases, bringing synchronizing oscillation instability. Finally, simulated results are presented to verify the analytical results.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 12","pages":"8470-8481"},"PeriodicalIF":5.2,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145600692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-03DOI: 10.1109/TCSI.2025.3574204
Yingzhe Liu;Hongfa Ding;Zhou He
This work presents a variable frequency phase-shift modulation quasi-steady-state observer-based control (VFPSM-QSSOBC) strategy for series parallel resonant converters (LCC) employed in grid-friendly repetitive bipolar pulse generator (RBPG), which has advantages of high efficiency and low interharmonics injection. To reduce interharmonics, constant power (CP) charging is well achieved by using quasi-steady-state observer to accurately obtain the averaged charging power. The VFPSM strategy is applied to improve the efficiency and narrow down the switching frequency range. In order to validate the feasibility of the proposed design, a 2.8 kW/1.2 kV prototype is constructed. Experimental results show that the prototype has an efficiency of 95.4% and a lower total interharmonic distortion (TIHD) under the rated operation, which proves that VFPSM-QSSOBC has advantages over conventional variable frequency modulation proportion-integration control (VFM-PIC) and frequency trajectory control (VFM-FTC) in the efficiency and the input current quality.
{"title":"A Quasi-Steady-State Observer-Based Control Strategy for Grid-Friendly Repetitive Bipolar Pulse Generator","authors":"Yingzhe Liu;Hongfa Ding;Zhou He","doi":"10.1109/TCSI.2025.3574204","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3574204","url":null,"abstract":"This work presents a variable frequency phase-shift modulation quasi-steady-state observer-based control (VFPSM-QSSOBC) strategy for series parallel resonant converters (LCC) employed in grid-friendly repetitive bipolar pulse generator (RBPG), which has advantages of high efficiency and low interharmonics injection. To reduce interharmonics, constant power (CP) charging is well achieved by using quasi-steady-state observer to accurately obtain the averaged charging power. The VFPSM strategy is applied to improve the efficiency and narrow down the switching frequency range. In order to validate the feasibility of the proposed design, a 2.8 kW/1.2 kV prototype is constructed. Experimental results show that the prototype has an efficiency of 95.4% and a lower total interharmonic distortion (TIHD) under the rated operation, which proves that VFPSM-QSSOBC has advantages over conventional variable frequency modulation proportion-integration control (VFM-PIC) and frequency trajectory control (VFM-FTC) in the efficiency and the input current quality.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 12","pages":"8457-8469"},"PeriodicalIF":5.2,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145600686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a low-dropout regulator (LDO) with a 5-A current capability, supporting a wide range of output capacitors. An output impedance shaping technique is proposed, introducing two half-zeros into the loop to shape the LDO’s output impedance between resistive and inductive characteristics. The proposed technique ensures a decent frequency and transient response across an output capacitance range from 0 to $150~boldsymbol {mu }$ F. To achieve a widely adjustable output voltage, a two-stage buffer with fast transient response and active feedback is employed, which further improves the overall stability and transient performance of the LDO. Under light-load conditions, the current sensing module provides an auxiliary feedback path for the error amplifier (EA), thereby securing loop stability by pushing the dominant pole to a higher frequency and lowering the DC loop gain. Implemented with a $0.18~boldsymbol { mu }$ m CMOS process, the chip occupies an area of $1.9times 1.9$ mm2. The LDO regulates an output voltage from 0.8 to 3.5 V within an input voltage range of 2.8 to 5.5 V. With a minimum dropout voltage of 150 mV, the open-loop gain is 80 dB and remains comparatively unaffected by load alterations, ensuring a robust load regulation of 1.3 mV/A. Measured results demonstrate a 170-mV undershoot during a 5-A/1-$boldsymbol {mu }$ s load step without external output capacitors.
{"title":"A High Current NMOS LDO Handles a Wide Range of Load Capacitors With Output Impedance Shaping Technique","authors":"Yuhao Yang;Lenian He;Yizhang Liu;Haoze Su;Jianxiong Xi;Anming Gao;Wei Jiang","doi":"10.1109/TCSI.2025.3570165","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3570165","url":null,"abstract":"This paper presents a low-dropout regulator (LDO) with a 5-A current capability, supporting a wide range of output capacitors. An output impedance shaping technique is proposed, introducing two half-zeros into the loop to shape the LDO’s output impedance between resistive and inductive characteristics. The proposed technique ensures a decent frequency and transient response across an output capacitance range from 0 to <inline-formula> <tex-math>$150~boldsymbol {mu }$ </tex-math></inline-formula>F. To achieve a widely adjustable output voltage, a two-stage buffer with fast transient response and active feedback is employed, which further improves the overall stability and transient performance of the LDO. Under light-load conditions, the current sensing module provides an auxiliary feedback path for the error amplifier (EA), thereby securing loop stability by pushing the dominant pole to a higher frequency and lowering the DC loop gain. Implemented with a <inline-formula> <tex-math>$0.18~boldsymbol { mu }$ </tex-math></inline-formula>m CMOS process, the chip occupies an area of <inline-formula> <tex-math>$1.9times 1.9$ </tex-math></inline-formula> mm2. The LDO regulates an output voltage from 0.8 to 3.5 V within an input voltage range of 2.8 to 5.5 V. With a minimum dropout voltage of 150 mV, the open-loop gain is 80 dB and remains comparatively unaffected by load alterations, ensuring a robust load regulation of 1.3 mV/A. Measured results demonstrate a 170-mV undershoot during a 5-A/1-<inline-formula> <tex-math>$boldsymbol {mu }$ </tex-math></inline-formula>s load step without external output capacitors.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 11","pages":"7449-7462"},"PeriodicalIF":5.2,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-03DOI: 10.1109/TCSI.2025.3571416
Kai Yu;Yuhong Deng;Sizhen Li;Jingran Zhang;Mo Huang
This paper presents a scalable hybrid boost converter (SHBC) with adjusted number of stages (N) to acquire high conversion ratio (CR) and high power efficiency. Firstly, unlike most converters where CR is related only to duty cycle (D), the CR of SHBC is related to both D and N. This allows the converter to provide a high CR while keeping D at a reasonable value for easy loop control. Secondly, N flying capacitors in series with the inductor can divide output voltage ($V_{mathrm {OUT}}$ ) to use low voltage devices with small figure of metric (FOM) for high power efficiency. Moreover, N flying capacitors in parallel with the inductor can shunt the inductor current to reduce the inductor DCR loss, which also helps improve power efficiency. Thirdly, when many N values meet the requirements of a specific application scenario, an optimal number of stages (NOPT) is proposed to minimize the total loss and optimize the power efficiency further. The prototype design of SHBC with $mathrm{N}_{mathrm {OPT}} =2$ has been discussed and fabricated by $0.18~mu $ m BCD process. The measurement results demonstrate its operation is normal in the CR range from 4 to 8. Besides, a 93.34% peak efficiency is also achieved with $I_{mathrm {OUT}} =0.125$ A and CR = 4.
本文提出了一种可调级数混合升压转换器（SHBC），以获得高转换率（CR）和高功率效率。首先，与大多数变换器的CR只与占空比(D)有关不同，SHBC的CR与D和n都有关，这使得变换器可以提供高CR，同时保持D在一个合理的值，以便于环路控制。其次，与电感串联的N个飞行电容器可以分割输出电压（$V_{ maththrm {OUT}}$），使用具有小度量图（FOM）的低压器件，从而提高功率效率。此外，与电感并联的N个飞行电容器可以分流电感电流，降低电感DCR损耗，也有助于提高功率效率。第三，当多个N值满足特定应用场景的要求时，提出最优级数（NOPT），使总损耗最小化，进一步优化功率效率。讨论了$ mathm {N}_{ mathm {OPT}} =2$的SHBC原型设计，并采用$0.18~mu $ m BCD工艺制作了SHBC原型。测量结果表明，在4 ~ 8的CR范围内，其运行正常。此外，当$I_{ mathm {OUT}} =0.125$ a, CR = 4时，峰值效率也达到了93.34%。
{"title":"Design of Scalable Hybrid Boost Converter With Optimal Number of Stages for High Conversion Ratio and High Power Efficiency","authors":"Kai Yu;Yuhong Deng;Sizhen Li;Jingran Zhang;Mo Huang","doi":"10.1109/TCSI.2025.3571416","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3571416","url":null,"abstract":"This paper presents a scalable hybrid boost converter (SHBC) with adjusted number of stages (N) to acquire high conversion ratio (<italic>CR</i>) and high power efficiency. Firstly, unlike most converters where <italic>CR</i> is related only to duty cycle (<italic>D</i>), the <italic>CR</i> of SHBC is related to both <italic>D</i> and N. This allows the converter to provide a high <italic>CR</i> while keeping <italic>D</i> at a reasonable value for easy loop control. Secondly, N flying capacitors in series with the inductor can divide output voltage (<inline-formula> <tex-math>$V_{mathrm {OUT}}$ </tex-math></inline-formula>) to use low voltage devices with small figure of metric (FOM) for high power efficiency. Moreover, N flying capacitors in parallel with the inductor can shunt the inductor current to reduce the inductor DCR loss, which also helps improve power efficiency. Thirdly, when many N values meet the requirements of a specific application scenario, an optimal number of stages (N<sub>OPT</sub>) is proposed to minimize the total loss and optimize the power efficiency further. The prototype design of SHBC with <inline-formula> <tex-math>$mathrm{N}_{mathrm {OPT}} =2$ </tex-math></inline-formula> has been discussed and fabricated by <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m BCD process. The measurement results demonstrate its operation is normal in the <italic>CR</i> range from 4 to 8. Besides, a 93.34% peak efficiency is also achieved with <inline-formula> <tex-math>$I_{mathrm {OUT}} =0.125$ </tex-math></inline-formula> A and <italic>CR</i> = 4.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 12","pages":"8434-8445"},"PeriodicalIF":5.2,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145600684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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