{"title":"Finite-Time Asynchronous Switching Control for Fuzzy Markov Jump Systems by Applying Polynomial Membership Functions","authors":"Yinghong Zhao, Likui Wang, Xiangpeng Xie, Hak-Keung Lam","doi":"10.1109/tcsi.2024.3448629","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3448629","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"82 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 4–22 GHz Ultra-Wideband Low-Noise Amplifier With 0.8–1.5 dB NF and 28–31 dB Gain Enhanced by the Negative Load Impedance","authors":"Xiaojie Zhang, Kuisong Wang, Ruiying Gao, Yuying Zhang, Jing Wan, Zhiyong Zhou, Xuming Sun, Xiaoxin Liang","doi":"10.1109/tcsi.2024.3448534","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3448534","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"32 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-29DOI: 10.1109/tcsi.2024.3447703
Kai Wang, Feiyang Zhong, Jian Song, Zichuan Yu, Lu Tang, Xusheng Tang, Qing Yao
{"title":"Power System Frequency Estimation With Zero Response Time Under Abrupt Transients","authors":"Kai Wang, Feiyang Zhong, Jian Song, Zichuan Yu, Lu Tang, Xusheng Tang, Qing Yao","doi":"10.1109/tcsi.2024.3447703","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3447703","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"13 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-29DOI: 10.1109/TCSI.2024.3444005
Zhile Lin;Liangzong He;Hongyan Zhou
This paper proposed an innovative fractional-order circuit LC (FOC-LC) based resonant filtering method to suppress low-order harmonic currents in AC power system. By constructing the FOC-LC harmonic suppression branch and applying a corresponding modulation strategy, the impedance complex plane maintains symmetrical resonance inductance and capacitance. This leads to an extremely low equivalent impedance for different harmonic currents, effectively suppressing harmonics with diverse frequencies and magnitudes. The proposed method demonstrates robustness to device parameters and maintains reliable harmonic suppression performance within an acceptable error range. The utilization of fractional-order circuits allows for auxiliary charging, modifying output port capacitance, adjusting equivalent resistance, and even achieving negative resistance characteristics. This results in minimal resonance equivalent resistance in the harmonic suppression branch. To verify feasibility, a 1.2 kW prototype was implemented, yielding promising results. The experimental validation validates the practical applicability and effectiveness of this method.
{"title":"Adaptive Low-Order Harmonic Currents Suppression in AC Power System Using Fractional-Order Circuit","authors":"Zhile Lin;Liangzong He;Hongyan Zhou","doi":"10.1109/TCSI.2024.3444005","DOIUrl":"10.1109/TCSI.2024.3444005","url":null,"abstract":"This paper proposed an innovative fractional-order circuit LC (FOC-LC) based resonant filtering method to suppress low-order harmonic currents in AC power system. By constructing the FOC-LC harmonic suppression branch and applying a corresponding modulation strategy, the impedance complex plane maintains symmetrical resonance inductance and capacitance. This leads to an extremely low equivalent impedance for different harmonic currents, effectively suppressing harmonics with diverse frequencies and magnitudes. The proposed method demonstrates robustness to device parameters and maintains reliable harmonic suppression performance within an acceptable error range. The utilization of fractional-order circuits allows for auxiliary charging, modifying output port capacitance, adjusting equivalent resistance, and even achieving negative resistance characteristics. This results in minimal resonance equivalent resistance in the harmonic suppression branch. To verify feasibility, a 1.2 kW prototype was implemented, yielding promising results. The experimental validation validates the practical applicability and effectiveness of this method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4446-4457"},"PeriodicalIF":5.2,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-28DOI: 10.1109/TCSI.2024.3439210
Amr I. Eissa;Enrique Alvarez-Fontecilla;Colin Weltin-Wu;Ian Galton
Increasing a PLL’s reference frequency offers significant performance advantages, but doing so by increasing the PLL’s crystal oscillator frequency is not a viable option in many applications. Instead, a frequency doubler can be used to derive a reference signal with twice the frequency of the crystal oscillator, but conventional PLLs are highly sensitive to the crystal oscillator’s duty cycle error in such cases. Prior solutions to this problem involve calibration techniques which impose convergence speed versus accuracy tradeoffs. In contrast, this paper proposes a system modification which makes a PLL immune to such duty cycle errors without the need for calibration. The technique is presented and analyzed in the context of a delta-sigma frequency-to-digital converter ( $Delta Sigma $ -FDC) based PLL. Analysis and behavioral simulations with nonideal circuit parameters show that the worst-case convergence time is at least 10 times faster than that of the prior techniques. Additionally, the proposed $Delta Sigma $ -FDC includes other modifications which improve its performance relative to comparable prior $Delta Sigma $ -FDCs.
{"title":"A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs","authors":"Amr I. Eissa;Enrique Alvarez-Fontecilla;Colin Weltin-Wu;Ian Galton","doi":"10.1109/TCSI.2024.3439210","DOIUrl":"10.1109/TCSI.2024.3439210","url":null,"abstract":"Increasing a PLL’s reference frequency offers significant performance advantages, but doing so by increasing the PLL’s crystal oscillator frequency is not a viable option in many applications. Instead, a frequency doubler can be used to derive a reference signal with twice the frequency of the crystal oscillator, but conventional PLLs are highly sensitive to the crystal oscillator’s duty cycle error in such cases. Prior solutions to this problem involve calibration techniques which impose convergence speed versus accuracy tradeoffs. In contrast, this paper proposes a system modification which makes a PLL immune to such duty cycle errors without the need for calibration. The technique is presented and analyzed in the context of a delta-sigma frequency-to-digital converter (\u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000-FDC) based PLL. Analysis and behavioral simulations with nonideal circuit parameters show that the worst-case convergence time is at least 10 times faster than that of the prior techniques. Additionally, the proposed \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000-FDC includes other modifications which improve its performance relative to comparable prior \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000-FDCs.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4524-4537"},"PeriodicalIF":5.2,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-28DOI: 10.1109/TCSI.2024.3441434
{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2024.3441434","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3441434","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 9","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10654564","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-28DOI: 10.1109/tcsi.2024.3447080
Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Włodarczak
{"title":"A Nonlinear Stream Cipher for Encryption of Test Patterns in Streaming Scan Networks","authors":"Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Włodarczak","doi":"10.1109/tcsi.2024.3447080","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3447080","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"13 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-28DOI: 10.1109/tcsi.2024.3447013
Yoomi Park, Sangjin Byun
{"title":"Analysis and Design of a 570-Stage CMOS RF-DC Rectifier With Ground Shielded Input Coupling Capacitors","authors":"Yoomi Park, Sangjin Byun","doi":"10.1109/tcsi.2024.3447013","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3447013","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"2016 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-28DOI: 10.1109/TCSI.2024.3441432
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2024.3441432","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3441432","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 9","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10654556","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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