Pub Date : 2024-08-28DOI: 10.1109/TCSI.2024.3441436
{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2024.3441436","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3441436","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 9","pages":"4410-4410"},"PeriodicalIF":5.2,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10654560","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-27DOI: 10.1109/tcsi.2024.3436694
Sang-Wha Seo, Joon-Hyoung Ryu, June-Seok Lee
{"title":"Bidirectional High Step-Up/Down DC/DC Converter With a Coupled Inductor and Switched Capacitor","authors":"Sang-Wha Seo, Joon-Hyoung Ryu, June-Seok Lee","doi":"10.1109/tcsi.2024.3436694","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3436694","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"22 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-27DOI: 10.1109/tcsi.2024.3446582
Majed Alsharari, Son T. Mai, Roger Woods, Carlos Reaño
{"title":"Efficient Integer-Only-Inference of Gradient Boosting Decision Trees on Low-Power Devices","authors":"Majed Alsharari, Son T. Mai, Roger Woods, Carlos Reaño","doi":"10.1109/tcsi.2024.3446582","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3446582","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"16 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-27DOI: 10.1109/tcsi.2024.3447830
Gennaro Di Meo, Antonio Giuseppe Maria Strollo, Davide De Caro, Luca Tegazzini, Ettore Napoli
{"title":"Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation","authors":"Gennaro Di Meo, Antonio Giuseppe Maria Strollo, Davide De Caro, Luca Tegazzini, Ettore Napoli","doi":"10.1109/tcsi.2024.3447830","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3447830","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"109 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-27DOI: 10.1109/TCSI.2024.3438563
Chao Cui;Chunbo Zhu;Xin Gao;Shumei Cui;Qianfan Zhang;C. C. Chan
Modular parallel inverter technology can enhance the power level and redundancy of wireless power transfer (WPT) systems, contributing to standardized production. It serves as an effective method for realizing high-power systems. However, inappropriate selection of compensation components can negatively affect the system’s efficiency, power factor, and the flexibility of modularization. This paper analyzes two key properties of modular-parallel-inverter WPT (MPI-WPT) systems: module number flexibility and modular deviation suppression. Firstly, to assess the modular deviation suppression of the system, its definition and calculation method are provided. Secondly, the expansion condition to achieve modular flexibility is examined, highlighting that the modular system needs to be a fully resonant system. Subsequently, an expansion design methodology from a single WPT system to an MPI-WPT system is proposed, ensuring the preservation of the original properties of the system during its extension. Finally, the parallel characteristics of MPI-WPT systems were experimentally verified.
{"title":"Modular Expansion Method for Wireless Power Transfer Systems With Arbitrary Topologies","authors":"Chao Cui;Chunbo Zhu;Xin Gao;Shumei Cui;Qianfan Zhang;C. C. Chan","doi":"10.1109/TCSI.2024.3438563","DOIUrl":"10.1109/TCSI.2024.3438563","url":null,"abstract":"Modular parallel inverter technology can enhance the power level and redundancy of wireless power transfer (WPT) systems, contributing to standardized production. It serves as an effective method for realizing high-power systems. However, inappropriate selection of compensation components can negatively affect the system’s efficiency, power factor, and the flexibility of modularization. This paper analyzes two key properties of modular-parallel-inverter WPT (MPI-WPT) systems: module number flexibility and modular deviation suppression. Firstly, to assess the modular deviation suppression of the system, its definition and calculation method are provided. Secondly, the expansion condition to achieve modular flexibility is examined, highlighting that the modular system needs to be a fully resonant system. Subsequently, an expansion design methodology from a single WPT system to an MPI-WPT system is proposed, ensuring the preservation of the original properties of the system during its extension. Finally, the parallel characteristics of MPI-WPT systems were experimentally verified.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4824-4836"},"PeriodicalIF":5.2,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-27DOI: 10.1109/TCSI.2024.3428636
Tsung-Hsi Wu;Chang Shu;Tsung-Te Liu
This work presents a Field Programmable Gate Array (FPGA)-based deep neural network (DNN) accelerator that can maintain consistently high efficiency when executing various neural network architectures, including convolutional neural network (CNN), transposed and dilated convolution (TD-convolution) operations for modern computer vision (CV) tasks. To deal with the utilization degradation issue with a large processing unit (PE) array, a 3-D mapping strategy that adaptively tailors different layer configurations is proposed to optimize the parallelism dimensions of the PE, which significantly increases the hardware utilization to enhance the accelerator efficiency. Moreover, to minimize the implementation and performance overhead resulting from the TD-convolution operations, a unified processing flow is proposed to realize an integrated operation of traditional and TD-convolution. This allows the accelerator to bypass redundant zero operations, further boosting overall efficiency. The 4096-PE accelerator implementation on Intel Stratix 10 FPGA achieves a throughput performance of 2.597–2.870 TOPS with an efficiency of 0.63-0.70 GOPS/DSP across various DNN networks. This represents $1.72times $ and $1.73times $ improvement in throughput and efficiency, respectively, compared to the state-of-the-art designs.
{"title":"An Efficient FPGA-Based Dilated and Transposed Convolutional Neural Network Accelerator","authors":"Tsung-Hsi Wu;Chang Shu;Tsung-Te Liu","doi":"10.1109/TCSI.2024.3428636","DOIUrl":"10.1109/TCSI.2024.3428636","url":null,"abstract":"This work presents a Field Programmable Gate Array (FPGA)-based deep neural network (DNN) accelerator that can maintain consistently high efficiency when executing various neural network architectures, including convolutional neural network (CNN), transposed and dilated convolution (TD-convolution) operations for modern computer vision (CV) tasks. To deal with the utilization degradation issue with a large processing unit (PE) array, a 3-D mapping strategy that adaptively tailors different layer configurations is proposed to optimize the parallelism dimensions of the PE, which significantly increases the hardware utilization to enhance the accelerator efficiency. Moreover, to minimize the implementation and performance overhead resulting from the TD-convolution operations, a unified processing flow is proposed to realize an integrated operation of traditional and TD-convolution. This allows the accelerator to bypass redundant zero operations, further boosting overall efficiency. The 4096-PE accelerator implementation on Intel Stratix 10 FPGA achieves a throughput performance of 2.597–2.870 TOPS with an efficiency of 0.63-0.70 GOPS/DSP across various DNN networks. This represents \u0000<inline-formula> <tex-math>$1.72times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.73times $ </tex-math></inline-formula>\u0000 improvement in throughput and efficiency, respectively, compared to the state-of-the-art designs.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5178-5186"},"PeriodicalIF":5.2,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-22DOI: 10.1109/TCSI.2024.3445179
Ya Zhao;Chao Fan;Jun Yin;Pui-In Mak;Li Geng
This paper reports a triple-coil transformer-coupled quadrature voltage-controlled oscillator (TC-QVCO), which inherently provides the quadrature signal without using the noisy active-coupling transistors. The determinate correlation of tank voltages is verified by utilizing the initial state to facilitate the oscillation state analysis. Thus, the TC-QVCO would operate without the oscillation mode ambiguity. Additionally, thanks to the triple-coil transformer coupling, a large source coil $L_{S}$ aids in achieving in-phase coupling for phase noise (PN) improvement, and the intensified coupling factor $k_{gd}$ benefits reducing the PN and the quadrature phase error simultaneously. Therefore, our TC-QVCO would alleviate the tradeoff between PN and quadrature phase accuracy via using a large $L_{S}$ and $k_{gd}$ . The proposed QVCO prototyped in 65-nm CMOS exhibits a superior FoM $_{text {@10MHz}}$ (180.1 to 182.2 dBc/Hz) over a 18.2% frequency tuning range (21.2 to 25.5 GHz), and the estimated quadrature phase error <0.8°.
{"title":"Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO","authors":"Ya Zhao;Chao Fan;Jun Yin;Pui-In Mak;Li Geng","doi":"10.1109/TCSI.2024.3445179","DOIUrl":"10.1109/TCSI.2024.3445179","url":null,"abstract":"This paper reports a triple-coil transformer-coupled quadrature voltage-controlled oscillator (TC-QVCO), which inherently provides the quadrature signal without using the noisy active-coupling transistors. The determinate correlation of tank voltages is verified by utilizing the initial state to facilitate the oscillation state analysis. Thus, the TC-QVCO would operate without the oscillation mode ambiguity. Additionally, thanks to the triple-coil transformer coupling, a large source coil \u0000<inline-formula> <tex-math>$L_{S}$ </tex-math></inline-formula>\u0000 aids in achieving in-phase coupling for phase noise (PN) improvement, and the intensified coupling factor \u0000<inline-formula> <tex-math>$k_{gd}$ </tex-math></inline-formula>\u0000 benefits reducing the PN and the quadrature phase error simultaneously. Therefore, our TC-QVCO would alleviate the tradeoff between PN and quadrature phase accuracy via using a large \u0000<inline-formula> <tex-math>$L_{S}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$k_{gd}$ </tex-math></inline-formula>\u0000. The proposed QVCO prototyped in 65-nm CMOS exhibits a superior FoM\u0000<inline-formula> <tex-math>$_{text {@10MHz}}$ </tex-math></inline-formula>\u0000 (180.1 to 182.2 dBc/Hz) over a 18.2% frequency tuning range (21.2 to 25.5 GHz), and the estimated quadrature phase error <0.8°.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4538-4549"},"PeriodicalIF":5.2,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a 0.5-V, two-stage, pseudo-differential bulk-driven operational transconductance amplifier with high gain and linearity for low-power continuous-time applications. The input stage’s common-mode feedback utilizes a linear resistor detector with a conductance reduction cross-coupled pair to mitigate the loading effect of the common-mode detector resistor at ultra-low power operations. Temperature dependence of the conductance reduction circuit is compensated. The impact of the conductance reduction circuit on linearity performance is explored. The output stage employs a class-AB topology and utilizes a phase lead compensator to stabilize the OTA. Implemented in 180 nm CMOS technology, this OTA achieves a DC gain and slew rate of 68 dB and 26.1 V/ $mu $ s, respectively, under a capacitive load of 10 pF. The total power consumption is $34.2~mu $ W. With unit gain feedback configuration, the measured total harmonic distortion is only 0.02% at an output amplitude of 500 mVpp. Test results validate the proposed circuit, positioning it competitively compared to state-of-the-art designs.
本文介绍了一种 0.5 V、两级、伪差分批量驱动运算跨导放大器，具有高增益和线性度，适用于低功耗连续时间应用。输入级的共模反馈采用线性电阻检测器和电导降低交叉耦合对，以减轻超低功耗工作时共模检测器电阻的负载效应。电导降低电路的温度依赖性得到了补偿。探讨了电导降低电路对线性性能的影响。输出级采用 AB 类拓扑结构，并利用相位导联补偿器来稳定 OTA。该 OTA 采用 180 nm CMOS 技术实现，在 10 pF 的电容负载下，直流增益和压摆率分别达到 68 dB 和 26.1 V/ $mu$s。在单位增益反馈配置下，输出振幅为 500 mVpp 时，测得的总谐波失真仅为 0.02%。测试结果验证了所提出的电路，使其与最先进的设计相比更具竞争力。
{"title":"A 0.5-V 0.02% THD Bulk-Driven OTA for Continuous-Time Applications in 180 nm CMOS","authors":"Yangxin Xiang;Huajun Yao;Minghao Jiang;Junkun Chen;Yongzhen Chen;Jiangfeng Wu","doi":"10.1109/TCSI.2024.3443452","DOIUrl":"10.1109/TCSI.2024.3443452","url":null,"abstract":"This paper introduces a 0.5-V, two-stage, pseudo-differential bulk-driven operational transconductance amplifier with high gain and linearity for low-power continuous-time applications. The input stage’s common-mode feedback utilizes a linear resistor detector with a conductance reduction cross-coupled pair to mitigate the loading effect of the common-mode detector resistor at ultra-low power operations. Temperature dependence of the conductance reduction circuit is compensated. The impact of the conductance reduction circuit on linearity performance is explored. The output stage employs a class-AB topology and utilizes a phase lead compensator to stabilize the OTA. Implemented in 180 nm CMOS technology, this OTA achieves a DC gain and slew rate of 68 dB and 26.1 V/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 s, respectively, under a capacitive load of 10 pF. The total power consumption is \u0000<inline-formula> <tex-math>$34.2~mu $ </tex-math></inline-formula>\u0000 W. With unit gain feedback configuration, the measured total harmonic distortion is only 0.02% at an output amplitude of 500 mVpp. Test results validate the proposed circuit, positioning it competitively compared to state-of-the-art designs.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4420-4433"},"PeriodicalIF":5.2,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-20DOI: 10.1109/TCSI.2024.3439616
Mei-Hsuan Chang;Pei-Yun Tsai
The complexity of conventional massage propagation algorithm (MPA) for detection of sparse code multiple access (SCMA) grows exponentially as the size of the codebook increases, posing a challenge for hardware implementation of large-size codebooks. Expectation propagation algorithm (EPA) has shown its superiority owing to its linear complexity with respect to the codebook size. In this paper, we propose log-domain group-approximate EPA (GA-EPA) for further complexity reduction. The mother constellation points are partitioned into several groups, which can simplify the calculation of posterior probability. Compared to conventional EPA, log-domain GA-EPA can reduce approximately 76.4% of multiplications and 53.8% of divisions for MIMO-SCMA signal detection. A GA-EPA detector is then designed in 40nm CMOS technology, we use customized floating-point to shorten word-lengths and to exploit the property of exponential function for accomplishing 17% total area reduction and more than 99% table reduction. From the synthesis results, our design for MIMO-SCMA detection with 16-point codebook from 4 receiving antennas can achieve a throughput of 364Mbps at an operating frequency of 167MHz. Compared to the prior MPA-related implementations, our work outperforms in normalized hardware efficiency and demonstrates a promising solution for large codebook cardinality.
{"title":"Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook","authors":"Mei-Hsuan Chang;Pei-Yun Tsai","doi":"10.1109/TCSI.2024.3439616","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3439616","url":null,"abstract":"The complexity of conventional massage propagation algorithm (MPA) for detection of sparse code multiple access (SCMA) grows exponentially as the size of the codebook increases, posing a challenge for hardware implementation of large-size codebooks. Expectation propagation algorithm (EPA) has shown its superiority owing to its linear complexity with respect to the codebook size. In this paper, we propose log-domain group-approximate EPA (GA-EPA) for further complexity reduction. The mother constellation points are partitioned into several groups, which can simplify the calculation of posterior probability. Compared to conventional EPA, log-domain GA-EPA can reduce approximately 76.4% of multiplications and 53.8% of divisions for MIMO-SCMA signal detection. A GA-EPA detector is then designed in 40nm CMOS technology, we use customized floating-point to shorten word-lengths and to exploit the property of exponential function for accomplishing 17% total area reduction and more than 99% table reduction. From the synthesis results, our design for MIMO-SCMA detection with 16-point codebook from 4 receiving antennas can achieve a throughput of 364Mbps at an operating frequency of 167MHz. Compared to the prior MPA-related implementations, our work outperforms in normalized hardware efficiency and demonstrates a promising solution for large codebook cardinality.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4753-4766"},"PeriodicalIF":5.2,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-20DOI: 10.1109/TCSI.2024.3443270
Jeongmin Kim;Sungho Kim;Kangjoon Choi;In-Cheol Park
The SoftMax function is one of the activation functions used in deep neural networks (DNN) to normalize input values to the range of (0,1). With the advent of DNN models including the Transformer, operations utilizing SoftMax have gained significant attention, and the efficient hardware implementation of such operations has become a prominent issue in hardware realization. Implementing SoftMax often involves exponential and division operations, which can be a significant bottleneck in terms of hardware cost and performance. Various efforts have been made to address this challenge, and this paper introduces a novel approach to efficiently implement SoftMax. In most previous works, the maximum input value is subtracted from all the input values to ensure numerical stability. In the proposed approach, the maximum value is replaced with a different value to reduce the hardware complexity with ensuring numerical stability. Additionally, in exponential operations, simple Look-Up Tables (LUTs) with only one entry each are used for bit-wise calculations, and the reciprocal of the total exponential sum is computed to replace division with multiplication. Applying the proposed methods reduces the computational complexity significantly compared to the previous log-sum-exp approach. As a result, the proposed 8-bit SoftMax accelerator achieves a high operating frequency of 3.12GHz and a high throughput of 25G inputs/s. It also improves area efficiency and power consumption by at least 2 times. From an accuracy perspective, furthermore, it is associated with similar or even better accuracy compared to previous works.
{"title":"Hardware-Efficient SoftMax Architecture With Bit-Wise Exponentiation and Reciprocal Calculation","authors":"Jeongmin Kim;Sungho Kim;Kangjoon Choi;In-Cheol Park","doi":"10.1109/TCSI.2024.3443270","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3443270","url":null,"abstract":"The SoftMax function is one of the activation functions used in deep neural networks (DNN) to normalize input values to the range of (0,1). With the advent of DNN models including the Transformer, operations utilizing SoftMax have gained significant attention, and the efficient hardware implementation of such operations has become a prominent issue in hardware realization. Implementing SoftMax often involves exponential and division operations, which can be a significant bottleneck in terms of hardware cost and performance. Various efforts have been made to address this challenge, and this paper introduces a novel approach to efficiently implement SoftMax. In most previous works, the maximum input value is subtracted from all the input values to ensure numerical stability. In the proposed approach, the maximum value is replaced with a different value to reduce the hardware complexity with ensuring numerical stability. Additionally, in exponential operations, simple Look-Up Tables (LUTs) with only one entry each are used for bit-wise calculations, and the reciprocal of the total exponential sum is computed to replace division with multiplication. Applying the proposed methods reduces the computational complexity significantly compared to the previous log-sum-exp approach. As a result, the proposed 8-bit SoftMax accelerator achieves a high operating frequency of 3.12GHz and a high throughput of 25G inputs/s. It also improves area efficiency and power consumption by at least 2 times. From an accuracy perspective, furthermore, it is associated with similar or even better accuracy compared to previous works.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4574-4585"},"PeriodicalIF":5.2,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142377007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：