Pub Date : 2024-09-09DOI: 10.1109/tcsi.2024.3446621
Shanlin Liu, Yingwei Zhang, Xudong Zhao
{"title":"Adaptive Event-Triggered Control for PDE-ODE Cascade Systems via Hierarchical Sliding Mode","authors":"Shanlin Liu, Yingwei Zhang, Xudong Zhao","doi":"10.1109/tcsi.2024.3446621","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3446621","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"36 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Non-volatile memory (NVM)-based Computation-in-memory has demonstrated a significant advantage in high-efficiency neural networks. However, the requirement of analog-to-digital converter (ADC) and post-processing circuits not only cost high energy and area but also results in high computation errors, which tradeoffs the performance boost brought by CIM. Here, we present a specific ADC and post-processing circuit of the NVM-based CIM neural network to address these issues. The main contributions include: (1) A novel residual charge accumulation function (RCA) is designed to achieve charge-domain summation of quantized partial sum and reduces 38% quantization error; (2) Charge reset is introduced in the integrate & fire circuit to realize <1> $3.95times $ energy efficiency and $2.48times $ area efficiency. Evaluation based on the measured results of the fabricated chip shows that the VGG-11 neural network with the proposed ADC circuit can achieve a 3.28-time improvement in energy efficiency while maintaining the same network recognition rate.
{"title":"Specific ADC of NVM-Based Computation-in-Memory for Deep Neural Networks","authors":"Ao Shi;Yizhou Zhang;Lixia Han;Zheng Zhou;Yiyang Chen;Haozhang Yang;Lifeng Liu;Linxiao Shen;Xiaoyan Liu;Jinfeng Kang;Peng Huang","doi":"10.1109/TCSI.2024.3430290","DOIUrl":"10.1109/TCSI.2024.3430290","url":null,"abstract":"Non-volatile memory (NVM)-based Computation-in-memory has demonstrated a significant advantage in high-efficiency neural networks. However, the requirement of analog-to-digital converter (ADC) and post-processing circuits not only cost high energy and area but also results in high computation errors, which tradeoffs the performance boost brought by CIM. Here, we present a specific ADC and post-processing circuit of the NVM-based CIM neural network to address these issues. The main contributions include: (1) A novel residual charge accumulation function (RCA) is designed to achieve charge-domain summation of quantized partial sum and reduces 38% quantization error; (2) Charge reset is introduced in the integrate & fire circuit to realize <1> <tex-math>$3.95times $ </tex-math></inline-formula>\u0000 energy efficiency and \u0000<inline-formula> <tex-math>$2.48times $ </tex-math></inline-formula>\u0000 area efficiency. Evaluation based on the measured results of the fabricated chip shows that the VGG-11 neural network with the proposed ADC circuit can achieve a 3.28-time improvement in energy efficiency while maintaining the same network recognition rate.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5387-5399"},"PeriodicalIF":5.2,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-05DOI: 10.1109/TCSI.2024.3450966
Gianluca Leone;Matteo Antonio Scrugli;Lorenzo Badas;Luca Martis;Luigi Raffo;Paolo Meloni
Spiking Neural Networks (SNNs) are energy- and performance-efficient tools that have been found to be very useful in AI applications at the edge. This paper introduces SYNtzulu, an SNN processing element designed to be used in low-cost and low-power FPGA devices for near-sensor data analysis. The system is equipped with a RISC-V subsystem responsible for controlling the input/output and setting runtime parameters, thus increasing its flexibility. We evaluated the system, which was implemented on a Lattice iCE40UP5K FPGA, in various use cases employing SNNs with accuracy comparable to the state-of-the-art. SYNtzulu dissipates a maximum power of 12.05 mW when performing SNN inference, which can be reduced to an average of just 1.45 mW through the use of dynamic power management.
{"title":"SYNtzulu: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs","authors":"Gianluca Leone;Matteo Antonio Scrugli;Lorenzo Badas;Luca Martis;Luigi Raffo;Paolo Meloni","doi":"10.1109/TCSI.2024.3450966","DOIUrl":"10.1109/TCSI.2024.3450966","url":null,"abstract":"Spiking Neural Networks (SNNs) are energy- and performance-efficient tools that have been found to be very useful in AI applications at the edge. This paper introduces <monospace>SYNtzulu</monospace>, an SNN processing element designed to be used in low-cost and low-power FPGA devices for near-sensor data analysis. The system is equipped with a RISC-V subsystem responsible for controlling the input/output and setting runtime parameters, thus increasing its flexibility. We evaluated the system, which was implemented on a Lattice iCE40UP5K FPGA, in various use cases employing SNNs with accuracy comparable to the state-of-the-art. <monospace>SYNtzulu</monospace> dissipates a maximum power of 12.05 mW when performing SNN inference, which can be reduced to an average of just 1.45 mW through the use of dynamic power management.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"790-801"},"PeriodicalIF":5.2,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10666827","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-05DOI: 10.1109/TCSI.2024.3450668
Dixian Zhao;Weihan Gao;Ke Li;Hengzhi Wan;Qin Tian;Yongran Yi;Jiajun Zhang;Huiqi Liu
This paper presents 256-element transmitter (TX) and receiver (RX) phased arrays for satellite fixed communication at the Q and V bands, which integrate the phased-array antennas with eight-channel beamforming ICs. Wideband vector-modulated phase shifters (VGPS) and combinations of variable gain amplifier (VGA) and attenuators (ATT) are applied in the TX/RX beamforming ICs to achieve phase and gain tunings with large range and high precision. Based on the proposed beamforming ICs, the TX/RX phased arrays are realized with stacked aperture-coupled microstrip antennas on a cost-effective multi-layer PCB. Each array contains 32 TX/RX beamforming ICs, 256 antennas, and a 1-to-32 Wilkinson power divider/combiner networks. Fabricated in 65-nm CMOS technology, the packaged TX IC achieves an RMS gain error of 0.58 dB and an RMS phase error of 4.5° with 78.5-mW dc power per channel, while the $text {OP}_{text {1dB}}$ is 9.6 dBm at 50.5 GHz. The packaged RX IC realizes a 5.3-dB NF, 0.47-dB RMS gain error, and 1.7° RMS phase error with 24.2-mW dc power per channel. The Q/V-band phased arrays are capable of scanning ±60°, while the 256-element TX phased array achieves an EIRP of 63.5 dBm. Modulated signal measurements with 200- and 400-MHz QPSK, 16-QAM and 64-QAM are also provided.
{"title":"Q/V-Band CMOS Beamforming ICs and Integrated Phased-Array Antennas","authors":"Dixian Zhao;Weihan Gao;Ke Li;Hengzhi Wan;Qin Tian;Yongran Yi;Jiajun Zhang;Huiqi Liu","doi":"10.1109/TCSI.2024.3450668","DOIUrl":"10.1109/TCSI.2024.3450668","url":null,"abstract":"This paper presents 256-element transmitter (TX) and receiver (RX) phased arrays for satellite fixed communication at the Q and V bands, which integrate the phased-array antennas with eight-channel beamforming ICs. Wideband vector-modulated phase shifters (VGPS) and combinations of variable gain amplifier (VGA) and attenuators (ATT) are applied in the TX/RX beamforming ICs to achieve phase and gain tunings with large range and high precision. Based on the proposed beamforming ICs, the TX/RX phased arrays are realized with stacked aperture-coupled microstrip antennas on a cost-effective multi-layer PCB. Each array contains 32 TX/RX beamforming ICs, 256 antennas, and a 1-to-32 Wilkinson power divider/combiner networks. Fabricated in 65-nm CMOS technology, the packaged TX IC achieves an RMS gain error of 0.58 dB and an RMS phase error of 4.5° with 78.5-mW dc power per channel, while the <inline-formula> <tex-math>$text {OP}_{text {1dB}}$ </tex-math></inline-formula> is 9.6 dBm at 50.5 GHz. The packaged RX IC realizes a 5.3-dB NF, 0.47-dB RMS gain error, and 1.7° RMS phase error with 24.2-mW dc power per channel. The Q/V-band phased arrays are capable of scanning ±60°, while the 256-element TX phased array achieves an EIRP of 63.5 dBm. Modulated signal measurements with 200- and 400-MHz QPSK, 16-QAM and 64-QAM are also provided.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"776-789"},"PeriodicalIF":5.2,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents signal integrity augmentation design techniques in a 64-GBaud transimpedance amplifier (TIA) for coherent optical communication. In the FE-TIA, a bonding wire ringing reduction technique and an input DC current cancellation (IDCC) loop adapted for coherent communication are proposed. In the post amplifiers, a group delay variation (GDV) friendly bandwidth boosting technique is proposed to achieve optimal time domain performance. A non-linearity cancellation technique and a high-linearity gain control approach are proposed in both circuit and system levels. These signal integrity augmentation techniques form a toolkit to solve the design challenges in bandwidth, linearity, GDV, ringing, offset, crosstalk, etc. in high-speed high-order modulation communication. Fabricated in a 90-nm SiGe BiCMOS technology, the TIA shows input-referred noise current density of 15.1 pA/ $surd $ Hz, bandwidth of over 40 GHz with GDV less than ±3.75 ps. The TIA gain can be adjusted between $150~Omega $ - 5 K $Omega $ , which enables maximum overload input current of 3 mApp. The total harmonic distortion (THD) is less than 3% and the crosstalk between two channels is less than -3 dB. The chip consumes 264 mW from 3.3 V supply.
{"title":"Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS","authors":"Shuaizhe Ma;Nianquan Ran;Xi Liu;Yifei Xia;Songqin Xu;Wei Huang;Chen Tan;Jing Li;Zhenyu Yin;Shaoheng Lin;Jianhua Pan;Zhe Chen;Chaoxuan Zhang;Wu Wen;Quan Pan;Zhongming Xue;Xiaoyan Gui;Li Geng;Dan Li","doi":"10.1109/TCSI.2024.3450700","DOIUrl":"10.1109/TCSI.2024.3450700","url":null,"abstract":"This paper presents signal integrity augmentation design techniques in a 64-GBaud transimpedance amplifier (TIA) for coherent optical communication. In the FE-TIA, a bonding wire ringing reduction technique and an input DC current cancellation (IDCC) loop adapted for coherent communication are proposed. In the post amplifiers, a group delay variation (GDV) friendly bandwidth boosting technique is proposed to achieve optimal time domain performance. A non-linearity cancellation technique and a high-linearity gain control approach are proposed in both circuit and system levels. These signal integrity augmentation techniques form a toolkit to solve the design challenges in bandwidth, linearity, GDV, ringing, offset, crosstalk, etc. in high-speed high-order modulation communication. Fabricated in a 90-nm SiGe BiCMOS technology, the TIA shows input-referred noise current density of 15.1 pA/\u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000Hz, bandwidth of over 40 GHz with GDV less than ±3.75 ps. The TIA gain can be adjusted between \u0000<inline-formula> <tex-math>$150~Omega $ </tex-math></inline-formula>\u0000 - 5 K\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, which enables maximum overload input current of 3 mApp. The total harmonic distortion (THD) is less than 3% and the crosstalk between two channels is less than -3 dB. The chip consumes 264 mW from 3.3 V supply.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5221-5234"},"PeriodicalIF":5.2,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-04DOI: 10.1109/tcsi.2024.3451505
Dat-Thuc Nguyen, Ngoc Tuan Duong, Vo Anh Khoa
{"title":"Lipschitz Stability Estimate for an Initial Wave Reconstruction Problem of Telegraph Type With Gaussian Noise","authors":"Dat-Thuc Nguyen, Ngoc Tuan Duong, Vo Anh Khoa","doi":"10.1109/tcsi.2024.3451505","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3451505","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"13 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Spike-Timing-Dependent Plasticity (STDP) is a biological-plausible learning mechanism widely adopted for building Spiking Neural Networks (SNNs). It determines plasticity polarity and synapse strength change according to the timing difference between pre- and postsynaptic spikes. The learning curves of STDP differ in temporal window size, magnitude and polarity across different synapse types and brain regions and even within a cell, in different dendritic compartments. To accelerate on-chip STDP learning, various implementations have been proposed. However, they either introduce significant latency due to costly counter-based time difference calculation and substantial area cost due to the implementation of weight change LUTs, or lose biologically-plausible timing information due to oversimplification. For low-cost and efficient on-chip learning, a high-throughput Implicit-timing STDP (ImSTDP) with optimized SR depth and a low-cost register-based Implicit-Timing Look-up (ITL) are proposed. ASIC implementation in 22 nm technology demonstrates that ImSTDP can achieve up to $2times $ throughput improvement and $3.61times $ power efficiency improvement at 27% less area cost compared to the cutting-edge counter-LUT on-chip STDP learning solution.
{"title":"ImSTDP: Implicit Timing On-Chip STDP Learning","authors":"Dedong Zhao;Oliver Schrape;Zoran Stamenkovic;Milos Krstic","doi":"10.1109/TCSI.2024.3450958","DOIUrl":"10.1109/TCSI.2024.3450958","url":null,"abstract":"Spike-Timing-Dependent Plasticity (STDP) is a biological-plausible learning mechanism widely adopted for building Spiking Neural Networks (SNNs). It determines plasticity polarity and synapse strength change according to the timing difference between pre- and postsynaptic spikes. The learning curves of STDP differ in temporal window size, magnitude and polarity across different synapse types and brain regions and even within a cell, in different dendritic compartments. To accelerate on-chip STDP learning, various implementations have been proposed. However, they either introduce significant latency due to costly counter-based time difference calculation and substantial area cost due to the implementation of weight change LUTs, or lose biologically-plausible timing information due to oversimplification. For low-cost and efficient on-chip learning, a high-throughput Implicit-timing STDP (ImSTDP) with optimized SR depth and a low-cost register-based Implicit-Timing Look-up (ITL) are proposed. ASIC implementation in 22 nm technology demonstrates that ImSTDP can achieve up to <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> throughput improvement and <inline-formula> <tex-math>$3.61times $ </tex-math></inline-formula> power efficiency improvement at 27% less area cost compared to the cutting-edge counter-LUT on-chip STDP learning solution.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"868-881"},"PeriodicalIF":5.2,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-04DOI: 10.1109/TCSI.2024.3450875
Yong-Un Jeong;Joo-Hyung Chae
This paper presents a single-ended four-level pulse-amplitude modulation (PAM-4) transmitter using an unstacked tailless current-mode logic (CML) driver for memory interfaces. Compared with the voltage-mode (VM) driver commonly used for single-ended memory interfaces, the proposed CML driver has stable termination for impedance matching and a small pre-driver with low dynamic power consumption, which allow the transmitter to achieve a higher data rate and a better total energy efficiency. The unstacked driver structure with an auxiliary leg and a current calibration scheme leads to high PAM-4 linearity by compensating for channel-length modulation that causes current source variation while occupying a small area. The strength of the feed-forward equalization (FFE) distorted by channel-length modulation is also compensated by an additional pulse of the proposed coefficient-corrected equalization. A prototype chip fabricated in a 65-nm CMOS process has an area of 0.0172 mm $^{2}{}$ . It achieves a data rate of 34 Gb/s/pin with an energy efficiency of 0.60 pJ/bit and a level separation mismatch ratio (RLM) of 0.987.
{"title":"A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces","authors":"Yong-Un Jeong;Joo-Hyung Chae","doi":"10.1109/TCSI.2024.3450875","DOIUrl":"10.1109/TCSI.2024.3450875","url":null,"abstract":"This paper presents a single-ended four-level pulse-amplitude modulation (PAM-4) transmitter using an unstacked tailless current-mode logic (CML) driver for memory interfaces. Compared with the voltage-mode (VM) driver commonly used for single-ended memory interfaces, the proposed CML driver has stable termination for impedance matching and a small pre-driver with low dynamic power consumption, which allow the transmitter to achieve a higher data rate and a better total energy efficiency. The unstacked driver structure with an auxiliary leg and a current calibration scheme leads to high PAM-4 linearity by compensating for channel-length modulation that causes current source variation while occupying a small area. The strength of the feed-forward equalization (FFE) distorted by channel-length modulation is also compensated by an additional pulse of the proposed coefficient-corrected equalization. A prototype chip fabricated in a 65-nm CMOS process has an area of 0.0172 mm\u0000<inline-formula> <tex-math>$^{2}{}$ </tex-math></inline-formula>\u0000. It achieves a data rate of 34 Gb/s/pin with an energy efficiency of 0.60 pJ/bit and a level separation mismatch ratio (RLM) of 0.987.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6306-6315"},"PeriodicalIF":5.2,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-04DOI: 10.1109/TCSI.2024.3419425
Wei Chen;Yajie Li;Dake Liu
It is a great challenge to design an LDPC decoder with multi-standard compatibility, flexibility and low silicon overhead. This paper presents the efficient and low-overhead design of an LDPC decoder tailored for multi-standard, which include WLAN, 5G NR and WiMAX. We follow the design principles of Application-Specific Instruction-set Processor (ASIP). In order to enhance throughput, we double the computational speed by reducing memory speed from double logic speed to logic speed. By proposing the optimized hybrid scheduling algorithm based on matrix reordering, we further solve scheduling problems and eliminate pipeline conflicts. Through performing logic synthesis utilizing the 28 nm SMIC CMOS cell library, synthesis results show that the core area of our designed decoder is 0.86 mm2, the logic gate count is 1716 K, and our design achieves impressive throughput rates, that is up to 9.96 Gbps for WLAN, 7.69 Gbps for WiMAX, and 33 Gbps for 5G NR. Compared with other state-of-the-art LDPC decoders, the experimental results show that our proposed decoder has up to $4.5times $ higher throughput, $3.9times $ better area efficiency and $5.8times $ better energy efficiency than these state-of-the-art implementations.
设计一种兼容多标准、灵活、低硅开销的LDPC解码器是一个巨大的挑战。本文介绍了一种适用于WLAN、5G NR和WiMAX等多标准的高效低开销LDPC解码器设计。我们遵循专用指令集处理器（Application-Specific Instruction-set Processor， ASIP）的设计原则。为了提高吞吐量，我们通过将内存速度从双逻辑速度降低到逻辑速度来提高计算速度。通过提出基于矩阵重排序的优化混合调度算法，进一步解决了调度问题，消除了流水线冲突。通过执行逻辑综合利用28 nm中芯国际CMOS单元库,综合结果表明,我们设计了译码器的核心面积是0.86平方毫米,逻辑门数是1716 K,和我们的设计达到令人印象深刻的吞吐率,9.96 Gbps的WLAN, WiMAX 7.69 Gbps,并为5 g NR 33 Gbps。与其他先进的LDPC的解码器相比,实验结果表明,我们建议的解码器有4.5美元 *美元更高的吞吐量,比这些最先进的设备面积效率高3.9倍，能源效率高5.8倍。
{"title":"High-Throughput LDPC Decoder for Multiple Wireless Standards","authors":"Wei Chen;Yajie Li;Dake Liu","doi":"10.1109/TCSI.2024.3419425","DOIUrl":"10.1109/TCSI.2024.3419425","url":null,"abstract":"It is a great challenge to design an LDPC decoder with multi-standard compatibility, flexibility and low silicon overhead. This paper presents the efficient and low-overhead design of an LDPC decoder tailored for multi-standard, which include WLAN, 5G NR and WiMAX. We follow the design principles of Application-Specific Instruction-set Processor (ASIP). In order to enhance throughput, we double the computational speed by reducing memory speed from double logic speed to logic speed. By proposing the optimized hybrid scheduling algorithm based on matrix reordering, we further solve scheduling problems and eliminate pipeline conflicts. Through performing logic synthesis utilizing the 28 nm SMIC CMOS cell library, synthesis results show that the core area of our designed decoder is 0.86 mm2, the logic gate count is 1716 K, and our design achieves impressive throughput rates, that is up to 9.96 Gbps for WLAN, 7.69 Gbps for WiMAX, and 33 Gbps for 5G NR. Compared with other state-of-the-art LDPC decoders, the experimental results show that our proposed decoder has up to \u0000<inline-formula> <tex-math>$4.5times $ </tex-math></inline-formula>\u0000 higher throughput, \u0000<inline-formula> <tex-math>$3.9times $ </tex-math></inline-formula>\u0000 better area efficiency and \u0000<inline-formula> <tex-math>$5.8times $ </tex-math></inline-formula>\u0000 better energy efficiency than these state-of-the-art implementations.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"383-396"},"PeriodicalIF":5.2,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the distributed secondary voltage and frequency restoration problem is addressed in AC microgrid systems subjected to hybrid false data injection (FDI) and denial-of-service (DoS) attacks. Firstly, a new distributed resilient iterative estimator based on the k-step estimation method is proposed that can accurately estimate the FDI attack signals as well as the voltage and frequency of each distributed generation (DG) even under the impact of DoS attacks. Then, based on the mean value of the attack estimation signal, a distributed resilient secondary controller is designed to compensate for the considered hybrid attacks. Compared with existing researches on resilient control of AC microgrids under hybrid attacks, the voltage and frequency regulation errors of the microgrid system converge to zero for the first time. Finally, the precise convergence of voltage and frequency in the AC microgrid system under the proposed method is verified through a real-time controller-hardware-in-the-loop experiment in OPAL-RT.
本文探讨了交流微电网系统在受到混合虚假数据注入（FDI）和拒绝服务（DoS）攻击时的分布式二次电压和频率恢复问题。首先，提出了一种基于 k 步估计法的新型分布式弹性迭代估计器，即使在 DoS 攻击的影响下，也能准确估计 FDI 攻击信号以及各分布式发电（DG）的电压和频率。然后，基于攻击估计信号的平均值，设计了一种分布式弹性二次控制器来补偿所考虑的混合攻击。与现有的混合攻击下交流微电网弹性控制研究相比，微电网系统的电压和频率调节误差首次收敛为零。最后，通过在 OPAL-RT 中进行实时控制器-硬件在环实验，验证了所提方法下交流微电网系统电压和频率的精确收敛性。
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