{"title":"A Synchronous Current Inversion and Energy Extraction Circuit for Electromagnetic Energy Harvesting Enhancement","authors":"Jiacong Qiu, Haoyu Wang, Yu Liu, Minfan Fu, Junrui Liang","doi":"10.1109/tcsi.2024.3430055","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3430055","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141775240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-24DOI: 10.1109/tcsi.2024.3431588
Mei Guo, Lingtong Kong, Gang Dou, Herbert Ho-Ching Iu
{"title":"Neuromorphic Circuit of Classical and Operant Conditioning Based on Tunable Neural Circuitry Motifs","authors":"Mei Guo, Lingtong Kong, Gang Dou, Herbert Ho-Ching Iu","doi":"10.1109/tcsi.2024.3431588","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3431588","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141775237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-24DOI: 10.1109/TCSI.2024.3411883
Zhizheng Gan;Lu Qu;Zhanqing Yu;Xin Yan;Rong Zeng;Biao Zhao;Yulong Huang;Wei Li
Hybrid DC circuit breakers (HDCCBs) are among the most promising solutions for DC breaking. HDCCBs based on forced commutation have the shortcomings of conduction loss or high cost, which hinders their large-scale application. HDCCBs based on natural commutation, despite their lower cost and smaller volume, are limited by the arc voltage. Therefore, this paper proposes a type of multibreak mechanical switch applicable for medium-voltage natural commutation HDCCBs. Possessing the advantages of compact size and high arc voltage, the switch consists of a four-break gas chamber and a vacuum chamber, the former of which realizes the series connection of multiple arcs through a bridge contact structure. The vacuum chamber is used to bear the turn-off overvoltage. Combined with high-speed observation methods, the mechanical characteristics and arc characteristics of the multibreak mechanical switch are analyzed, and the influence mechanism of different factors on the arc characteristics of the four-break chamber is revealed. On this basis, a principle prototype of the 15 kV medium-voltage natural commutation HDCCB was developed, and breaking tests were carried out. The breaking current can reach 15 kA, and the breaking time is less than 3 ms.
{"title":"A Multi-Break Mechanical Switch Applicable for Medium Voltage Natural Commutation DC Circuit Breakers","authors":"Zhizheng Gan;Lu Qu;Zhanqing Yu;Xin Yan;Rong Zeng;Biao Zhao;Yulong Huang;Wei Li","doi":"10.1109/TCSI.2024.3411883","DOIUrl":"10.1109/TCSI.2024.3411883","url":null,"abstract":"Hybrid DC circuit breakers (HDCCBs) are among the most promising solutions for DC breaking. HDCCBs based on forced commutation have the shortcomings of conduction loss or high cost, which hinders their large-scale application. HDCCBs based on natural commutation, despite their lower cost and smaller volume, are limited by the arc voltage. Therefore, this paper proposes a type of multibreak mechanical switch applicable for medium-voltage natural commutation HDCCBs. Possessing the advantages of compact size and high arc voltage, the switch consists of a four-break gas chamber and a vacuum chamber, the former of which realizes the series connection of multiple arcs through a bridge contact structure. The vacuum chamber is used to bear the turn-off overvoltage. Combined with high-speed observation methods, the mechanical characteristics and arc characteristics of the multibreak mechanical switch are analyzed, and the influence mechanism of different factors on the arc characteristics of the four-break chamber is revealed. On this basis, a principle prototype of the 15 kV medium-voltage natural commutation HDCCB was developed, and breaking tests were carried out. The breaking current can reach 15 kA, and the breaking time is less than 3 ms.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.2,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141785263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-24DOI: 10.1109/tcsi.2024.3430048
Zain ul Aabidin Lodhi, Kai Zhang, Bin Zhou, Huaiyuan Jiang
{"title":"Adaptive Prescribed-Time Consensus for a Class of Nonlinear Multi-Agent Networks by Bounded Time-Varying Protocols","authors":"Zain ul Aabidin Lodhi, Kai Zhang, Bin Zhou, Huaiyuan Jiang","doi":"10.1109/tcsi.2024.3430048","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3430048","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141775238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-23DOI: 10.1109/tcsi.2024.3425642
Guangyi Zhang, Wenjun Huang
{"title":"Advancing Circuit Transient Response Macromodeling: From Conventional Neural Networks to Siamese-LSTM","authors":"Guangyi Zhang, Wenjun Huang","doi":"10.1109/tcsi.2024.3425642","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3425642","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141775529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-23DOI: 10.1109/tcsi.2024.3430930
Ning Wang, Dan Xu, Yan Yang, Fatemeh Parastesh, Herbert Ho-Ching Iu, Quan Xu
{"title":"Dual Memristive Chua’s Circuit","authors":"Ning Wang, Dan Xu, Yan Yang, Fatemeh Parastesh, Herbert Ho-Ching Iu, Quan Xu","doi":"10.1109/tcsi.2024.3430930","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3430930","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141775241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-23DOI: 10.1109/TCSI.2024.3413784
Song Ding;Zheng Zhang;Li Chen;Qinsong Qian;Weifeng Sun
There are two drawbacks in the previous tri-mode variable-frequency peak current mode (VFPCM) control for primary side regulation (PSR) double-clamp zero voltage switching (DCZVS) flyback converter: firstly, the current-sense resistor leads to non-negligible loss at high power and instability at high frequency; secondly, the previous tri-mode control suffers from poor dynamic performance and lacks accurate small-signal model in various control modes. In this paper, a novel sensorless current quad-mode control is proposed, which eliminates the current-sense resistor by input voltage feed-forward and improve the dynamic performance by introducing hybrid mode (HYM) and seamless mode-switch. In addition, a unified small-signal model of the four control modes is derived in the paper, which explains the high dynamic performance of the introduced HYM. The proposed sensorless current quad-mode control and the unified small-signal model are validated on a 16-50V input and 28V/320W output experimental prototype. Compared with the traditional tri-mode peak current mode control, the undershoot recovery time and overshoot recovery time of the proposed control scheme are reduced from 12ms to 2.0ms and 12ms to 1.6ms, respectively.
{"title":"Novel Sensorless Current Multimode Control for PSR Double-Clamp ZVS (DCZVS) Flyback Converter in DCM and CrCM","authors":"Song Ding;Zheng Zhang;Li Chen;Qinsong Qian;Weifeng Sun","doi":"10.1109/TCSI.2024.3413784","DOIUrl":"10.1109/TCSI.2024.3413784","url":null,"abstract":"There are two drawbacks in the previous tri-mode variable-frequency peak current mode (VFPCM) control for primary side regulation (PSR) double-clamp zero voltage switching (DCZVS) flyback converter: firstly, the current-sense resistor leads to non-negligible loss at high power and instability at high frequency; secondly, the previous tri-mode control suffers from poor dynamic performance and lacks accurate small-signal model in various control modes. In this paper, a novel sensorless current quad-mode control is proposed, which eliminates the current-sense resistor by input voltage feed-forward and improve the dynamic performance by introducing hybrid mode (HYM) and seamless mode-switch. In addition, a unified small-signal model of the four control modes is derived in the paper, which explains the high dynamic performance of the introduced HYM. The proposed sensorless current quad-mode control and the unified small-signal model are validated on a 16-50V input and 28V/320W output experimental prototype. Compared with the traditional tri-mode peak current mode control, the undershoot recovery time and overshoot recovery time of the proposed control scheme are reduced from 12ms to 2.0ms and 12ms to 1.6ms, respectively.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.2,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141775519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-23DOI: 10.1109/TCSI.2024.3429174
Anuj Verma;Rahul Shrestha
This manuscript proposes hardware-efficient and high-throughput reconfigurable architecture of the channel decoder for unified decoding of LDPC or polar code. It has been designed based on the new dataflow technique for reconfigurable decoding that incurs lesser hardware resources in the decoder design. In addition, this work presents memory-organized architecture that exploits the shared-memory hardware and also excludes various conventional sub modules. Furthermore, this reconfigurable LDPC/polar decoder has been ASIC fabricated in UMC 110 nm-CMOS technology node, occupying an area of 1.96 mm2. It supports multiple code-rates and code-lengths that are compliant to mMTC and URLLC applications of 5G-NR wireless communication standard. At the supply voltage of 1.2 V, the proposed decoder-chip operates at the measured clock frequency of 72.7 MHz and delivers a data throughput of 3.35 Gbps that is $4{times }$