This article presents the design theory and implementation of a fully integrated coupled-line-based load-modulated balanced amplifier (CLLMBA) monolithic microwave integrated circuit (MMIC). To facilitate the design, a novel design method is proposed for the CLLMBA to precisely control the load modulation and output power back-off (OBO) level by arranging the current ratio among the control amplifier (CA) and balanced amplifiers (BAs). Moreover, to further expand the working bandwidth, the coupled-line couplers are adopted in the CLLMBA. Subsequently, the physical dimensions and operating conditions of the three sub-amplifiers are selected accurately based on load modulation analysis at the fundamental frequency. It leads to properly modulated impedances and cancels the output matching networks for sub-amplifiers. Besides, meandering lange couplers are adopted by double metal layers and air-bridges for a compact layout. To validate the proposed techniques, a CLLMBA prototype is implemented and fabricated in a commercial 0.25- $mu $ m GaN HEMT process with the die size of $3.1times 2.3$ mm2. The measurement result exhibits a 38.1-39.3 dBm saturated output power with a 45.8%-57.6% saturated drain efficiency (DE), and a 31.7%-42.3% DE at 10-dB OBO from 4 to 6 GHz. Furthermore, under a 100 MHz orthogonal frequency division multiplexing (OFDM) signal with 8.5 dB peak-to-average power ratio (PAPR), the average DE is 32.8%-40.6% and the adjacent channel leakage ratio (ACLR) after digital predistortion is better than −47.5 dBc.
本文介绍了一种基于全集成耦合线负载调制平衡放大器（CLLMBA）的单片微波集成电路（MMIC）的设计原理和实现方法。为了方便设计，提出了一种新的CLLMBA设计方法，通过安排控制放大器（CA）和平衡放大器（BAs）之间的电流比来精确控制负载调制和输出功率回退（OBO）电平。此外，为了进一步扩大工作带宽，CLLMBA采用了耦合线耦合器。随后，基于基频下的负载调制分析，精确选择了三个子放大器的物理尺寸和工作条件。它导致适当调制的阻抗，并消除了子放大器的输出匹配网络。双金属层和空气桥采用曲径兰格耦合器，布局紧凑。为了验证所提出的技术，在0.25- $ $ mu $ m GaN HEMT工艺中实现并制造了CLLMBA原型，其模具尺寸为$3.1 × 2.3$ mm2。测量结果显示，在4 ~ 6 GHz范围内，10 db OBO的饱和输出功率为38.1 ~ 39.3 dBm，饱和漏极效率（DE）为45.8% ~ 57.6%，DE为31.7% ~ 42.3%。此外，在峰均功率比（PAPR）为8.5 dB的100 MHz正交频分复用（OFDM）信号下，平均DE为32.8% ~ 40.6%，数字预失真后的相邻信道泄漏比（ACLR）优于- 47.5 dBc。
{"title":"Design and Analysis of a Coupled-Line-Based Load-Modulated Balanced Amplifier MMIC With Enhanced Bandwidth Performance","authors":"Jingyuan Zhang;Weichen Zhao;Baoguo Yang;Xu Yan;Yongxin Guo","doi":"10.1109/TCSI.2024.3489555","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3489555","url":null,"abstract":"This article presents the design theory and implementation of a fully integrated coupled-line-based load-modulated balanced amplifier (CLLMBA) monolithic microwave integrated circuit (MMIC). To facilitate the design, a novel design method is proposed for the CLLMBA to precisely control the load modulation and output power back-off (OBO) level by arranging the current ratio among the control amplifier (CA) and balanced amplifiers (BAs). Moreover, to further expand the working bandwidth, the coupled-line couplers are adopted in the CLLMBA. Subsequently, the physical dimensions and operating conditions of the three sub-amplifiers are selected accurately based on load modulation analysis at the fundamental frequency. It leads to properly modulated impedances and cancels the output matching networks for sub-amplifiers. Besides, meandering lange couplers are adopted by double metal layers and air-bridges for a compact layout. To validate the proposed techniques, a CLLMBA prototype is implemented and fabricated in a commercial 0.25-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m GaN HEMT process with the die size of \u0000<inline-formula> <tex-math>$3.1times 2.3$ </tex-math></inline-formula>\u0000 mm2. The measurement result exhibits a 38.1-39.3 dBm saturated output power with a 45.8%-57.6% saturated drain efficiency (DE), and a 31.7%-42.3% DE at 10-dB OBO from 4 to 6 GHz. Furthermore, under a 100 MHz orthogonal frequency division multiplexing (OFDM) signal with 8.5 dB peak-to-average power ratio (PAPR), the average DE is 32.8%-40.6% and the adjacent channel leakage ratio (ACLR) after digital predistortion is better than −47.5 dBc.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"111-124"},"PeriodicalIF":5.2,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a time-domain mixed-signal computing architecture for Matrix-Vector Multiplication suited for embedded in-memory computing applications. The system leverages the low data rate of sensors’ data in embedded AI applications to target an energy-efficient implementation of the matrix-vector multiplication array. The mixed-signal computing scheme relies on incremental time-domain multiply-and-accumulate operations using switched current sources. The concept is demonstrated on a 28nm FDSOI prototype chip of a 100 $times $ 4 compute array that shows a 15.8TOPS/W energy efficiency for 5-bit MAC operations. Extrapolating the array to 100 $times $ 100 computing units leads to a 99.2TOPS/W energy efficiency.
{"title":"An Incremental Time-Domain Mixed-Signal Matrix-Vector-Multiplication Technique for Low-Power Edge-AI","authors":"Kévin Hérissé;Benoit Larras;Bruno Stefanelli;Andreas Kaiser;Antoine Frappé","doi":"10.1109/TCSI.2024.3480154","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3480154","url":null,"abstract":"This paper proposes a time-domain mixed-signal computing architecture for Matrix-Vector Multiplication suited for embedded in-memory computing applications. The system leverages the low data rate of sensors’ data in embedded AI applications to target an energy-efficient implementation of the matrix-vector multiplication array. The mixed-signal computing scheme relies on incremental time-domain multiply-and-accumulate operations using switched current sources. The concept is demonstrated on a 28nm FDSOI prototype chip of a 100\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u00004 compute array that shows a 15.8TOPS/W energy efficiency for 5-bit MAC operations. Extrapolating the array to 100\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000100 computing units leads to a 99.2TOPS/W energy efficiency.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6470-6481"},"PeriodicalIF":5.2,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-28DOI: 10.1109/TCSI.2024.3480951
Yushan Liu;Jianyu Cao;Xiao Li
In power conversion applications utilizing GaN HEMTs at elevated switching frequencies, the predominant source of power loss is attributed to switching, which becomes particularly sensitive to parasitic parameters due to the rapid switching operation. Traditional methods of calculating switching loss have exhibited inconsistencies when applied to designs incorporating GaN HEMTs and various operational conditions. Consequently, there is a pressing need for more precise methods to estimate switching loss in GaN HEMTs. This paper introduces two distinct switching loss calculation models, presented both as empirical formulas and analytical models. These models take into account the influence of critical parasitic inductances and junction temperature. The comparative analysis of these two calculation methods with the experimental results is provided to demonstrate their efficacy. Furthermore, the impact of nonideal factors, such as power loop parasitic inductance, common-source inductance, and junction temperature, is assessed.
在利用 GaN HEMT 实现开关频率较高的功率转换应用中，功率损耗的主要来源是开关，而由于快速开关操作，开关损耗对寄生参数尤为敏感。传统的开关损耗计算方法在应用于包含氮化镓 HEMT 的设计和各种工作条件时表现出不一致性。因此，迫切需要更精确的方法来估算 GaN HEMT 的开关损耗。本文介绍了两种不同的开关损耗计算模型，既有经验公式，也有分析模型。这些模型考虑了临界寄生电感和结温的影响。这两种计算方法与实验结果的对比分析证明了它们的有效性。此外，还评估了功率回路寄生电感、共源电感和结温等非理想因素的影响。
{"title":"Switching Loss Model for Fast-Switching GaN HEMT in Half-Bridge Circuit Considering Parasitic Inductance and Temperature Effect","authors":"Yushan Liu;Jianyu Cao;Xiao Li","doi":"10.1109/TCSI.2024.3480951","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3480951","url":null,"abstract":"In power conversion applications utilizing GaN HEMTs at elevated switching frequencies, the predominant source of power loss is attributed to switching, which becomes particularly sensitive to parasitic parameters due to the rapid switching operation. Traditional methods of calculating switching loss have exhibited inconsistencies when applied to designs incorporating GaN HEMTs and various operational conditions. Consequently, there is a pressing need for more precise methods to estimate switching loss in GaN HEMTs. This paper introduces two distinct switching loss calculation models, presented both as empirical formulas and analytical models. These models take into account the influence of critical parasitic inductances and junction temperature. The comparative analysis of these two calculation methods with the experimental results is provided to demonstrate their efficacy. Furthermore, the impact of nonideal factors, such as power loop parasitic inductance, common-source inductance, and junction temperature, is assessed.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6128-6137"},"PeriodicalIF":5.2,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/TCSI.2024.3469775
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2024.3469775","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3469775","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736188","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/TCSI.2024.3471029
Xinmiao Zhang
{"title":"Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2024","authors":"Xinmiao Zhang","doi":"10.1109/TCSI.2024.3471029","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3471029","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"4899-4899"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736185","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142555138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/TCSI.2024.3477149
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TCSI.2024.3477149","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3477149","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5371-5371"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736148","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we introduce a novel approach to achieving lightweight device authentication through the use of a low-complexity Convolutional Neural Network (CNN). In our work, we improve the False Authentication Rate (FAR) by transforming the standard CNN into a Bayesian CNN (BCNN or BNN). This transformation enables the use of probabilistic modelling techniques, increasing the model’s robustness and its confidence in authentication decisions. Regardless of the model used, clients authenticate with a retention-based Dynamic Random Access Memory Physical Unclonable Function (DRAM PUF) response. Our approach integrates the low computational complexity of the CNN with the intrinsic security characteristics of the DRAM PUF, offering a robust solution for lightweight and secure device authentication.
{"title":"Achieving Error-Free Lightweight Authentication With DRAM-Based Physical Unclonable Functions","authors":"Nico Mexis;Nikolaos Athanasios Anagnostopoulos;Stefan Katzenbeisser;Elif Bilge Kavun;Sara Tehranipoor;Tolga Arul","doi":"10.1109/TCSI.2024.3480852","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3480852","url":null,"abstract":"In this article, we introduce a novel approach to achieving lightweight device authentication through the use of a low-complexity Convolutional Neural Network (CNN). In our work, we improve the False Authentication Rate (FAR) by transforming the standard CNN into a Bayesian CNN (BCNN or BNN). This transformation enables the use of probabilistic modelling techniques, increasing the model’s robustness and its confidence in authentication decisions. Regardless of the model used, clients authenticate with a retention-based Dynamic Random Access Memory Physical Unclonable Function (DRAM PUF) response. Our approach integrates the low computational complexity of the CNN with the intrinsic security characteristics of the DRAM PUF, offering a robust solution for lightweight and secure device authentication.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"637-646"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/TCSI.2024.3447276
Philex Ming-Yan Fan;Chen-An Chen;Chih-Hao Wang;Hsiang-Yu Ko
The first 1.1V-programmable metal-fuse technology in 28nm CMOS technology is reported in this work. The prototyped 1Kb-memory array featuring a $12.4mu $ m2 1T1R bit cell adopts the proposed current-mode programming (CMP) scheme. The CMP scheme achieves a record low programming voltage of 1.1V, surpassing the programming voltages (≥1.6V) required by prior metal-fuse CMOS and FinFET technologies. To ensure successful programming, a closed-loop detector (CLD) employing an on-chip hysteresis comparator detects resistance transition in bit cells during programming. Preliminary experiments demonstrate that the proposed CMP scheme along with CLD achieves a 100% of yield after programming 960 bits at room temperature. Under various programming conditions, the combination of CMP and CLD demonstrates programming robustness, with resistance ratios before and after programming equal to and greater than three orders of magnitude. The measured results suggest a promising method for mitigating over-stress issues associated with high programming voltages used in prior art.
{"title":"A 1.1 V-Programmable Metal-Fuse Technology With Current-Mode Programming and Program-Guarantee Technique in 28 nm CMOS Technology","authors":"Philex Ming-Yan Fan;Chen-An Chen;Chih-Hao Wang;Hsiang-Yu Ko","doi":"10.1109/TCSI.2024.3447276","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3447276","url":null,"abstract":"The first 1.1V-programmable metal-fuse technology in 28nm CMOS technology is reported in this work. The prototyped 1Kb-memory array featuring a <inline-formula> <tex-math>$12.4mu $ </tex-math></inline-formula>m2 1T1R bit cell adopts the proposed current-mode programming (CMP) scheme. The CMP scheme achieves a record low programming voltage of 1.1V, surpassing the programming voltages (≥1.6V) required by prior metal-fuse CMOS and FinFET technologies. To ensure successful programming, a closed-loop detector (CLD) employing an on-chip hysteresis comparator detects resistance transition in bit cells during programming. Preliminary experiments demonstrate that the proposed CMP scheme along with CLD achieves a 100% of yield after programming 960 bits at room temperature. Under various programming conditions, the combination of CMP and CLD demonstrates programming robustness, with resistance ratios before and after programming equal to and greater than three orders of magnitude. The measured results suggest a promising method for mitigating over-stress issues associated with high programming voltages used in prior art.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"685-693"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/TCSI.2024.3469773
{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2024.3469773","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3469773","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5372-5372"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736147","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/TCSI.2024.3481904
Xu Wang;Michael Peter Kennedy
Digital-to-time converters (DTC’s) used in fractional-N frequency synthesizers attempt to cancel the accumulated quantization error (QE) introduced by the divider controller with a view to recovering the integer-N phase noise (PN) performance. The resolution of the DTC needs to be sufficiently fine to suppress its own QE below the intrinsic integer-N jitter and, at the same time, sufficiently coarse to limit the DTC’s hardware needs. In this manuscript, we propose optimal strategies to determine the effective dynamic range, number of bits, quantization resolution, and unity delay of the DTC to achieve these goals; the additional jitter power introduced by input-dithered quantization methods to eliminate DTC-quantization-induced spurs is also considered. DTCs parameterized following these strategies can come close to realizing the spur-free integer-N PN with minimum hardware. Behavioral simulations confirm our analysis.
{"title":"Method to Determine Quantization-Related Parameters of the Digital-to-Time Converter in a Fractional-N Frequency Synthesizer","authors":"Xu Wang;Michael Peter Kennedy","doi":"10.1109/TCSI.2024.3481904","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3481904","url":null,"abstract":"Digital-to-time converters (DTC’s) used in fractional-N frequency synthesizers attempt to cancel the accumulated quantization error (QE) introduced by the divider controller with a view to recovering the integer-N phase noise (PN) performance. The resolution of the DTC needs to be sufficiently fine to suppress its own QE below the intrinsic integer-N jitter and, at the same time, sufficiently coarse to limit the DTC’s hardware needs. In this manuscript, we propose optimal strategies to determine the effective dynamic range, number of bits, quantization resolution, and unity delay of the DTC to achieve these goals; the additional jitter power introduced by input-dithered quantization methods to eliminate DTC-quantization-induced spurs is also considered. DTCs parameterized following these strategies can come close to realizing the spur-free integer-N PN with minimum hardware. Behavioral simulations confirm our analysis.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"708-718"},"PeriodicalIF":5.2,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736006","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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