IEEE Transactions on Circuits and Systems I: Regular Papers最新文献

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2024.3494637","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3494637","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6584-6584"},"PeriodicalIF":5.2,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10768280","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Guest Editorial Special Issue on the International Symposium on Circuits and Systems—ISCAS 2024","authors":"Xinmiao Zhang","doi":"10.1109/TCSI.2024.3494892","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3494892","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5375-5375"},"PeriodicalIF":5.2,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10768277","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2024.3494635","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3494635","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10768278","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2024.3494639","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3494639","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10768430","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A SPAD Image Sensor With Main-Sub-TDC-Based Coincidence Detection","authors":"Chenggong Wan;Yi Zhu;Yingjie Ma;Xue Li;Lixia Zheng;Jin Wu;Weifeng Sun","doi":"10.1109/TCSI.2024.3503422","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3503422","url":null,"abstract":"Light detection and ranging (Lidar) is usually enabled by Single-Photon Avalanche Detector (SPAD) sensors which may be falsely triggered by ambient light. Coincidence detection can suppress the ambient light at the cost of the lateral resolution. A \u0000<inline-formula> <tex-math>$64times 64$ </tex-math></inline-formula>\u0000 SPAD image sensor with coincidence detection is proposed for Lidar. A main-sub time-to-digital converter (TDC), in which the main TDC is used for timestamping the coincidence window and the sub-TDC is used for timestamping the event within the coincidence window, is proposed to avoid the loss of the lateral resolution at a small power cost. A delay-locked loop (DLL) is adopted to generate an analog voltage for maintaining the length of the coincidence window against process-voltage-temperature (PVT) variations. A TDC code correction circuit is proposed to reduce the probability of TDC inter-segment errors to 0.7%. The SPAD image sensor is based on the 3D integration of a SPAD array with a ROIC. The ROIC chip is fabricated in a \u0000<inline-formula> <tex-math>$0.18mu $ </tex-math></inline-formula>\u0000m CMOS process. Driven by a 250 MHz multi-phase clock and a 100 MHz data readout clock, the chip achieves a maximum frame rate of 35.7 kframe/s, a timing resolution of 0.5 ns, and a timing range of \u0000<inline-formula> <tex-math>$2mu $ </tex-math></inline-formula>\u0000s. The typical average power consumption of the ROIC is 135.5 mW (@21.7 kframes/s). The measured differential nonlinearity (DNL) ranges from -0.74 to +0.82 least significant bit (LSB), and the integral nonlinearity (INL) ranges from -0.95 to +0.95 LSB.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"50-60"},"PeriodicalIF":5.2,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Back-Gate Bias Control on EVM Measurements of a Dual-Band Power Amplifier in 22 nm FD-SOI for 5G 28 and 39 GHz Applications","authors":"Lucas Nyssens;M. Nabet;M. Rack;Y. Bendou;S. Wane;J. B. Sombrin;J.-P. Raskin;D. Lederer","doi":"10.1109/TCSI.2024.3487636","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3487636","url":null,"abstract":"This paper presents a dual-band power amplifier (PA) covering the 5G n257 to n260 frequency 2 bands (24.25 to 29.5 GHz and 37 to 43.5 GHz), fabricated in the 22 nm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Its design is based on a distributed balun at the output that efficiently performs a wideband load impedance transformation. The back-gate terminal of each transistor is connected to different pads for detailed back-gate bias variation analysis. Under 5G new radio (NR) modulated signal measurements, we show how the average output power and efficiency can be optimized by varying the back-gate bias, which optimal value depends on (i) the signal bandwidth, (ii) the carrier frequency and (iii) the target error-vector-magnitude (EVM) value. To the best of the authors’ knowledge, the impact of back-gate bias control on the system-level EVM figure of merit is shown for the first time in this work. Overall, with 7.5 dBm and 7.3% mean output power and efficiency, respectively, at 27 GHz, 6 dBm and 5% at 40 GHz, for a 800 MHz bandwidth 5G NR signal, the presented PA shows outstanding performance among wideband/multiband FD-SOI-based PAs covering the 28 and 39 GHz bands, featuring comparable performance to best-in-class narrowband PA designs in FD-SOI technology.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"753-762"},"PeriodicalIF":5.2,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 3-D Multi-Precision Scalable Systolic FMA Architecture","authors":"Haotian Liu;Xicheng Lu;Xiaoyu Yu;Kai Li;Kaiyuan Yang;Haihang Xia;Sizhao Li;Tiantai Deng","doi":"10.1109/TCSI.2024.3497724","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3497724","url":null,"abstract":"Artificial Intelligence (AI) has almost become the default approach in a wide range of applications, such as computer vision, chatbots, and natural language processing. These AI-based applications require computing large-scale data with sufficient precision, typically in floating-point numbers, within a limited time window. A primary target for AI acceleration is matrix multiplication, mainly involving dot products through Multiply-Accumulate (MAC) operations. Current research employs the Fused Multiply-Add (FMA) operation, based on IEEE-754 Floating Point (FP) standard, to meet these requirements. However, current research focuses more on simplifying the internal digital circuits of the Processing Elements (PEs) performing FMA operations, rather than optimizing the FMA process specifically for MAC tasks. Current PE arrays often use a two-dimensional (2-D) systolic array design, without specific optimization for MAC operations, thus their parallelism is not fully utilized. Additionally, these designs lack reconfigurability and flexibility, leading to suboptimal performance on Field-Programmable Gate Arrays (FPGAs). Moreover, some designs adopt lower precision computing in AI inference for higher performance. However, some AI models still rely on high-precision computing to maintain the accuracy. Thus, multi-precision computing is commonly used in AI accelerators. To address these challenges, this paper proposes a novel Multi-Fused Multiply-Accumulate (MFMA) scheme and a corresponding three-dimensional (3-D) scalable systolic FP computing architecture. The MFMA scheme addresses the problem of the classical FMA scheme. It optimizes FMA for MAC operations with the Fused Multiply-Accumulate (FMAC) operation. Also, it combines multi-precision and mixed-precision FP computing methods for higher accuracy and lower overflow error. The proposed architecture integrates two 2-D systolic arrays into the PE for a 3-D systolic array, achieving higher parallelism and flexibility. The proposed scalable architecture can be customized to suit various FMAC operations. Compared with existing state-of-the-art FP architectures on FPGAs, our proposed architecture achieves 47%, 10%, and 159% energy efficiency improvements in FP32, FP16, and INT8 operations, respectively. Furthermore, our proposed architecture achieves energy efficiency improvements of 105%, 54%, and 262% under efficiency saturation conditions, outperforming the existing state-of-the-art design.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"265-276"},"PeriodicalIF":5.2,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Single- and Dual-Band Rectifiers With Wide Range of Load Variations","authors":"Kai Biao Zhang;Bai Hua Zeng;Shao Yong Zheng;Ming Hua Xia","doi":"10.1109/TCSI.2024.3426081","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3426081","url":null,"abstract":"With the development of low-power devices, wireless power transfer and wireless energy harvesting techniques become increasingly important. As the critical component, the rectifier is required to maintain good performance under different scenarios. Most existing works focus on the improvement in bandwidth and input power range with a constant load value. However, the impedance of the driven devices cannot be predicted in practical applications, resulting in performance deterioration. Thus, an adaptive signal diversion approach is proposed to diver the injected signal to the parallel high and low load branches with distinct reactance compensation networks. This topology can be applied to both single- and dual-band rectifiers with simplicity and scalability in design. For validation, two rectifiers are designed, fabricated, and measured. The rectifier operating at 2.4 GHz achieves a load range of 0.16 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 to 6 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 (load variation ratio of 37.5). The dual-band rectifier working at 2.49 GHz and 5.14 GHz achieves load ranges from 0.21 to 5.4 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 (load variation ratio of 25.7) and from 0.07 to 4.2 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000 (load variation ratio of 60), respectively. It can be found that the proposed rectifiers exhibit the largest load variation ratio with the minimum number of diodes and load compared with the state-of-the-art works.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5873-5883"},"PeriodicalIF":5.2,"publicationDate":"2024-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142757860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Detection and Localization of Hardware-Assisted Intermittent Power Attacks in Mixed-Critical Systems","authors":"Sneha Agarwal;Keshav Goel;Mitali Sinha;Sidhartha Sankar Rout;Sujay Deb","doi":"10.1109/TCSI.2024.3493386","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3493386","url":null,"abstract":"Increasing complexity in power management (PMT) has led to a growing demand for third-party power managers (3PPMs) in Network-on-Chip based Mixed-Critical Systems (NoCMCS). However, a malicious 3PPM can exploit the interdependence of power amongst the router nodes to orchestrate well-structured, covert power attacks. Detection and localization of a malicious 3PPM is crucial to restore standard dynamic PMT and mitigating system performance degradation. We propose a novel, non-invasive, low-overhead, attack detection and localization framework for Hardware Trojan (HT)-assisted intermittent power attacks with random activation and deactivation phases in NoCMCS. In Phase-I, our framework makes use of pre-profiled thermal statistics of router nodes to detect any anomaly at runtime. In Phase-II, it leverages a self-aware methodology to locate the router nodes with malicious 3PPM. The proposed framework can detect multiple intermittent HTs in the network. Experimental evaluations on real-life benchmarks show that Phase-I of our framework is able to consolidate the search space of malicious nodes, reducing almost 90% of Phase-II’s computational workload. Phase-II localizes the malicious router nodes across various experimental scenarios with zero false positives. We also demonstrate the robustness of our framework for detecting and localizing malicious router nodes for different intermittent HTs with varying burst attacks over time.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"586-599"},"PeriodicalIF":5.2,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143184448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient Asymmetric Outphasing Power Amplifier With Extended Back-Off Range for 5G Applications","authors":"Bai Hua Zeng;Wing Shing Chan;Shao Yong Zheng;Xin Yu Zhou;Shichang Chen","doi":"10.1109/TCSI.2024.3483933","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3483933","url":null,"abstract":"5G and future 6G wireless communication systems are pushing the practical limits on the modulation schemes that can be achieved in practice. These higher-level modulation schemes have further exacerbated the challenges in power amplifier (PA) design. One solution to linearly and efficiently amplify these modulation schemes that have high peak-to-average power ratios (PAPRs), is to use dual-input Outphasing PAs (OPAs). However, the output back-off (OBO) range of a conventional OPA is limited. To mitigate this issue, a new OPA based on an asymmetric architecture is proposed. This new asymmetric OPA is shown theoretically that the OBO range can be extended. To validate the proposal, an OPA is designed using two asymmetric sub-PAs and a modified Chireix combiner. The implemented OPA achieves drain efficiencies of 60.6% and 60% at saturation (44.1dBm) and at 8-dB OBO under CW excitation at 2.58 GHz, respectively. Measurement of the OPA using 20-MHz 5G NR signal with 8-dB PAPR yields an average drain efficiency of 58.3% with an adjacent channel power ratio (ACPR) below −45.1 dBc with digital pre-distortion (DPD).","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"143-154"},"PeriodicalIF":5.2,"publicationDate":"2024-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}