Pub Date : 2025-08-25DOI: 10.1109/TCSI.2025.3594347
Muhammad Rizwan Khan;Xun Liu;Xin Zhang;Cheng Huang
This paper proposes convergence enhancement to state-space averaging (SSA) methodology for steady-state and small-signal analysis of high-ratio hybrid DC-DC converters, first using analysis of Double-Step-Down (DSD) topology, including parasitics, as an example, then extending to other hybrid topologies with different numbers of capacitors and inductors. The enhanced SSA method can be used to: 1) derive small-signal control-to-output transfer functions, which is essential to optimize the compensator for fast and stable closed-loop operation; 2) calculate steady-state inductor currents, output voltage, input current and the voltage(s) across the flying capacitor(s), $V_{CFs}$ , which is important to determine steady-state characteristics and performance; 3) include circuit non-idealities such as parasitics and timing mismatches; and 4) evaluate $V_{CF}$ balancing property by the proposed matrix invertibility principle and added constants, and determine whether dedicated $V_{CF}$ balancing circuits can be eliminated, which is considered an important benefit with reduced complexity and improved reliability. The theoretical results of DSD are then plotted in MATLAB and verified in simulations using PSIM and Cadence periodic transfer function (PXF) analysis, and measurement results using GaN devices. The simulation and measurement results match well with theoretical analysis. The enhancement is then extended beyond the DSD topology to analyze emerging hybrid topologies with more switched inductors and capacitors, future-proofing its capability to be applicable to new hybrid topologies.
{"title":"Steady-State and Small-Signal Analysis of High-Ratio Hybrid Buck Converters With Enhancement to State-Space-Averaging Methodology","authors":"Muhammad Rizwan Khan;Xun Liu;Xin Zhang;Cheng Huang","doi":"10.1109/TCSI.2025.3594347","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3594347","url":null,"abstract":"This paper proposes convergence enhancement to state-space averaging (SSA) methodology for steady-state and small-signal analysis of high-ratio hybrid DC-DC converters, first using analysis of Double-Step-Down (DSD) topology, including parasitics, as an example, then extending to other hybrid topologies with different numbers of capacitors and inductors. The enhanced SSA method can be used to: <italic>1)</i> derive small-signal control-to-output transfer functions, which is essential to optimize the compensator for fast and stable closed-loop operation; <italic>2)</i> calculate steady-state inductor currents, output voltage, input current and the voltage(s) across the flying capacitor(s), <inline-formula> <tex-math>$V_{CFs}$ </tex-math></inline-formula>, which is important to determine steady-state characteristics and performance; <italic>3)</i> include circuit non-idealities such as parasitics and timing mismatches; and <italic>4)</i> evaluate <inline-formula> <tex-math>$V_{CF}$ </tex-math></inline-formula> balancing property by the proposed matrix invertibility principle and added constants, and determine whether dedicated <inline-formula> <tex-math>$V_{CF}$ </tex-math></inline-formula> balancing circuits can be eliminated, which is considered an important benefit with reduced complexity and improved reliability. The theoretical results of DSD are then plotted in MATLAB and verified in simulations using PSIM and Cadence periodic transfer function (PXF) analysis, and measurement results using GaN devices. The simulation and measurement results match well with theoretical analysis. The enhancement is then extended beyond the DSD topology to analyze emerging hybrid topologies with more switched inductors and capacitors, future-proofing its capability to be applicable to new hybrid topologies.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 2","pages":"1486-1499"},"PeriodicalIF":5.2,"publicationDate":"2025-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146071179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-18DOI: 10.1109/TCSI.2025.3596129
Kamini Singh;Karun Rawat
This work presents a new design space of Extended continuous class-F (ECCF) power amplifiers with resistive second harmonic impedance after including the effect of non-linear drain-to-source capacitance $C_{mathbf {ds}}~_{mathbf {}}$ of a transistor. The expression of current waveforms is modified to include the impact of nonlinear drain to source capacitance in this mode. The analysis shows that this non-linear capacitance generates harmonic current, which alters the load trajectory on the Smith chart by achieving active and modified passive second harmonic loads. These active harmonic loads at the current reference plane of the transistor represent an active harmonic injection that increases the drain efficiency. Consequently, a design methodology is proposed to obtain passive loads for matching that ensures this active harmonic injection at the current reference plane of the transistor provides an efficiency improvement in the ECCF mode while maintaining the operation more than the octave frequency range. The proposed theory is validated by designing a power amplifier operating from 0.8-3.0 GHz (115.7% fractional bandwidth) with a measured drain efficiency of 57.24-70.3%, and an output power of 41.7-44.63 dBm. The power amplifier is also tested with modulated signals and linearized using digital predistortion to qualify spectral mask with a measured (Error Vector Magnitude) EVM of 1.54%.
{"title":"Non-Linearity Analysis of Drain-Source Capacitance in Extended Continuous Class-F Power Amplifier","authors":"Kamini Singh;Karun Rawat","doi":"10.1109/TCSI.2025.3596129","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3596129","url":null,"abstract":"This work presents a new design space of Extended continuous class-F (ECCF) power amplifiers with resistive second harmonic impedance after including the effect of non-linear drain-to-source capacitance <inline-formula> <tex-math>$C_{mathbf {ds}}~_{mathbf {}}$ </tex-math></inline-formula> of a transistor. The expression of current waveforms is modified to include the impact of nonlinear drain to source capacitance in this mode. The analysis shows that this non-linear capacitance generates harmonic current, which alters the load trajectory on the Smith chart by achieving active and modified passive second harmonic loads. These active harmonic loads at the current reference plane of the transistor represent an active harmonic injection that increases the drain efficiency. Consequently, a design methodology is proposed to obtain passive loads for matching that ensures this active harmonic injection at the current reference plane of the transistor provides an efficiency improvement in the ECCF mode while maintaining the operation more than the octave frequency range. The proposed theory is validated by designing a power amplifier operating from 0.8-3.0 GHz (115.7% fractional bandwidth) with a measured drain efficiency of 57.24-70.3%, and an output power of 41.7-44.63 dBm. The power amplifier is also tested with modulated signals and linearized using digital predistortion to qualify spectral mask with a measured (Error Vector Magnitude) EVM of 1.54%.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 1","pages":"735-747"},"PeriodicalIF":5.2,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-18DOI: 10.1109/TCSI.2025.3597288
Jiawang Yue;Zhitao Liu;Hongye Su
This paper aims to develop a constant output voltage controller for dynamic wireless power transfer systems(DWPTSs) incorporating sensor noise filtering and fault tolerance. DWPTSs are designed to alleviate range anxiety in electric vehicles(EVs); however, the output voltage fluctuations are their significant drawback compared to static charging mode. Additionally, DWPTSs also face sensor measurement noise and potential faults that exacerbate system instability. To mitigate above challenges, a data-driven fault-tolerant control framework is designed for DWPTS based on a self-learning predictor, which implements constant voltage regulation with enhanced noise and fault immunity. Specifically, a self-learning predictor is integrated into the feedforward loop of a high-gain extended state observer (ESO) to filter sensor noise. Then, a data memory stack is constructed to store predicted states and estimated disturbances, and a concurrent learning algorithm is introduced to recover control gains online. Finally, a composite anti-disturbance control law is implemented to generate the required control signals for the charging circuit. A notable advantage of this scheme is its ability to simultaneously address both sensor noise and faults, ensuring a constant output voltage during EV driving. Experimental results validate that the designed control framework effectively eliminates output voltage fluctuations and measurement noise, even in the presence of sensor faults.
{"title":"Data-Driven Fault-Tolerant Control Framework for EV Dynamic Wireless Power Transfer System Based on Self-Learning Predictor","authors":"Jiawang Yue;Zhitao Liu;Hongye Su","doi":"10.1109/TCSI.2025.3597288","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3597288","url":null,"abstract":"This paper aims to develop a constant output voltage controller for dynamic wireless power transfer systems(DWPTSs) incorporating sensor noise filtering and fault tolerance. DWPTSs are designed to alleviate range anxiety in electric vehicles(EVs); however, the output voltage fluctuations are their significant drawback compared to static charging mode. Additionally, DWPTSs also face sensor measurement noise and potential faults that exacerbate system instability. To mitigate above challenges, a data-driven fault-tolerant control framework is designed for DWPTS based on a self-learning predictor, which implements constant voltage regulation with enhanced noise and fault immunity. Specifically, a self-learning predictor is integrated into the feedforward loop of a high-gain extended state observer (ESO) to filter sensor noise. Then, a data memory stack is constructed to store predicted states and estimated disturbances, and a concurrent learning algorithm is introduced to recover control gains online. Finally, a composite anti-disturbance control law is implemented to generate the required control signals for the charging circuit. A notable advantage of this scheme is its ability to simultaneously address both sensor noise and faults, ensuring a constant output voltage during EV driving. Experimental results validate that the designed control framework effectively eliminates output voltage fluctuations and measurement noise, even in the presence of sensor faults.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 2","pages":"1448-1459"},"PeriodicalIF":5.2,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146071159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-14DOI: 10.1109/TCSI.2025.3586143
Sicong Jin;Xin Zhang;Dehong Xu
The cascaded solid-state transformer (SST) has garnered significant attention in recent years due to its modular advantages, offering improved scalability, efficiency, and fault-tolerant capabilities. However, the modeling of N-module cascaded SSTs and their impedance characteristics remains insufficiently explored, which could hinder the reliable integration of SSTs. To address this issue, this paper proposes a matrix-based modeling method to characterize the N-module SST and establish its corresponding impedance model. A universal module equivalent block diagram, accounting for arbitrary-order harmonic disturbances, is constructed through an initial matrix aggregation. Building upon this, a second matrix aggregation is performed to develop a system-wide equivalent block diagram, which accommodates any combination of modules, thus enabling standardized representation and modular expansion of the N-module SST. Based on the system equivalent block diagram, a transfer-matrix-based method is used to flexibly compute the SST impedance expression. Using the derived impedance model, the impact of factors such as module differences, operating conditions, and hardware parameters on port impedance is discussed. The influence of these factors on overall system stability is also discussed. Finally, the accuracy and validity of the impedance model, along with the related stability analysis, are verified through a hardware-in-the-loop (HIL) experimental setup.
{"title":"A Flexible Impedance Modeling Method and Stability Analysis Toward the Cascaded Solid-State Transformer","authors":"Sicong Jin;Xin Zhang;Dehong Xu","doi":"10.1109/TCSI.2025.3586143","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3586143","url":null,"abstract":"The cascaded solid-state transformer (SST) has garnered significant attention in recent years due to its modular advantages, offering improved scalability, efficiency, and fault-tolerant capabilities. However, the modeling of N-module cascaded SSTs and their impedance characteristics remains insufficiently explored, which could hinder the reliable integration of SSTs. To address this issue, this paper proposes a matrix-based modeling method to characterize the N-module SST and establish its corresponding impedance model. A universal module equivalent block diagram, accounting for arbitrary-order harmonic disturbances, is constructed through an initial matrix aggregation. Building upon this, a second matrix aggregation is performed to develop a system-wide equivalent block diagram, which accommodates any combination of modules, thus enabling standardized representation and modular expansion of the N-module SST. Based on the system equivalent block diagram, a transfer-matrix-based method is used to flexibly compute the SST impedance expression. Using the derived impedance model, the impact of factors such as module differences, operating conditions, and hardware parameters on port impedance is discussed. The influence of these factors on overall system stability is also discussed. Finally, the accuracy and validity of the impedance model, along with the related stability analysis, are verified through a hardware-in-the-loop (HIL) experimental setup.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 2","pages":"1420-1433"},"PeriodicalIF":5.2,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146071148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates the impact of bifurcations on the performance of power electronic circuits. We focus on circuits that include energy-harvesting devices, which exhibit a maximum power point (MPP). In particular, a DC–DC converter with a photovoltaic (PV) module is considered a representative example of such systems to evaluate the relationship between the circuit performance indices (such as power conversion and maximum power point tracking (MPPT) efficiency) and the bifurcation phenomena observed in the system. First, experimental results are reported that evaluate circuit characteristics and performance under MPPT control. Then, a novel mathematical PV model is presented and fully defined using experimentally measured parameters; this model does not necessitate the use of root-finding algorithms. Next, this model is integrated with the switched nonlinear model of a DC–DC converter subject to peak current mode control (PCMC), and a stability analysis of the periodic orbits is performed. Finally, the relationship between circuit performance and observed bifurcation phenomena is investigated and discussed. This research demonstrates the occurrence of both period-doubling and Neimark–Sacker bifurcations in the system considered here, and these features are shown in a two-parameter bifurcation diagram.
{"title":"Impact of Bifurcations on the Performance of Power Electronic Circuits","authors":"Hiroyuki Asahara;Kuntal Mandal;Hiroki Akiba;Nobuyuki Kasa;Takuji Kousaka","doi":"10.1109/TCSI.2025.3595507","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3595507","url":null,"abstract":"This paper investigates the impact of bifurcations on the performance of power electronic circuits. We focus on circuits that include energy-harvesting devices, which exhibit a maximum power point (MPP). In particular, a DC–DC converter with a photovoltaic (PV) module is considered a representative example of such systems to evaluate the relationship between the circuit performance indices (such as power conversion and maximum power point tracking (MPPT) efficiency) and the bifurcation phenomena observed in the system. First, experimental results are reported that evaluate circuit characteristics and performance under MPPT control. Then, a novel mathematical PV model is presented and fully defined using experimentally measured parameters; this model does not necessitate the use of root-finding algorithms. Next, this model is integrated with the switched nonlinear model of a DC–DC converter subject to peak current mode control (PCMC), and a stability analysis of the periodic orbits is performed. Finally, the relationship between circuit performance and observed bifurcation phenomena is investigated and discussed. This research demonstrates the occurrence of both period-doubling and Neimark–Sacker bifurcations in the system considered here, and these features are shown in a two-parameter bifurcation diagram.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 2","pages":"1500-1511"},"PeriodicalIF":5.2,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146071177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes the first simultaneous wireless power and data transfer (SWPDT) integrated circuit (IC) which exploits a Capacitive-Inductive Channel (CI-Channel), enabling concurrent power and data transmission. The communication across the CI-Channel can support data-only transmission or can be incorporated into the system control loop, allowing output voltage regulation through phase-shift control applied at the primary side. The proposed IC can be configured as primary side (power transmitter, P-TX, and data receiver, RX) or secondary side (power receiver, P-RX, and data transmitter, TX). In order to ensure communication robustness, unwanted disturbances are removed through specifically designed Power Blanking and Ringing Blanking circuits. The proposed SWPDT IC test-chip prototype was fabricated using a 130-nm BCD process and experimentally verified considering the complete wireless power transfer (WPT) system, including primary side, CI-Channel and secondary side. The overall system, targeting medium-power industrial applications, achieves a maximum 5.3-W output power, a peak efficiency of 83.7% and a load regulation of 0.09 mV/mA. Moreover, a 540 kb/s data rate with no transmission errors across $10^{9}$ bit acquisitions, corresponding to a bit-error-rate (BER) $lt 10^{-9}$ , was achieved.
{"title":"A 5.3-W 83.7% Peak Efficiency Simultaneous Wireless Power and Data Transfer IC Enabling 10–9 BER 540-kb/s Data Rate or Output Voltage Regulation","authors":"Alessandro Liotta;Elisabetta Moisello;Giovanni Frattini;Pietro Giannelli;Piero Malcovati;Edoardo Bonizzoni","doi":"10.1109/TCSI.2025.3595804","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3595804","url":null,"abstract":"This paper proposes the first simultaneous wireless power and data transfer (SWPDT) integrated circuit (IC) which exploits a Capacitive-Inductive Channel (CI-Channel), enabling concurrent power and data transmission. The communication across the CI-Channel can support data-only transmission or can be incorporated into the system control loop, allowing output voltage regulation through phase-shift control applied at the primary side. The proposed IC can be configured as primary side (power transmitter, P-TX, and data receiver, RX) or secondary side (power receiver, P-RX, and data transmitter, TX). In order to ensure communication robustness, unwanted disturbances are removed through specifically designed Power Blanking and Ringing Blanking circuits. The proposed SWPDT IC test-chip prototype was fabricated using a 130-nm BCD process and experimentally verified considering the complete wireless power transfer (WPT) system, including primary side, CI-Channel and secondary side. The overall system, targeting medium-power industrial applications, achieves a maximum 5.3-W output power, a peak efficiency of 83.7% and a load regulation of 0.09 mV/mA. Moreover, a 540 kb/s data rate with no transmission errors across <inline-formula> <tex-math>$10^{9}$ </tex-math></inline-formula> bit acquisitions, corresponding to a bit-error-rate (BER) <inline-formula> <tex-math>$lt 10^{-9}$ </tex-math></inline-formula>, was achieved.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 2","pages":"1406-1419"},"PeriodicalIF":5.2,"publicationDate":"2025-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146071155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-08DOI: 10.1109/TCSI.2025.3593415
Zheng Liu;Hanlin Dong;Qianbao Mi;Zhiqiang Ma;Zhaoke Ning;Xudong Wang
This paper primarily introduces a novel prescribed performance control method to achieve rapid and high-precision control in servo systems. Initially, an interesting asymmetric barrier function is proposed, so that the controlled plant with arbitrary initial values can be confined within an asymmetric boundary. To reduce the dependence of controller deployment on physical parameters, an ultralocal model (ULM) approach is adopted and the logarithmic sliding-mode manifold is synthesized to design the controller and observer, resulting in an order-reduced and transient-performance-improved error dynamics. Since there are no non-Lipschitz continuous elements in the logarithmic sliding-mode, the super-twisting algorithm can be used to weaken signal chattering while converging the equivalent error rapidly. The Lyapunov-based direct analysis proves the stability of the controlled servo system with unknown parameters. The superiority of the scheme is verified through a series of simulations and experiments on PMSM platform.
{"title":"Ultralocal Model-Free Logarithmic Sliding-Mode Control for PMSM Angle Robust Tracking With Asymmetric Constraints","authors":"Zheng Liu;Hanlin Dong;Qianbao Mi;Zhiqiang Ma;Zhaoke Ning;Xudong Wang","doi":"10.1109/TCSI.2025.3593415","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3593415","url":null,"abstract":"This paper primarily introduces a novel prescribed performance control method to achieve rapid and high-precision control in servo systems. Initially, an interesting asymmetric barrier function is proposed, so that the controlled plant with arbitrary initial values can be confined within an asymmetric boundary. To reduce the dependence of controller deployment on physical parameters, an ultralocal model (ULM) approach is adopted and the logarithmic sliding-mode manifold is synthesized to design the controller and observer, resulting in an order-reduced and transient-performance-improved error dynamics. Since there are no non-Lipschitz continuous elements in the logarithmic sliding-mode, the super-twisting algorithm can be used to weaken signal chattering while converging the equivalent error rapidly. The Lyapunov-based direct analysis proves the stability of the controlled servo system with unknown parameters. The superiority of the scheme is verified through a series of simulations and experiments on PMSM platform.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 1","pages":"644-656"},"PeriodicalIF":5.2,"publicationDate":"2025-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes the load-independent class-E Zero-Voltage Switching (ZVS) power oscillator. Conventional class-E power oscillator has a load-dependent phase shift, which hinders sustained oscillation under varying load conditions. Hence, we introduce the class-E power amplifier that ensures the load-independent phase shift in the output current. By incorporating it into an LCLC filter with a resonant-capacitor feedback network, the load-independent self-oscillation is realized. The proposed power oscillator satisfies a phase-shift requirement for sustained oscillation regardless of the load resistance. Furthermore, the proposed circuit exhibits load independence in ZVS, output current, and gate-drive voltage. This paper provides a thorough analysis of the proposed power oscillator, covering its operating principle, power loss prediction, design, and limitations. This paper also gives two design examples with 0.8 MHz and 6.78 MHz oscillation frequencies. In the experiment, the prototype power oscillators achieved 93.8 % and 87.4 % power-conversion efficiencies, respectively. The validity and effectiveness of the proposed power oscillator are demonstrated from the experimental verifications.
{"title":"Analysis and Design of Load-Independent Class-E Zero-Voltage Switching Power Oscillator","authors":"Yutaro Komiyama;Wenqi Zhu;Akihiro Konishi;Kien Nguyen;Hiroo Sekiya","doi":"10.1109/TCSI.2025.3594362","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3594362","url":null,"abstract":"This paper proposes the load-independent class-E Zero-Voltage Switching (ZVS) power oscillator. Conventional class-E power oscillator has a load-dependent phase shift, which hinders sustained oscillation under varying load conditions. Hence, we introduce the class-E power amplifier that ensures the load-independent phase shift in the output current. By incorporating it into an LCLC filter with a resonant-capacitor feedback network, the load-independent self-oscillation is realized. The proposed power oscillator satisfies a phase-shift requirement for sustained oscillation regardless of the load resistance. Furthermore, the proposed circuit exhibits load independence in ZVS, output current, and gate-drive voltage. This paper provides a thorough analysis of the proposed power oscillator, covering its operating principle, power loss prediction, design, and limitations. This paper also gives two design examples with 0.8 MHz and 6.78 MHz oscillation frequencies. In the experiment, the prototype power oscillators achieved 93.8 % and 87.4 % power-conversion efficiencies, respectively. The validity and effectiveness of the proposed power oscillator are demonstrated from the experimental verifications.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 1","pages":"721-734"},"PeriodicalIF":5.2,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-07DOI: 10.1109/TCSI.2025.3594266
Xin Tong;Zhangyong Chen;Yong Chen;Lehan Xu
In switching converters, capacitor current is a critical feedback parameter due to its ability to rapidly reflect dynamic load variations, making it widely applicable in various control strategies such as current-mode feedback regulation. With the rapid advancement of digital power technology, current detection must be implemented in the digital domain, typically requiring high-bandwidth current sensors and high-speed analog-to-digital converters (ADCs). To address the high-cost challenge associated with capacitor current sampling in digital buck converters, this paper proposes a low-cost digital capacitor current estimation technique based on output voltage information tracking. By analyzing the dynamic characteristics of the output voltage, the method achieves precise estimation of the capacitor current. This paper thoroughly investigates the error issues arising from time constant mismatch in the proposed capacitor current estimation method and introduces an online time constant identification approach based on the output capacitor ($mathbf {C}_{mathbf {o}}$ ) and its equivalent series resistance (ESR). By dynamically adjusting the estimator parameters, the estimation accuracy is significantly improved. The proposed algorithm is experimentally validated on a buck converter prototype. The results demonstrate that the error in the time constant after identification and correction is controlled within 3%, and the capacitor current estimation accuracy is maintained within 6%.
{"title":"A Low-Cost Digital Capacitor Current Estimation Algorithm Based on Parameter Identification for Buck Converter Application","authors":"Xin Tong;Zhangyong Chen;Yong Chen;Lehan Xu","doi":"10.1109/TCSI.2025.3594266","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3594266","url":null,"abstract":"In switching converters, capacitor current is a critical feedback parameter due to its ability to rapidly reflect dynamic load variations, making it widely applicable in various control strategies such as current-mode feedback regulation. With the rapid advancement of digital power technology, current detection must be implemented in the digital domain, typically requiring high-bandwidth current sensors and high-speed analog-to-digital converters (ADCs). To address the high-cost challenge associated with capacitor current sampling in digital buck converters, this paper proposes a low-cost digital capacitor current estimation technique based on output voltage information tracking. By analyzing the dynamic characteristics of the output voltage, the method achieves precise estimation of the capacitor current. This paper thoroughly investigates the error issues arising from time constant mismatch in the proposed capacitor current estimation method and introduces an online time constant identification approach based on the output capacitor (<inline-formula> <tex-math>$mathbf {C}_{mathbf {o}}$ </tex-math></inline-formula>) and its equivalent series resistance (ESR). By dynamically adjusting the estimator parameters, the estimation accuracy is significantly improved. The proposed algorithm is experimentally validated on a buck converter prototype. The results demonstrate that the error in the time constant after identification and correction is controlled within 3%, and the capacitor current estimation accuracy is maintained within 6%.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"73 2","pages":"1512-1524"},"PeriodicalIF":5.2,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146071165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A major challenge of long-term clock stability is frequency drift due to temperature variations. This paper describes the design of a proportional, integral, derivative (PID) control system for external ovenization of an AlScN-on-Si Shear-BAW Resonator (S3R), which has a fixed turnover temperature where the $1{^{text {st}}}$ order temperature coefficient of frequency is $approx 0$ ppm/°C. The control system provides $pm ~0.125^{circ }$ C temperature stability and assists in achieving better than $pm ~25$ ppb frequency stability over a temperature range of 15-40°C by maintaining resonator operation near the turnover temperature, where the $2{^{text {nd}}}$ order temperature coefficient of frequency drift is -62.71ppb/°C2. The robust and adaptive PID algorithm (programmed on an external microcontroller unit connected to the interposer) ensures continuous ovenization by configuring the duty cycle of a compact heat actuator (powerMOS) that is placed in <3.5mm> $times 2$ mm resonator and a complementary to absolute temperature sensor (implemented as a 1mm$times 1$ mm, 65nm integrated circuit), that are all held on a thermally conductive 7mm$times$ 7mm Si interposer.
{"title":"Achieving < ±25 ppb Frequency Stability With a ±0.125 °C Oven Control on a Si Interposer for an AlScN-on-Si Shear-BAW Resonator","authors":"Everestus Ezike;Ratul Kundu;Shaurya Dabas;Banafsheh Jabbari;Shruti Mishra;Dicheng Mo;Honggyu Kim;Zetian Mi;Roozbeh Tabrizian;Baibhab Chatterjee","doi":"10.1109/TCSI.2025.3590669","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3590669","url":null,"abstract":"A major challenge of long-term clock stability is frequency drift due to temperature variations. This paper describes the design of a proportional, integral, derivative (PID) control system for external ovenization of an AlScN-on-Si Shear-BAW Resonator (S<sup>3</sup>R), which has a fixed turnover temperature where the <inline-formula> <tex-math>$1{^{text {st}}}$ </tex-math></inline-formula> order temperature coefficient of frequency is <inline-formula> <tex-math>$approx 0$ </tex-math></inline-formula> ppm/°C. The control system provides <inline-formula> <tex-math>$pm ~0.125^{circ }$ </tex-math></inline-formula>C temperature stability and assists in achieving better than <inline-formula> <tex-math>$pm ~25$ </tex-math></inline-formula>ppb frequency stability over a temperature range of 15-40°C by maintaining resonator operation near the turnover temperature, where the <inline-formula> <tex-math>$2{^{text {nd}}}$ </tex-math></inline-formula> order temperature coefficient of frequency drift is -62.71ppb/°C<sup>2</sup>. The robust and adaptive PID algorithm (programmed on an external microcontroller unit connected to the interposer) ensures continuous ovenization by configuring the duty cycle of a compact heat actuator (powerMOS) that is placed in <3.5mm> <tex-math>$times 2$ </tex-math></inline-formula>mm resonator and a complementary to absolute temperature sensor (implemented as a 1mm<inline-formula> <tex-math>$times 1$ </tex-math></inline-formula>mm, 65nm integrated circuit), that are all held on a thermally conductive 7mm<inline-formula> <tex-math>$times$ </tex-math></inline-formula>7mm Si interposer.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 9","pages":"4455-4468"},"PeriodicalIF":5.2,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144918190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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