Pub Date : 2025-09-09DOI: 10.1109/TED.2025.3606424
Sang-Won Lee;Seong-Yun Yun;Yang-Kyu Choi
The p-n-p bi-stable resistor (biristor), complementary to an n-p-n biristor, is demonstrated on a bulk substrate in the form of a silicon nanowire (SiNW). It consists of a ${p}^{+}$ -emitter, ${n}^{{0}}$ -base, and ${p}^{+}$ -collector, with each electrode having inverted polarity compared to an n-p-n biristor. This p-n-p biristor also exhibits the characteristics of a single-transistor latch (STL), similar to its counterpart, the n-p-n biristor. The p-n-p biristor can also be applied to a steep slope device, a ternary device, an artificial neuron, a relaxation oscillator, and a true random number generator, akin to n-p-n biristor applications.
{"title":"p-n-p Biristor With a Silicon Nanowire","authors":"Sang-Won Lee;Seong-Yun Yun;Yang-Kyu Choi","doi":"10.1109/TED.2025.3606424","DOIUrl":"https://doi.org/10.1109/TED.2025.3606424","url":null,"abstract":"The p-n-p bi-stable resistor (biristor), complementary to an n-p-n biristor, is demonstrated on a bulk substrate in the form of a silicon nanowire (SiNW). It consists of a <inline-formula> <tex-math>${p}^{+}$ </tex-math></inline-formula>-emitter, <inline-formula> <tex-math>${n}^{{0}}$ </tex-math></inline-formula>-base, and <inline-formula> <tex-math>${p}^{+}$ </tex-math></inline-formula>-collector, with each electrode having inverted polarity compared to an n-p-n biristor. This p-n-p biristor also exhibits the characteristics of a single-transistor latch (STL), similar to its counterpart, the n-p-n biristor. The p-n-p biristor can also be applied to a steep slope device, a ternary device, an artificial neuron, a relaxation oscillator, and a true random number generator, akin to n-p-n biristor applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6375-6378"},"PeriodicalIF":3.2,"publicationDate":"2025-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gallium-doped hafnium oxide (HGO) exhibits excellent ferroelectricity with remarkable reliability and improved endurance characteristics. However, the requisite high-temperature annealing ($gt 600~^{circ }$ C) poses challenges for CMOS back-end-of-line (BEOL) integration. To achieve ferroelectric (FE) HGO at low temperatures (below $400~^{circ }$ C), we carried out an in-depth analysis on the role of N2 flow during rapid thermal annealing (RTA) on ferroelectricity at $400~^{circ }$ C. Low-N2-flow-rate annealing under reduced pressure lowers the energy barrier for stabilizing the FE orthorhombic phase (o-phase) in HGO, though at the expense of cooling efficiency. Strategic flow parameter optimization enables FE for the HGO capacitor under BEOL-compatible annealing conditions. In addition, the FE behavior of HGO films with different Ga doping concentrations was investigated. The identified Ga doping window (4.17–9.09 atomic%) redefines the phase stability criteria for 10 nm HGO FEs. The remnant polarization $(2{P}_{r})$ of $24.8~mu $ C/cm2 was achieved for HGO samples with 6.14 atomic% Ga processed at $400~^{circ }$ C. Furthermore, due to the decrease in process temperature, the devices exhibit robust performance, including low leakage current and high endurance ($gt 10^{{9}}$ ). This work establishes a BEOL-compatible hafnium-based FE material system through low-temperature process engineering.
{"title":"A Back-End-of-Line-Compatible Ferroelectric Ga-Doped HfO₂ Capacitor With Low Thermal Budget (400°C)","authors":"Peng Yuan;Xufang Zhang;Peng Peng;Xinzhong Zhu;Heng Ye;Xiaomin Lai;Yuan Qiu;Pengfei Jiang;Qing Luo;Jing Zhang","doi":"10.1109/TED.2025.3604777","DOIUrl":"https://doi.org/10.1109/TED.2025.3604777","url":null,"abstract":"Gallium-doped hafnium oxide (HGO) exhibits excellent ferroelectricity with remarkable reliability and improved endurance characteristics. However, the requisite high-temperature annealing (<inline-formula> <tex-math>$gt 600~^{circ }$ </tex-math></inline-formula>C) poses challenges for CMOS back-end-of-line (BEOL) integration. To achieve ferroelectric (FE) HGO at low temperatures (below <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C), we carried out an in-depth analysis on the role of N2 flow during rapid thermal annealing (RTA) on ferroelectricity at <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C. Low-N2-flow-rate annealing under reduced pressure lowers the energy barrier for stabilizing the FE orthorhombic phase (o-phase) in HGO, though at the expense of cooling efficiency. Strategic flow parameter optimization enables FE for the HGO capacitor under BEOL-compatible annealing conditions. In addition, the FE behavior of HGO films with different Ga doping concentrations was investigated. The identified Ga doping window (4.17–9.09 atomic%) redefines the phase stability criteria for 10 nm HGO FEs. The remnant polarization <inline-formula> <tex-math>$(2{P}_{r})$ </tex-math></inline-formula> of <inline-formula> <tex-math>$24.8~mu $ </tex-math></inline-formula>C/cm2 was achieved for HGO samples with 6.14 atomic% Ga processed at <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C. Furthermore, due to the decrease in process temperature, the devices exhibit robust performance, including low leakage current and high endurance (<inline-formula> <tex-math>$gt 10^{{9}}$ </tex-math></inline-formula>). This work establishes a BEOL-compatible hafnium-based FE material system through low-temperature process engineering.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6387-6390"},"PeriodicalIF":3.2,"publicationDate":"2025-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we have experimentally studied the response of electrolyte-gated graphene field-effect transistors (EG-gFETs) under various stress and relaxation conditions at different voltage bias values and temperatures. We fit all the experimental data with an analytical model based on charge trapping at the silicon oxide substrate defects in contact with the graphene channel. In the model, the electron transitions require overcoming an energetic barrier leading to the new state and, consequently, the process is temperature- and gate-bias-dependent. The fit parameters to the experimental data are then used for the first time to construct the capture–emission time maps (CET maps) of the EG-gFET devices, or the capture/emission time distribution of the oxide defects and their contribution to the device’s drift and noise at each timescale. Studying these maps as a function of the bias and temperature allows us to gain insight into the best experimental conditions to minimize electrical noise during measurements, to propose improved protocols when using EG-gFETs in applications and to guide circuit designers on deciding the best operating conditions.
{"title":"Temperature- and Bias-Dependent Capture–Emission Time Maps in Electrolyte-Gated Graphene Field-Effect Transistors","authors":"Adriana Oliveira;Henrique Nóbrega;Telma Domingues;Jérôme Borme;Pedro Alpuim;João Mouro","doi":"10.1109/TED.2025.3603796","DOIUrl":"https://doi.org/10.1109/TED.2025.3603796","url":null,"abstract":"In this work, we have experimentally studied the response of electrolyte-gated graphene field-effect transistors (EG-gFETs) under various stress and relaxation conditions at different voltage bias values and temperatures. We fit all the experimental data with an analytical model based on charge trapping at the silicon oxide substrate defects in contact with the graphene channel. In the model, the electron transitions require overcoming an energetic barrier leading to the new state and, consequently, the process is temperature- and gate-bias-dependent. The fit parameters to the experimental data are then used for the first time to construct the capture–emission time maps (CET maps) of the EG-gFET devices, or the capture/emission time distribution of the oxide defects and their contribution to the device’s drift and noise at each timescale. Studying these maps as a function of the bias and temperature allows us to gain insight into the best experimental conditions to minimize electrical noise during measurements, to propose improved protocols when using EG-gFETs in applications and to guide circuit designers on deciding the best operating conditions.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6321-6328"},"PeriodicalIF":3.2,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TED.2025.3598553
{"title":"IEEE Transactions on Electron Devices Publication Information","authors":"","doi":"10.1109/TED.2025.3598553","DOIUrl":"https://doi.org/10.1109/TED.2025.3598553","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"C2-C2"},"PeriodicalIF":3.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142505","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TED.2025.3598557
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Reliability of Advanced Nodes","authors":"","doi":"10.1109/TED.2025.3598557","DOIUrl":"https://doi.org/10.1109/TED.2025.3598557","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5261-5262"},"PeriodicalIF":3.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142481","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TED.2025.3598555
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices on Wide Band Gap Semiconductors for Automotive Applications","authors":"","doi":"10.1109/TED.2025.3598555","DOIUrl":"https://doi.org/10.1109/TED.2025.3598555","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5259-5260"},"PeriodicalIF":3.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142480","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TED.2025.3598559
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/TED.2025.3598559","DOIUrl":"https://doi.org/10.1109/TED.2025.3598559","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5263-5264"},"PeriodicalIF":3.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142479","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TED.2025.3598561
{"title":"IEEE Transactions on Electron Devices Information for Authors","authors":"","doi":"10.1109/TED.2025.3598561","DOIUrl":"https://doi.org/10.1109/TED.2025.3598561","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"C3-C3"},"PeriodicalIF":3.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142483","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TED.2025.3589340
Myung Jin;Hyungcheol Shin
We propose a novel physical model for the attempt-to-escape frequency of trap-to-band electron emission, which is broadly applicable to various trap-to-band scenarios. The model is verified under detrapping mechanisms in bandgap-engineered tunneling oxide (BETOX), enabling accurate prediction of electron emission dynamics within extremely short timeframes. Extensive comparisons between the proposed model and calibrated TCAD simulations demonstrate excellent agreement, validating its accuracy and reliability. Additionally, based on calibrated physical parameters, the model is adaptable to engineering variations such as trap profiles, including intricate combinations of Gaussian trap distributions, making it highly versatile for future device optimization and analysis.
{"title":"Modeling Attempt-to-Escape Frequency: Tunneling Emission of Trapped Electrons in Tunneling Oxides of 3-D NAND Flash Memory","authors":"Myung Jin;Hyungcheol Shin","doi":"10.1109/TED.2025.3589340","DOIUrl":"https://doi.org/10.1109/TED.2025.3589340","url":null,"abstract":"We propose a novel physical model for the attempt-to-escape frequency of trap-to-band electron emission, which is broadly applicable to various trap-to-band scenarios. The model is verified under detrapping mechanisms in bandgap-engineered tunneling oxide (BETOX), enabling accurate prediction of electron emission dynamics within extremely short timeframes. Extensive comparisons between the proposed model and calibrated TCAD simulations demonstrate excellent agreement, validating its accuracy and reliability. Additionally, based on calibrated physical parameters, the model is adaptable to engineering variations such as trap profiles, including intricate combinations of Gaussian trap distributions, making it highly versatile for future device optimization and analysis.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4884-4889"},"PeriodicalIF":3.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TED.2025.3582221
Pengyu Lai;Hui Wang;Kevin Chen;H. Alan Mantooth;Zhong Chen
This article proposes the generalized design guideline for micrometer silicon carbide (SiC) complementary metal-oxide-semiconductor (CMOS) devices for integrated circuit (IC) applications. The design window of 1-$mu $ m SiC CMOS devices, which considers device operation voltage, on-state current, short channel effect (SCE), and subthreshold swing (SS), is proposed to show the design margins of the gate oxide thickness and channel doping concentration. The performance of CMOS devices in 1-$mu $ m SiC CMOS processes is used to demonstrate the effectiveness of the proposed design window. SiC-based buffer chain circuits are tested to demonstrate circuit operating speed and power consumption. The devices and circuits are fully characterized from 25 ° C to 300 ° C. It has been demonstrated that further design improvements for SiC CMOS devices are needed before large-scale implementation due to their strong SCE, high SS, and lowon-state current. On the other hand, SiC ICs show less degradation with increasing temperatures compared to Si ICs, making them promising for high-temperature applications.
本文提出了用于集成电路（IC）应用的微米级碳化硅（SiC）互补金属氧化物半导体（CMOS）器件的通用设计准则。提出了考虑器件工作电压、导通电流、短沟道效应（SCE）和亚阈值摆幅（SS）的1- $mu $ m SiC CMOS器件的设计窗口，以显示栅极氧化物厚度和沟道掺杂浓度的设计裕度。用1- $mu $ m SiC CMOS工艺中CMOS器件的性能来证明所提出的设计窗口的有效性。测试了基于sic的缓冲链电路，以演示电路的运行速度和功耗。器件和电路在25°C至300°C范围内进行了充分表征。由于SiC CMOS器件具有强SCE，高SS和低状态电流，因此在大规模实施之前需要进一步改进设计。另一方面，与Si ic相比，SiC ic随着温度的升高而表现出更少的降解，这使得它们在高温应用中具有前景。
{"title":"Design Optimizations of Micrometer SiC CMOS Devices for High-Temperature IC Applications","authors":"Pengyu Lai;Hui Wang;Kevin Chen;H. Alan Mantooth;Zhong Chen","doi":"10.1109/TED.2025.3582221","DOIUrl":"https://doi.org/10.1109/TED.2025.3582221","url":null,"abstract":"This article proposes the generalized design guideline for micrometer silicon carbide (SiC) complementary metal-oxide-semiconductor (CMOS) devices for integrated circuit (IC) applications. The design window of 1-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> m SiC CMOS devices, which considers device operation voltage, <sc>on</small>-state current, short channel effect (SCE), and subthreshold swing (SS), is proposed to show the design margins of the gate oxide thickness and channel doping concentration. The performance of CMOS devices in 1-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> m SiC CMOS processes is used to demonstrate the effectiveness of the proposed design window. SiC-based buffer chain circuits are tested to demonstrate circuit operating speed and power consumption. The devices and circuits are fully characterized from 25 ° C to 300 ° C. It has been demonstrated that further design improvements for SiC CMOS devices are needed before large-scale implementation due to their strong SCE, high SS, and low<sc>on</small>-state current. On the other hand, SiC ICs show less degradation with increasing temperatures compared to Si ICs, making them promising for high-temperature applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4742-4751"},"PeriodicalIF":3.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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