Pub Date : 2025-02-04DOI: 10.1109/TED.2025.3532581
Zhouchao Gan;Chenyu Zhang;Fan Yang;Dongdong Zhang;Yinghao Ma;Menghua Huang;Xiangshui Miao;Xingsheng Wang
Logic-in-memory (LIM) computing is expected to break the von Neumann bottleneck by performing logical operations in memory. This article presents a novel 2–1 multiplexer (MUX) scheme based on memristors that requires only two steps and three memristors. The proposed MUX logic can be executed natively in a memristor array, facilitating the construction of complex logic and arithmetic functions. Employing the proposed 2–1 MUX logic combined with xor logic, the 1-bit full-adder (FA) function is efficiently implemented and experimentally verified. The area and delay overheads of both serial and parallel architectures of n-bit FAs are derived, and the FA function is experimentally verified through a 4-bit carry-select adder case. Compared with IMPLY logic, the proposed FA scheme shows a significant performance improvement without sacrificing power consumption. The experimental results demonstrate the efficiency of the proposed MUX logic in accelerating FA functions, paving the way for building efficient LIM systems.
内存逻辑（LIM）计算有望通过在内存中执行逻辑运算来打破冯-诺依曼瓶颈。本文介绍了一种基于忆阻器的新型 2-1 多路复用器（MUX）方案，该方案只需两个步骤和三个忆阻器。所提出的多路复用逻辑可在忆阻器阵列中本地执行，便于构建复杂的逻辑和算术功能。利用所提出的 2-1 MUX 逻辑与 xor 逻辑相结合，高效地实现了 1 位全梯形图（FA）功能，并通过实验进行了验证。推导出了 n 位 FA 的串行和并行架构的面积和延迟开销，并通过 4 位带选加法器实例对 FA 函数进行了实验验证。与 IMPLY 逻辑相比，所提出的 FA 方案在不牺牲功耗的情况下显著提高了性能。实验结果证明了所提出的 MUX 逻辑在加速 FA 功能方面的效率，为构建高效的 LIM 系统铺平了道路。
{"title":"Efficiently Implemented Logic Primitives of MUX and XOR Based on Memristors and Applications in Full-Adder Functions","authors":"Zhouchao Gan;Chenyu Zhang;Fan Yang;Dongdong Zhang;Yinghao Ma;Menghua Huang;Xiangshui Miao;Xingsheng Wang","doi":"10.1109/TED.2025.3532581","DOIUrl":"https://doi.org/10.1109/TED.2025.3532581","url":null,"abstract":"Logic-in-memory (LIM) computing is expected to break the von Neumann bottleneck by performing logical operations in memory. This article presents a novel 2–1 multiplexer (MUX) scheme based on memristors that requires only two steps and three memristors. The proposed MUX logic can be executed natively in a memristor array, facilitating the construction of complex logic and arithmetic functions. Employing the proposed 2–1 MUX logic combined with <sc>xor</small> logic, the 1-bit full-adder (FA) function is efficiently implemented and experimentally verified. The area and delay overheads of both serial and parallel architectures of n-bit FAs are derived, and the FA function is experimentally verified through a 4-bit carry-select adder case. Compared with IMPLY logic, the proposed FA scheme shows a significant performance improvement without sacrificing power consumption. The experimental results demonstrate the efficiency of the proposed MUX logic in accelerating FA functions, paving the way for building efficient LIM systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1118-1124"},"PeriodicalIF":2.9,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-31DOI: 10.1109/TED.2025.3533465
Xiaoxin Xie;Yuchen Wang;Zili Tang;Yijiao Wang;Xing Zhang;Fei Liu
The combination of machine-learning (ML) and electronic structure computation has proven effective in studying various properties of molecules and crystals at the atomistic level. However, challenges arise when these molecules or crystals are contacted with external electrodes, complicating the description of quantum transport properties using existing methods. In this study, we propose an attention-based heterogeneous graph neural network to characterize the global field and dynamic features of open systems. Our approach aims to accelerate or bypass the resource-intensive self-consistent iterations of solving Schrödinger and Poisson equations within nonequilibrium Green’s function (NEGF) formalism from the bottom-up, significantly improving the efficiency of quantum transport calculations. Representing the device with a heterogeneous graph largely retains its intrinsic physical characteristics, while the global graph attention network (GAT) effectively captures the propagation of nonlocal physical information, addressing prediction accuracy challenges due to device scaling. The global field heterogeneous graph neural network (GFGNN) demonstrates high accuracy, significant acceleration, and potential transferability at different channel lengths in simulations of p-n junctions (two-terminal with significant tunneling effect) and MOSFETs (three-terminal).
{"title":"A Bottom-Up Machine-Learning Approach for Efficient Device Simulation","authors":"Xiaoxin Xie;Yuchen Wang;Zili Tang;Yijiao Wang;Xing Zhang;Fei Liu","doi":"10.1109/TED.2025.3533465","DOIUrl":"https://doi.org/10.1109/TED.2025.3533465","url":null,"abstract":"The combination of machine-learning (ML) and electronic structure computation has proven effective in studying various properties of molecules and crystals at the atomistic level. However, challenges arise when these molecules or crystals are contacted with external electrodes, complicating the description of quantum transport properties using existing methods. In this study, we propose an attention-based heterogeneous graph neural network to characterize the global field and dynamic features of open systems. Our approach aims to accelerate or bypass the resource-intensive self-consistent iterations of solving Schrödinger and Poisson equations within nonequilibrium Green’s function (NEGF) formalism from the bottom-up, significantly improving the efficiency of quantum transport calculations. Representing the device with a heterogeneous graph largely retains its intrinsic physical characteristics, while the global graph attention network (GAT) effectively captures the propagation of nonlocal physical information, addressing prediction accuracy challenges due to device scaling. The global field heterogeneous graph neural network (GFGNN) demonstrates high accuracy, significant acceleration, and potential transferability at different channel lengths in simulations of p-n junctions (two-terminal with significant tunneling effect) and MOSFETs (three-terminal).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1282-1292"},"PeriodicalIF":2.9,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Flip FET (FFET), a novel self-aligned stacked transistor architecture with dual-sided transistor stacking, was recently proposed and demonstrated. However, due to the vertically stacking nature, the electrical coupling of frontside (FS) and backside (BS) transistors should be carefully examined. Here, we thoroughly investigated the coupling effects of FFET at both device and circuit levels using TCAD simulation. For the device level assessment, the coupling effects are measured by the threshold voltage (${V}_{text {th}}$ ) shift and the subthreshold swing (SS) degradation of transistors, as a result of the bias applied on the other side’s transistors. At the circuit level, the propagation delay of FFET inverters was studied. In the worst case scenario, the ${V}_{text {th}}$ shift is up to 135 mV, the SS degradation up to 235 mV/dec (from 72.6 mV/dec), and the inverter’s delay change up to 4.41% is found, which is undesired and intolerable for circuit designs. To address this issue, a novel middle dielectric isolation (MDI) technique was proposed and found to be quite effective in blocking the electrical field from the other side, thus reducing the coupling effects. By implementing the MDI technique, the ${V}_{text {th}}$ shift of no more than 0.85 mV, negligible SS degradation, and the INV’s delay change of less than 0.6% are realized. We also investigated MDI FFET’s gate structure innovations [e.g., Pi-gate, omega-gate (OG), and gate-all-around (GAA)] to enhance the gate control, by which the ${V} _{text {th}}$ shift can be minimized to 0.12 mV. This work paves the way for practical implementation of FFET in the future.
{"title":"Understanding of the Electrostatic Coupling in Flip FET (FFET) and Corresponding Strategies","authors":"Jiacheng Sun;Haoran Lu;Yu Liu;Wanyue Peng;Runsheng Wang;Heng Wu;Ru Huang","doi":"10.1109/TED.2025.3532920","DOIUrl":"https://doi.org/10.1109/TED.2025.3532920","url":null,"abstract":"Flip FET (FFET), a novel self-aligned stacked transistor architecture with dual-sided transistor stacking, was recently proposed and demonstrated. However, due to the vertically stacking nature, the electrical coupling of frontside (FS) and backside (BS) transistors should be carefully examined. Here, we thoroughly investigated the coupling effects of FFET at both device and circuit levels using TCAD simulation. For the device level assessment, the coupling effects are measured by the threshold voltage (<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>) shift and the subthreshold swing (SS) degradation of transistors, as a result of the bias applied on the other side’s transistors. At the circuit level, the propagation delay of FFET inverters was studied. In the worst case scenario, the <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shift is up to 135 mV, the SS degradation up to 235 mV/dec (from 72.6 mV/dec), and the inverter’s delay change up to 4.41% is found, which is undesired and intolerable for circuit designs. To address this issue, a novel middle dielectric isolation (MDI) technique was proposed and found to be quite effective in blocking the electrical field from the other side, thus reducing the coupling effects. By implementing the MDI technique, the <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shift of no more than 0.85 mV, negligible SS degradation, and the INV’s delay change of less than 0.6% are realized. We also investigated MDI FFET’s gate structure innovations [e.g., Pi-gate, omega-gate (OG), and gate-all-around (GAA)] to enhance the gate control, by which the <inline-formula> <tex-math>${V} _{text {th}}$ </tex-math></inline-formula> shift can be minimized to 0.12 mV. This work paves the way for practical implementation of FFET in the future.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"971-978"},"PeriodicalIF":2.9,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-30DOI: 10.1109/TED.2025.3532904
Wang Weidong;Qi Minghong;Jin Shilong;Ding Taotao;Zhao Zhengqian;Ding Zhi;Zhu Ye;Hou Baoyin;Che Lufeng
MEMS gravimeters capable of accurately measuring changes in gravitational acceleration play a vital role in various application fields such as geological studies, crustal deformation monitoring, and solid tide observation. Researchers have rendered the MEMS gravimeters more sensitive by lowering their resonant frequency, allowing for detecting the subtle changes in gravitational acceleration. However, these devices achieve low and stable resonant frequencies only when the angle between their sensitive axis and the horizontal plane is 90°. Although the resonant frequency remains low when this angle is less than 90°, it becomes unstable. To address this issue, we propose a novel MEMS gravimeter that can maintain a consistently low and stable resonant frequency by adjusting the width of the curved beam (CB), even when the angle is less than 90°. Simulation results demonstrate that adjusting the CBs’ width from 5 to $20~mu $ m enables this gravimeter to maintain a stabilized low resonant frequency (<10> $20~mu $ m exhibits a noise power spectral density of $9.2~mu $ Gal/$surd $ Hz at 6 Hz and a bias instability of $4.1~mu $ Gal with an integration time of 1800 s.
{"title":"A Low-Noise MEMS Gravimeter Capable of Attaining Stable Low Resonant Frequency at Various Tilt Angles Through Adjusting Curved Beams’ Width","authors":"Wang Weidong;Qi Minghong;Jin Shilong;Ding Taotao;Zhao Zhengqian;Ding Zhi;Zhu Ye;Hou Baoyin;Che Lufeng","doi":"10.1109/TED.2025.3532904","DOIUrl":"https://doi.org/10.1109/TED.2025.3532904","url":null,"abstract":"MEMS gravimeters capable of accurately measuring changes in gravitational acceleration play a vital role in various application fields such as geological studies, crustal deformation monitoring, and solid tide observation. Researchers have rendered the MEMS gravimeters more sensitive by lowering their resonant frequency, allowing for detecting the subtle changes in gravitational acceleration. However, these devices achieve low and stable resonant frequencies only when the angle between their sensitive axis and the horizontal plane is 90°. Although the resonant frequency remains low when this angle is less than 90°, it becomes unstable. To address this issue, we propose a novel MEMS gravimeter that can maintain a consistently low and stable resonant frequency by adjusting the width of the curved beam (CB), even when the angle is less than 90°. Simulation results demonstrate that adjusting the CBs’ width from 5 to <inline-formula> <tex-math>$20~mu $ </tex-math></inline-formula>m enables this gravimeter to maintain a stabilized low resonant frequency (<10> <tex-math>$20~mu $ </tex-math></inline-formula>m exhibits a noise power spectral density of <inline-formula> <tex-math>$9.2~mu $ </tex-math></inline-formula>Gal/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz at 6 Hz and a bias instability of <inline-formula> <tex-math>$4.1~mu $ </tex-math></inline-formula>Gal with an integration time of 1800 s.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1368-1376"},"PeriodicalIF":2.9,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143519866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-30DOI: 10.1109/TED.2025.3532249
Yushan Zhou;Shuyu Fan;Ziying Zhu;Shanqian Su;Dibo Hou;Hongjian Zhang;Yunqi Cao
This study proposes a novel high-sensitivity calorimetric flow sensor based on vanadium dioxide (VO2) to meet the growing demand for low-flow detection. The thermoresistive effect characterization results of the fabricated VO2 thin film show a temperature coefficient of resistance (TCR) of $99boldsymbol {%}$ /K that is two orders of magnitude higher than that of conventional thermal sensing material, indicating its potential for enhancing the sensitivity of the calorimetric sensor. Notably, it exhibits a nonlinear temperature-dependent hysteretic behavior with the minor resistance-temperature curves nested in the major hysteresis curves, posing a challenge to the practical use of VO2-based sensors. Thus, a comprehensive hysteresis model, utilizing physical model for the major hysteresis loop and modified Preisach models for the minor hysteresis loop, has been established to give an accurate resistance-temperature response, providing a solid basis for the development of high performance sensor based on VO2. The finite element analysis (FEA) confirmed the proposed calorimetric sensor’s superior performance, with a linear range of 0–$0.4~mu $ L/min and a normalized output sensitivity of 11.08 V/(m/s)/mW, consuming 1.5 times less power than dual-heater configurations. The dual-heater calorimetric sensor achieved a sensitivity of 21.23 V/(m/s)/mW in its CH mode, 18.3 times higher than conventional metal-based sensors. This work advances the understanding of VO2 hysteresis for microflow sensor design and paves the way for nonlinear phase-change material (PCM)-based microfluidic sensors.
{"title":"Enabling High-Sensitivity Calorimetric Flow Sensor Using Vanadium Dioxide Phase-Change Material With Predictable Hysteretic Behavior","authors":"Yushan Zhou;Shuyu Fan;Ziying Zhu;Shanqian Su;Dibo Hou;Hongjian Zhang;Yunqi Cao","doi":"10.1109/TED.2025.3532249","DOIUrl":"https://doi.org/10.1109/TED.2025.3532249","url":null,"abstract":"This study proposes a novel high-sensitivity calorimetric flow sensor based on vanadium dioxide (VO2) to meet the growing demand for low-flow detection. The thermoresistive effect characterization results of the fabricated VO2 thin film show a temperature coefficient of resistance (TCR) of <inline-formula> <tex-math>$99boldsymbol {%}$ </tex-math></inline-formula>/K that is two orders of magnitude higher than that of conventional thermal sensing material, indicating its potential for enhancing the sensitivity of the calorimetric sensor. Notably, it exhibits a nonlinear temperature-dependent hysteretic behavior with the minor resistance-temperature curves nested in the major hysteresis curves, posing a challenge to the practical use of VO2-based sensors. Thus, a comprehensive hysteresis model, utilizing physical model for the major hysteresis loop and modified Preisach models for the minor hysteresis loop, has been established to give an accurate resistance-temperature response, providing a solid basis for the development of high performance sensor based on VO2. The finite element analysis (FEA) confirmed the proposed calorimetric sensor’s superior performance, with a linear range of 0–<inline-formula> <tex-math>$0.4~mu $ </tex-math></inline-formula>L/min and a normalized output sensitivity of 11.08 V/(m/s)/mW, consuming 1.5 times less power than dual-heater configurations. The dual-heater calorimetric sensor achieved a sensitivity of 21.23 V/(m/s)/mW in its CH mode, 18.3 times higher than conventional metal-based sensors. This work advances the understanding of VO2 hysteresis for microflow sensor design and paves the way for nonlinear phase-change material (PCM)-based microfluidic sensors.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1360-1367"},"PeriodicalIF":2.9,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-30DOI: 10.1109/TED.2025.3528870
Julien Legendre;Pierre-Olivier Chapuis
Thermophotonic (TPX) devices are radiative heat engines in which the exchange of electroluminescent (EL) radiation between a heated light-emitting diode (LED) and a cool photovoltaic (PV) cell allows for the conversion of heat into electrical power. Here, we introduce coupled radiative and electrical solver for efficient near-field TPX in 1-D (CRESCENT-1D), the solver we have developed to simulate the performance of 1-D TPX systems, which is made publicly available on GitHub. It couples photon transport in the far or near field (NF), based on the fluctuational electrodynamics framework, and charge transport in heterostructures, modeled with the drift–diffusion and Poisson equations. We include both thermionic emission and charge carrier tunneling to precisely model charge transport at heterointerfaces, while the photon chemical potential is computed in a self-consistent manner between the radiative and electrical sections of the solver. Compared to simpler formulations, these models provide accurate results at high voltages, which is essential to achieve high-power output. The capabilities of CRESCENT-1D are illustrated with an optimized InGaP/InGaAs TPX heterostructure, whose maximum power reaches $1.6~text {W}cdot text { cm}^{-{2}}$ for an efficiency of 19.7% considering a 300-K temperature difference between the LED and the PV cell. This solver makes it possible for anyone to design various categories of optoelectronic structures (TPX, LED, thermophotovoltaic (TPV), thermoradiative, etc.), and represent an important step in the development of near-field radiative heat engines.
{"title":"CRESCENT-1D: A 1-D Solver of Coupled Charge and Light Transport in Heterostructures for the Design of Near-Field Thermophotonic Engines","authors":"Julien Legendre;Pierre-Olivier Chapuis","doi":"10.1109/TED.2025.3528870","DOIUrl":"https://doi.org/10.1109/TED.2025.3528870","url":null,"abstract":"Thermophotonic (TPX) devices are radiative heat engines in which the exchange of electroluminescent (EL) radiation between a heated light-emitting diode (LED) and a cool photovoltaic (PV) cell allows for the conversion of heat into electrical power. Here, we introduce coupled radiative and electrical solver for efficient near-field TPX in 1-D (CRESCENT-1D), the solver we have developed to simulate the performance of 1-D TPX systems, which is made publicly available on GitHub. It couples photon transport in the far or near field (NF), based on the fluctuational electrodynamics framework, and charge transport in heterostructures, modeled with the drift–diffusion and Poisson equations. We include both thermionic emission and charge carrier tunneling to precisely model charge transport at heterointerfaces, while the photon chemical potential is computed in a self-consistent manner between the radiative and electrical sections of the solver. Compared to simpler formulations, these models provide accurate results at high voltages, which is essential to achieve high-power output. The capabilities of CRESCENT-1D are illustrated with an optimized InGaP/InGaAs TPX heterostructure, whose maximum power reaches <inline-formula> <tex-math>$1.6~text {W}cdot text { cm}^{-{2}}$ </tex-math></inline-formula> for an efficiency of 19.7% considering a 300-K temperature difference between the LED and the PV cell. This solver makes it possible for anyone to design various categories of optoelectronic structures (TPX, LED, thermophotovoltaic (TPV), thermoradiative, etc.), and represent an important step in the development of near-field radiative heat engines.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1211-1220"},"PeriodicalIF":2.9,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Current transport in polysilicon is a complicated process with many factors to consider. The inhomogeneous nature of polysilicon with its differently shaped and sized grains is one such consideration. We have developed a method that enhances existing resistivity models with a 2-D extension that incorporates the grain size distribution using a Voronoi-based resistor network. We obtain grain size distributions both from our growth simulations (700, 800, and 900 K) and experimental analysis. Applying our method, we investigate the effect that variation in grain size produces with cases of different average grain sizes (2 nm–$3~mu $ m). For example, the resistivity of polysilicon with an average grain size of 175 nm drops from 11 to 4.5 k$Omega cdot $ cm when compared with conventional 1-D modeling. Our study highlights the strong effect of grain size variation on resistivity, revealing that wider distributions result in significant resistivity reductions of up to more than 50%. Due to larger grains present with a grain size distribution, current transport encounters fewer grain boundaries while the average grain size remains the same resulting in fewer barriers along the current transport path. Incorporating the grain structure into the resistivity modeling facilitates a more detailed and comprehensive characterization of the electrical properties of polysilicon.
多晶硅中的电流传输是一个复杂的过程，需要考虑很多因素。多晶硅的非均质性及其不同形状和尺寸的晶粒就是考虑因素之一。我们开发了一种方法，利用基于 Voronoi 的电阻网络将晶粒尺寸分布纳入二维扩展，从而增强了现有的电阻率模型。我们从生长模拟（700、800 和 900 K）和实验分析中获得了晶粒尺寸分布。应用我们的方法，我们研究了不同平均晶粒尺寸（2 nm- $3~mu $ m）情况下晶粒尺寸变化产生的影响。例如，与传统的一维建模相比，平均晶粒尺寸为 175 nm 的多晶硅的电阻率从 11 k $Omega cdot $ cm 下降到 4.5 k $Omega cdot $ cm。我们的研究强调了晶粒尺寸变化对电阻率的强烈影响，揭示了更宽的分布会导致电阻率显著降低，降幅可达 50%以上。由于晶粒尺寸分布中存在较大的晶粒，电流传输遇到的晶粒边界较少，而平均晶粒尺寸保持不变，因此电流传输路径上的障碍较少。将晶粒结构纳入电阻率建模有助于更详细、更全面地描述多晶硅的电气特性。
{"title":"A Detailed Examination of Polysilicon Resistivity Incorporating the Grain Size Distribution","authors":"Mikael Santonen;Antti Lahti;Zahra Jahanshah Rad;Mikko Miettinen;Masoud Ebrahimzadeh;Juha-Pekka Lehtiö;Enni Snellman;Pekka Laukkanen;Marko Punkkinen;Kalevi Kokko;Katja Parkkinen;Markus Eklund","doi":"10.1109/TED.2025.3530865","DOIUrl":"https://doi.org/10.1109/TED.2025.3530865","url":null,"abstract":"Current transport in polysilicon is a complicated process with many factors to consider. The inhomogeneous nature of polysilicon with its differently shaped and sized grains is one such consideration. We have developed a method that enhances existing resistivity models with a 2-D extension that incorporates the grain size distribution using a Voronoi-based resistor network. We obtain grain size distributions both from our growth simulations (700, 800, and 900 K) and experimental analysis. Applying our method, we investigate the effect that variation in grain size produces with cases of different average grain sizes (2 nm–<inline-formula> <tex-math>$3~mu $ </tex-math></inline-formula>m). For example, the resistivity of polysilicon with an average grain size of 175 nm drops from 11 to 4.5 k<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm when compared with conventional 1-D modeling. Our study highlights the strong effect of grain size variation on resistivity, revealing that wider distributions result in significant resistivity reductions of up to more than 50%. Due to larger grains present with a grain size distribution, current transport encounters fewer grain boundaries while the average grain size remains the same resulting in fewer barriers along the current transport path. Incorporating the grain structure into the resistivity modeling facilitates a more detailed and comprehensive characterization of the electrical properties of polysilicon.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1184-1190"},"PeriodicalIF":2.9,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10857810","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In our previous study, we successfully generated subnanosecond microwave pulses with a high power compression factor using a standard rectangular waveguide. However, the compressor loss is substantial due to the operating frequency being close to the cutoff frequency, which greatly limits the power compression factor. The novelty of this manuscript is using a unilateral overmoded waveguide to mitigate the loss, thereby improving the efficiency and the power compression factor. Calculations indicate that the compressor loss could potentially be reduced by 48.9%, while the optimal power compression factor could increase by 104.5%, rising from 58.5 to 119.7, compared with the result of the standard waveguide. Under our current experimental conditions, we used a 5-m long overmoded waveguide compressor for proof of principle and generated an ultrashort pulse with a power compression factor of 50.2 and a 3 dB pulsewidth of 266 ps. Compared with the standard waveguide, the compressor loss was reduced by 13.5%, and the power compression factor increased by 13.6%. The experimental results are in good agreement with the simulations, indicating that this method has the potential to enhance the power compression factor and enable it to exceed 100.
{"title":"Increasing the Power Compression Factor by Overmoded Waveguide for Subnanosecond Microwave Pulse Generation","authors":"Zhiyuan Zhang;Ruoyang Pan;Weijie Wang;Yelei Yao;Wei Jiang;Zeiwei Wu;Youlei Pu;Jianxun Wang;Yong Luo;Guo Liu","doi":"10.1109/TED.2025.3532575","DOIUrl":"https://doi.org/10.1109/TED.2025.3532575","url":null,"abstract":"In our previous study, we successfully generated subnanosecond microwave pulses with a high power compression factor using a standard rectangular waveguide. However, the compressor loss is substantial due to the operating frequency being close to the cutoff frequency, which greatly limits the power compression factor. The novelty of this manuscript is using a unilateral overmoded waveguide to mitigate the loss, thereby improving the efficiency and the power compression factor. Calculations indicate that the compressor loss could potentially be reduced by 48.9%, while the optimal power compression factor could increase by 104.5%, rising from 58.5 to 119.7, compared with the result of the standard waveguide. Under our current experimental conditions, we used a 5-m long overmoded waveguide compressor for proof of principle and generated an ultrashort pulse with a power compression factor of 50.2 and a 3 dB pulsewidth of 266 ps. Compared with the standard waveguide, the compressor loss was reduced by 13.5%, and the power compression factor increased by 13.6%. The experimental results are in good agreement with the simulations, indicating that this method has the potential to enhance the power compression factor and enable it to exceed 100.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1435-1440"},"PeriodicalIF":2.9,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-28DOI: 10.1109/TED.2025.3531836
Qiang Zhang;Quan Zhang;Yunfei Sun;Chengwei Yuan;Xuan Liu;Zhenqiang Cao
In this article, a compact TM$^{circ }_{{01}}$ to TE$^{circ }_{{01}}$ (symbol $bigcirc $ represents the circular waveguide) mode converter for X-band high-power microwave (HPM) applications is designed, fabricated, and experimentally verified. The proposed device comprises three parts, which are a TM$^{circ }_{{01}}$ to vertical polarization (VP) TE$^{scriptscriptstyle square }_{{10}}$ (symbol □ represents the rectangle waveguide) mode power divider, a horizontal polarization (HP) TE$^{scriptscriptstyle square }_{{10}}$ to TE$^{circ }_{{01}}$ mode power combiner, and an N-way TE$^{scriptscriptstyle square }_{{10}}$ circumferential array polarization torsion structure (CA-PTS). The first two parts utilize the topologic structures of radial power dividers (RPDs), which are then connected by the CA-PTS. This novel methodology makes the input and output ports of the mode converter on the same axis, with the transverse and longitudinal dimensions of approximately $8.6lambda _{{0}}$ and $3.5lambda _{{0}}$ , respectively. Simulation results of the TM$^{circ }_{{01}}$ to TE$^{circ }_{{01}}$ mode converter demonstrate that the return loss is better than −15.0 dB from 8.28 to 8.74 GHz, while the insertion loss remains below −0.2 dB, and a remarkable conversion efficiency achieves 99.21% at the center frequency of 8.4 GHz. An 18-way prototype was subjected to experiments. The measured S-parameter results of the setup were in good agreement with simulation one. Under an input power of 0.5 W, the simulated maximum internal electric field measured 943 V/m, and the power handling capacity (PHC) was also validated in the HPM test.
{"title":"Design and Experiment of a Compact Circular Waveguide TM₀₁ to TE₀₁ Mode Converter","authors":"Qiang Zhang;Quan Zhang;Yunfei Sun;Chengwei Yuan;Xuan Liu;Zhenqiang Cao","doi":"10.1109/TED.2025.3531836","DOIUrl":"https://doi.org/10.1109/TED.2025.3531836","url":null,"abstract":"In this article, a compact TM<inline-formula> <tex-math>$^{circ }_{{01}}$ </tex-math></inline-formula> to TE<inline-formula> <tex-math>$^{circ }_{{01}}$ </tex-math></inline-formula> (symbol <inline-formula> <tex-math>$bigcirc $ </tex-math></inline-formula> represents the circular waveguide) mode converter for X-band high-power microwave (HPM) applications is designed, fabricated, and experimentally verified. The proposed device comprises three parts, which are a TM<inline-formula> <tex-math>$^{circ }_{{01}}$ </tex-math></inline-formula> to vertical polarization (VP) TE<inline-formula> <tex-math>$^{scriptscriptstyle square }_{{10}}$ </tex-math></inline-formula> (symbol □ represents the rectangle waveguide) mode power divider, a horizontal polarization (HP) TE<inline-formula> <tex-math>$^{scriptscriptstyle square }_{{10}}$ </tex-math></inline-formula> to TE<inline-formula> <tex-math>$^{circ }_{{01}}$ </tex-math></inline-formula> mode power combiner, and an N-way TE<inline-formula> <tex-math>$^{scriptscriptstyle square }_{{10}}$ </tex-math></inline-formula> circumferential array polarization torsion structure (CA-PTS). The first two parts utilize the topologic structures of radial power dividers (RPDs), which are then connected by the CA-PTS. This novel methodology makes the input and output ports of the mode converter on the same axis, with the transverse and longitudinal dimensions of approximately <inline-formula> <tex-math>$8.6lambda _{{0}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$3.5lambda _{{0}}$ </tex-math></inline-formula>, respectively. Simulation results of the TM<inline-formula> <tex-math>$^{circ }_{{01}}$ </tex-math></inline-formula> to TE<inline-formula> <tex-math>$^{circ }_{{01}}$ </tex-math></inline-formula> mode converter demonstrate that the return loss is better than −15.0 dB from 8.28 to 8.74 GHz, while the insertion loss remains below −0.2 dB, and a remarkable conversion efficiency achieves 99.21% at the center frequency of 8.4 GHz. An 18-way prototype was subjected to experiments. The measured S-parameter results of the setup were in good agreement with simulation one. Under an input power of 0.5 W, the simulated maximum internal electric field measured 943 V/m, and the power handling capacity (PHC) was also validated in the HPM test.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1412-1418"},"PeriodicalIF":2.9,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we perform the low-frequency noise (LFN) characterization of back-end-of-line (BEOL) compatible transistors. Specifically, the noise performance of oxide channel (W-doped In2O3, or IWO) transistors with a dielectric gate (IWOMOSFET) and ferroelectric gate (IWO FeFET) is studied and compared. The objective of this study is to understand the impact of a ferroelectric gate on the device reliability under dc stress. The normalized noise power spectral density (${S}_{I}/{I}_{D}^{,{2}}$ ) value is extracted for a fresh device and stressed device. We find that a ferroelectric gate-stack induces $3times $ more noise than a dielectric gate-stack. Further, the increase in post stress ${S}_{I}/{I}_{D}^{,{2}}$ for IWO FeFET is $7.5times $ higher than that for IWO MOSFET under positive stress voltage, and negligible for both devices under negative stress voltage. We conclude that the stress induced by the same gate voltage in IWO FeFET is higher than that in IWO MOSFET is due to the electric field enhancement caused by polarization in the ferroelectric gate-stack, which leads to more defect generation under the stress.
{"title":"Effect of DC Stress on Low-Frequency Noise Characteristics of W-Doped In2O3 BEOL Transistors","authors":"Omkar Phadke;Khandker Akif Aabrar;Gihun Choe;Yuan-Chun Luo;Sharadindu Gopal Kirtania;Asif Islam Khan;Suman Datta;Shimeng Yu","doi":"10.1109/TED.2025.3532234","DOIUrl":"https://doi.org/10.1109/TED.2025.3532234","url":null,"abstract":"In this article, we perform the low-frequency noise (LFN) characterization of back-end-of-line (BEOL) compatible transistors. Specifically, the noise performance of oxide channel (W-doped In2O3, or IWO) transistors with a dielectric gate (IWOMOSFET) and ferroelectric gate (IWO FeFET) is studied and compared. The objective of this study is to understand the impact of a ferroelectric gate on the device reliability under dc stress. The normalized noise power spectral density (<inline-formula> <tex-math>${S}_{I}/{I}_{D}^{,{2}}$ </tex-math></inline-formula>) value is extracted for a fresh device and stressed device. We find that a ferroelectric gate-stack induces <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> more noise than a dielectric gate-stack. Further, the increase in post stress <inline-formula> <tex-math>${S}_{I}/{I}_{D}^{,{2}}$ </tex-math></inline-formula> for IWO FeFET is <inline-formula> <tex-math>$7.5times $ </tex-math></inline-formula> higher than that for IWO MOSFET under positive stress voltage, and negligible for both devices under negative stress voltage. We conclude that the stress induced by the same gate voltage in IWO FeFET is higher than that in IWO MOSFET is due to the electric field enhancement caused by polarization in the ferroelectric gate-stack, which leads to more defect generation under the stress.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1489-1493"},"PeriodicalIF":2.9,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143580903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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