Pub Date : 2025-09-29DOI: 10.1109/TED.2025.3608778
Jimyoung Lee;Seung Kyu Kim;Kwang Young Lee;Jongwook Jeon
The complementary field-effect transistors (CFETs) are promising for next-generation logic devices, but tall vias (TVs) face challenges, including high resistance, parasitic capacitance, and metal void defects. This study evaluates three source-side to backside power delivery network (BSPDN) interconnect structures: conventional TV, line-type TV (LTV), and frontside connection (FSC). FSC utilizes frontside metal lines with power tap cells (PTCs) for front-to-back connectivity, offering a scalable solution. Through 3D-TCAD simulations, we analyze their cell-level and area-adjusted performance. FSC achieves a + 2.2% higher frequency at the same power (Freq. at $P$ ) and a −4.7% lower power at the same frequency (Power at F) compared to TV, while maintaining consistent performance across cell height (CH) scaling. In contrast, TV and LTV exhibit degradation due to increased resistance and capacitance at reduced CH. FSC’s sweet zone (12–71 CPPs) ensures sufficient margin for PTC insertion, delivering a 1.7% Freq. at $P$ gain at 31 CPPs and 12% area reduction at zero frequency offset. Notably, FSC’s compatibility with nonvertical via profiles (essential for void prevention) further enhances its advantages in real processes. These results demonstrate FSC’s superior power, performance, and area (PPA) characteristics, positioning it as a robust alternative to TV/LTV for CFET architectures. The study provides critical insights for advancing the next-generation logic devices.
{"title":"Area-Adjusted Comparison of BSPDN Interconnects in CFET: Superiority of Frontside Connection","authors":"Jimyoung Lee;Seung Kyu Kim;Kwang Young Lee;Jongwook Jeon","doi":"10.1109/TED.2025.3608778","DOIUrl":"https://doi.org/10.1109/TED.2025.3608778","url":null,"abstract":"The complementary field-effect transistors (CFETs) are promising for next-generation logic devices, but tall vias (TVs) face challenges, including high resistance, parasitic capacitance, and metal void defects. This study evaluates three source-side to backside power delivery network (BSPDN) interconnect structures: conventional TV, line-type TV (LTV), and frontside connection (FSC). FSC utilizes frontside metal lines with power tap cells (PTCs) for front-to-back connectivity, offering a scalable solution. Through 3D-TCAD simulations, we analyze their cell-level and area-adjusted performance. FSC achieves a + 2.2% higher frequency at the same power (Freq. at <inline-formula> <tex-math>$P$ </tex-math></inline-formula>) and a −4.7% lower power at the same frequency (Power at F) compared to TV, while maintaining consistent performance across cell height (CH) scaling. In contrast, TV and LTV exhibit degradation due to increased resistance and capacitance at reduced CH. FSC’s sweet zone (12–71 CPPs) ensures sufficient margin for PTC insertion, delivering a 1.7% Freq. at <inline-formula> <tex-math>$P$ </tex-math></inline-formula> gain at 31 CPPs and 12% area reduction at zero frequency offset. Notably, FSC’s compatibility with nonvertical via profiles (essential for void prevention) further enhances its advantages in real processes. These results demonstrate FSC’s superior power, performance, and area (PPA) characteristics, positioning it as a robust alternative to TV/LTV for CFET architectures. The study provides critical insights for advancing the next-generation logic devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6329-6335"},"PeriodicalIF":3.2,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-26DOI: 10.1109/TED.2025.3612316
Muhammad Asghar Khan;Yelim Kang;Muhammad Farooq Khan;Shania Rehman;Min Jong Lee;Sang Heon Lee;Seunghyun Oh;Tae Hyuk Kim;Seon Joong Kim;Hyungju Ahn;Jae Won Shim
Organic semiconductors exhibit significant potential for application in artificial neuromorphic computing because of their unique electrical and optoelectronic properties. In this study, we explore the potential of the nonfullerene Y6 (also known as BTP-4F) organic semiconductor material in optoelectronic neuromorphic computing, image recognition, reservoir computing (RC), and wireless encrypted communication. The organic field-effect transistor (OFET) constructed using the Y6 polymer exhibits n-type semiconductor behavior with a current on–off ($I_{mathrm{ON}} / I_{mathrm{OFF}}$ ) ratio of approximately $10^{{2}}$ as well as excellent synaptic functionalities under ultraviolet (UV) light. The synaptic plasticity of OFET is demonstrated to be optically controllable using incident light of 220-nm wavelength. Notably, the transition from short-term memory (STM) to long-term memory (LTM) could be modulated by manipulating pulse time, pulse number, and pulse interval. Furthermore, image recognition on the Modified National Institute of Standards and Technology (MNIST) dataset using the fabricated device in conjunction with a convolutional neural network (CNN) is observed to yield an excellent accuracy of 93.4%. Moreover, we demonstrate the application of Y6 OFET in a 4-bit RC for digit classification. Finally, optically encrypted communication is also achieved based on the international Morse code. These findings demonstrate the potential of Y6-based OFETs in neuromorphic computing, RC, and encrypted communication, paving the way for innovations in brain-inspired computing and artificial intelligence (AI) hardware.
{"title":"Ultraviolet Light-Driven Artificial Neuromorphic Properties in Organic Transistors for Reservoir Computing and Encrypted Communication","authors":"Muhammad Asghar Khan;Yelim Kang;Muhammad Farooq Khan;Shania Rehman;Min Jong Lee;Sang Heon Lee;Seunghyun Oh;Tae Hyuk Kim;Seon Joong Kim;Hyungju Ahn;Jae Won Shim","doi":"10.1109/TED.2025.3612316","DOIUrl":"https://doi.org/10.1109/TED.2025.3612316","url":null,"abstract":"Organic semiconductors exhibit significant potential for application in artificial neuromorphic computing because of their unique electrical and optoelectronic properties. In this study, we explore the potential of the nonfullerene Y6 (also known as BTP-4F) organic semiconductor material in optoelectronic neuromorphic computing, image recognition, reservoir computing (RC), and wireless encrypted communication. The organic field-effect transistor (OFET) constructed using the Y6 polymer exhibits n-type semiconductor behavior with a current <sc>on</small>–<sc>off</small> (<inline-formula> <tex-math>$I_{mathrm{ON}} / I_{mathrm{OFF}}$ </tex-math></inline-formula>) ratio of approximately <inline-formula> <tex-math>$10^{{2}}$ </tex-math></inline-formula> as well as excellent synaptic functionalities under ultraviolet (UV) light. The synaptic plasticity of OFET is demonstrated to be optically controllable using incident light of 220-nm wavelength. Notably, the transition from short-term memory (STM) to long-term memory (LTM) could be modulated by manipulating pulse time, pulse number, and pulse interval. Furthermore, image recognition on the Modified National Institute of Standards and Technology (MNIST) dataset using the fabricated device in conjunction with a convolutional neural network (CNN) is observed to yield an excellent accuracy of 93.4%. Moreover, we demonstrate the application of Y6 OFET in a 4-bit RC for digit classification. Finally, optically encrypted communication is also achieved based on the international Morse code. These findings demonstrate the potential of Y6-based OFETs in neuromorphic computing, RC, and encrypted communication, paving the way for innovations in brain-inspired computing and artificial intelligence (AI) hardware.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6341-6348"},"PeriodicalIF":3.2,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/TED.2025.3608842
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/TED.2025.3608842","DOIUrl":"https://doi.org/10.1109/TED.2025.3608842","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 10","pages":"5774-5775"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11176793","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145121311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/TED.2025.3608844
{"title":"IEEE Transactions on Electron Devices Information for Authors","authors":"","doi":"10.1109/TED.2025.3608844","DOIUrl":"https://doi.org/10.1109/TED.2025.3608844","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 10","pages":"C3-C3"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11176796","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145121312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gate oxide scaling is essential for enhancing the performance of amorphous oxide semiconductor (AOS) field-effect transistors, yet it remains limited by charge trapping and interface quality. In this work, we demonstrate tungsten-doped In2O3 indium–tungsten oxide (IWO) MOSFETs incorporating an amorphous HfO2/ZrO2/HfO2 (HZH) trilayer gate dielectric that achieves an equivalent oxide thickness (EOT) as low as $3~unicode{0x00C5}$ . The transistors exhibit near-ideal subthreshold swing (SS) (75 mV/decade), high on-state current ($gt 240~{mu }$ A/$mu $ m), and suppressed gate leakage even at this extreme limit of EOT scaling. Positive bias-stress (PBS) tests reveal improved reliability in HZH compared with conventional HfO2, with minimal threshold voltage shift. Through density-gradient-based numerical modeling and analytical stress-recovery simulations, we show that these improvements originate from spatial and energetic redistribution of oxygen vacancy induced traps into the ZrO2-rich region, away from the channel interface. The consequent reduction in the density of acceptor-like subgap states collectively improves carrier mobility and mitigates trap-limited conduction (TLC). These results highlight the potential of targeted gate-stack engineering in extending conventional EOT scaling benefits to AOS transistors.
{"title":"Extreme EOT Scaling in Tungsten-Doped In2O3 MOSFETs for Enhanced Stability and Drive Current","authors":"Hyeonwoo Park;Sharadindu Gopal Kirtania;Eknath Sarkar;Dyutimoy Chakraborty;Chengyang Zhang;Hyun Jae Lee;Jaewon Shin;Shimeng Yu;Asif Khan;H. Kim;C. Im;M. J. Hong;Daewon Ha;Suman Datta","doi":"10.1109/TED.2025.3612345","DOIUrl":"https://doi.org/10.1109/TED.2025.3612345","url":null,"abstract":"Gate oxide scaling is essential for enhancing the performance of amorphous oxide semiconductor (AOS) field-effect transistors, yet it remains limited by charge trapping and interface quality. In this work, we demonstrate tungsten-doped In<sub>2</sub>O<sub>3</sub> indium–tungsten oxide (IWO) MOSFETs incorporating an amorphous HfO<sub>2</sub>/ZrO<sub>2</sub>/HfO<sub>2</sub> (HZH) trilayer gate dielectric that achieves an equivalent oxide thickness (EOT) as low as <inline-formula> <tex-math>$3~unicode{0x00C5}$ </tex-math></inline-formula>. The transistors exhibit near-ideal subthreshold swing (SS) (75 mV/decade), high <sc>on</small>-state current (<inline-formula> <tex-math>$gt 240~{mu }$ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m), and suppressed gate leakage even at this extreme limit of EOT scaling. Positive bias-stress (PBS) tests reveal improved reliability in HZH compared with conventional HfO<sub>2</sub>, with minimal threshold voltage shift. Through density-gradient-based numerical modeling and analytical stress-recovery simulations, we show that these improvements originate from spatial and energetic redistribution of oxygen vacancy induced traps into the ZrO<sub>2</sub>-rich region, away from the channel interface. The consequent reduction in the density of acceptor-like subgap states collectively improves carrier mobility and mitigates trap-limited conduction (TLC). These results highlight the potential of targeted gate-stack engineering in extending conventional EOT scaling benefits to AOS transistors.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7136-7144"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/TED.2025.3609307
Xiaolei Zhang;Jiahao Lin;Chuandu Zhang;Wei Xu
The accurate monitoring of low-range pressure variations is crucial in many biomedical and wearable sensing applications, where abnormal pressure levels can indicate potential health risks. This brief presents a passive wireless inductor–capacitor (LC) pressure sensor, developed using MEMS and flexible printed circuit board (FPCB) technologies for low-range pressure monitoring. The sensor comprises a 16.2-$mu $ m-thick MEMS layer with a 2-mm circular electrode, a bottom electrode with an integrated spiral inductor on the FPCB, and a 50-$mu $ m laser-cut polyimide (PI) intermediate layer forming the capacitive structure. Simulations and experimental evaluations in a controlled low-pressure water environment confirmed stable performance and close agreement between theoretical and measured responses over the 100–5000-Pa range. By accounting for parasitic capacitance effects from water environments and interlayer interactions, the sensor still achieves a high average sensitivity of 5.15 MHz/kPa, a fine resolution of 25 Pa, and a low-temperature coefficient of frequency (TCF) of 173 ppm/°C. With its compact, flexible, and wireless design, the proposed sensor holds strong potential for continuous physiological pressure monitoring.
{"title":"A Compact Wireless Passive Pressure Sensor With High Sensitivity and Resolution Based on MEMS–FPCB Integration","authors":"Xiaolei Zhang;Jiahao Lin;Chuandu Zhang;Wei Xu","doi":"10.1109/TED.2025.3609307","DOIUrl":"https://doi.org/10.1109/TED.2025.3609307","url":null,"abstract":"The accurate monitoring of low-range pressure variations is crucial in many biomedical and wearable sensing applications, where abnormal pressure levels can indicate potential health risks. This brief presents a passive wireless inductor–capacitor (<italic>LC</i>) pressure sensor, developed using MEMS and flexible printed circuit board (FPCB) technologies for low-range pressure monitoring. The sensor comprises a 16.2-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick MEMS layer with a 2-mm circular electrode, a bottom electrode with an integrated spiral inductor on the FPCB, and a 50-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m laser-cut polyimide (PI) intermediate layer forming the capacitive structure. Simulations and experimental evaluations in a controlled low-pressure water environment confirmed stable performance and close agreement between theoretical and measured responses over the 100–5000-Pa range. By accounting for parasitic capacitance effects from water environments and interlayer interactions, the sensor still achieves a high average sensitivity of 5.15 MHz/kPa, a fine resolution of 25 Pa, and a low-temperature coefficient of frequency (TCF) of 173 ppm/°C. With its compact, flexible, and wireless design, the proposed sensor holds strong potential for continuous physiological pressure monitoring.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6391-6395"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Synaptic transistors are fabricated using chitosan as the gate dielectric and CuI with sputtered ITO as the channel. Surface charge-transfer doping from the ITO enhanced the performance and operational stability of the devices. Meanwhile, the application of voltage pulses enables the devices to emulate synaptic characteristics, including excitatory postsynaptic currents (EPSCs), inhibitory postsynaptic currents (IPSCs), paired-pulse facilitation (PPF), short-term plasticity (STP), and spike-frequency-dependent plasticity (SFDP). Furthermore, the transistors exhibit the capacity to modulate synaptic weights bidirectionally by realizing both long-term potentiation (LTP) and long-term depression (LTD), with good repeatability. The biomimetic synaptic properties of the devices enable them to emulate the learning behaviors observed in biological systems. These findings highlight the potential of CuI-ITO transistors in neuromorphic applications that demand adaptive learning and real-time signal processing, thereby offering a promising pathway toward the advancement of artificial intelligence systems.
{"title":"Synaptic Plasticity and Learning Behavior Emulated in CuI-ITO Transistors","authors":"Yuling Peng;Wei Dou;Jiangyun Lei;Pengfei Chen;Xiaodong Xu;Dongsheng Tang","doi":"10.1109/TED.2025.3609305","DOIUrl":"https://doi.org/10.1109/TED.2025.3609305","url":null,"abstract":"Synaptic transistors are fabricated using chitosan as the gate dielectric and CuI with sputtered ITO as the channel. Surface charge-transfer doping from the ITO enhanced the performance and operational stability of the devices. Meanwhile, the application of voltage pulses enables the devices to emulate synaptic characteristics, including excitatory postsynaptic currents (EPSCs), inhibitory postsynaptic currents (IPSCs), paired-pulse facilitation (PPF), short-term plasticity (STP), and spike-frequency-dependent plasticity (SFDP). Furthermore, the transistors exhibit the capacity to modulate synaptic weights bidirectionally by realizing both long-term potentiation (LTP) and long-term depression (LTD), with good repeatability. The biomimetic synaptic properties of the devices enable them to emulate the learning behaviors observed in biological systems. These findings highlight the potential of CuI-ITO transistors in neuromorphic applications that demand adaptive learning and real-time signal processing, thereby offering a promising pathway toward the advancement of artificial intelligence systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6336-6340"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/TED.2025.3608840
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Reliability of Advanced Nodes","authors":"","doi":"10.1109/TED.2025.3608840","DOIUrl":"https://doi.org/10.1109/TED.2025.3608840","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 10","pages":"5772-5773"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11176794","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145121310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we report performance enhancement and reliability improvement of oxide semiconductor FETs (OS FETs) by polycrystalline Ga-doped InOx (poly-IGO). Atomic layer deposition (ALD) and post-deposition annealing (PDA) were employed to achieve crystallization of IGO. A systematic study of bottom-gate (BG) FETs with varied Ga concentrations and film thicknesses identified optimized conditions yielding a mobility up to 81 cm2/V $cdot $ s. Low-temperature measurements were conducted to physically understand the mobility improvement. The carrier transport mechanisms were discussed. Then, we developed a novel selective crystallization method in the OS stack for process integration and device operation of gate-all-around (GAA) nanosheet (NS) IGO FETs. The fabricated GAA IGO FETs showed normally-off operation, high on-current of $326~mu $ A/$mu $ m, and a steep subthreshold slope of 68 mV/dec. In addition, GAA NS FETs exhibited further improved bias stress stability. This work provides a scalable strategy of poly-OS channels for monolithic 3-D (M3D) integration and 3-D memory such as 3-D DRAM and 3-D NAND.
{"title":"A Gate-All-Around Oxide Semiconductor FETs With Selectively Crystallized InGaOₓ Channel for Performance and Reliability Improvement","authors":"Ki-Woong Park;Anlan Chen;Kota Sakai;Sunbin Hwang;Xingyu Huang;Takuya Saraya;Toshiro Hiramoto;Takanori Takahashi;Mutsunori Uenuma;Yukiharu Uraoka;Masaharu Kobayashi","doi":"10.1109/TED.2025.3605574","DOIUrl":"https://doi.org/10.1109/TED.2025.3605574","url":null,"abstract":"In this article, we report performance enhancement and reliability improvement of oxide semiconductor FETs (OS FETs) by polycrystalline Ga-doped InOx (poly-IGO). Atomic layer deposition (ALD) and post-deposition annealing (PDA) were employed to achieve crystallization of IGO. A systematic study of bottom-gate (BG) FETs with varied Ga concentrations and film thicknesses identified optimized conditions yielding a mobility up to 81 cm2/V <inline-formula> <tex-math>$cdot $ </tex-math></inline-formula> s. Low-temperature measurements were conducted to physically understand the mobility improvement. The carrier transport mechanisms were discussed. Then, we developed a novel selective crystallization method in the OS stack for process integration and device operation of gate-all-around (GAA) nanosheet (NS) IGO FETs. The fabricated GAA IGO FETs showed normally-<sc>off</small> operation, high <sc>on</small>-current of <inline-formula> <tex-math>$326~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, and a steep subthreshold slope of 68 mV/dec. In addition, GAA NS FETs exhibited further improved bias stress stability. This work provides a scalable strategy of poly-OS channels for monolithic 3-D (M3D) integration and 3-D memory such as 3-D DRAM and 3-D NAND.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7128-7135"},"PeriodicalIF":3.2,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1109/TED.2025.3605320
Yuzhuo Yuan;Guangshun Li;Daohui Ge;Tingting Liu;Qian Xin;Aimin Song
Neuromorphic system may overcome von Neumann bottleneck and achieve higher computational efficiency. Among various approaches, oxide-based synaptic transistors have gained significant attention due to their tunable physical properties and compatibility with large-area industrial manufacturing. However, most reported artificial synapses are n-type, while p-type remain scarce. In this article, p-type tin monoxide (SnO) transistor with high hysteresis current of 1157.5 nA is realized by optimizing the annealing condition. Both excitatory and inhibitory plasticity can be realized within a single thin-film transistor (TFT) device, enhancing its functionality for neuromorphic applications. The observed linear dependence of postsynaptic current on the spike voltage simplifies computation complexity and enhancing efficiency. Additionally, essential synaptic functions including spike-duration dependent plasticity (SDDP), paired-pulse facilitation (PPF), paired-pulse depression (PPD), AtkinsonShiffrin memory mode, high-pass filter, spike-timingdependent plasticity (STDP), and anti-STDP are also successfully simulated. Furthermore, the p-type SnO material demonstrates low cytotoxicity. The synaptic plasticity of p-type SnO-based synaptic transistor effectively mimics biological synapse behavior, highlighting its potential to construct high-performance complementary neuromorphic systems.
{"title":"Gate-Tunable Synaptic Transistors Based on P-Type SnO for Complementary Neuromorphic System","authors":"Yuzhuo Yuan;Guangshun Li;Daohui Ge;Tingting Liu;Qian Xin;Aimin Song","doi":"10.1109/TED.2025.3605320","DOIUrl":"https://doi.org/10.1109/TED.2025.3605320","url":null,"abstract":"Neuromorphic system may overcome von Neumann bottleneck and achieve higher computational efficiency. Among various approaches, oxide-based synaptic transistors have gained significant attention due to their tunable physical properties and compatibility with large-area industrial manufacturing. However, most reported artificial synapses are n-type, while p-type remain scarce. In this article, p-type tin monoxide (SnO) transistor with high hysteresis current of 1157.5 nA is realized by optimizing the annealing condition. Both excitatory and inhibitory plasticity can be realized within a single thin-film transistor (TFT) device, enhancing its functionality for neuromorphic applications. The observed linear dependence of postsynaptic current on the spike voltage simplifies computation complexity and enhancing efficiency. Additionally, essential synaptic functions including spike-duration dependent plasticity (SDDP), paired-pulse facilitation (PPF), paired-pulse depression (PPD), AtkinsonShiffrin memory mode, high-pass filter, spike-timingdependent plasticity (STDP), and anti-STDP are also successfully simulated. Furthermore, the p-type SnO material demonstrates low cytotoxicity. The synaptic plasticity of p-type SnO-based synaptic transistor effectively mimics biological synapse behavior, highlighting its potential to construct high-performance complementary neuromorphic systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6315-6320"},"PeriodicalIF":3.2,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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