We propose a novel approach that combines machine learning (ML) and Pareto optimization to simultaneously enhance the program efficiency and disturbance of 3D-NAND flash memory. The relationship between program pulse (PP) shapes and threshold voltage shifts has never been investigated owing to the presence of numerous PP shapes. The complex relationship is modeled rapidly and quantitatively by leveraging ML. A multiobjective optimization problem is designed to consider the trade-off in program efficiency and disturbance. Pareto optimization facilitates determining PP shapes that achieve optimal solutions between maximizing program efficiency and minimizing program disturbance. The Pareto front provides practical and intuitive candidates for determining optimal PP shapes. Experimental results confirm that the program efficiency and disturbance can be enhanced by 14%–22% and 5%–40%, respectively. The ML-based Pareto optimization has the potential to vary the pulse conditions for desired operations in 3D-NAND flash, which is the biggest nonvolatile memory market in the semiconductor industry.
我们提出了一种结合机器学习（ML）和帕累托优化的新方法，可同时提高 3D-NAND 闪存的编程效率和干扰。由于程序脉冲（PP）形状繁多，阈值电压偏移与程序脉冲（PP）形状之间的关系从未被研究过。我们利用 ML 对这一复杂关系进行了快速定量建模。设计了一个多目标优化问题，以考虑程序效率和干扰之间的权衡。帕累托优化有助于确定 PP 形状，从而在最大化程序效率和最小化程序干扰之间找到最佳解决方案。帕累托前沿为确定最佳 PP 形状提供了实用而直观的候选方案。实验结果证实，程序效率和干扰可分别提高 14%-22% 和 5%-40% 。基于 ML 的帕累托优化有可能改变 3D-NAND 闪存中理想操作的脉冲条件，而 3D-NAND 闪存是半导体行业最大的非易失性存储器市场。
{"title":"Program Pulse Control for Program Efficiency and Disturbance of 3D-NAND Flash Using Novel Machine Learning-Based Pareto Optimization","authors":"Kihoon Nam;Donghyun Kim;Hyeok Yun;Chanyang Park;Hyundong Jang;Kyeongrae Cho;Seungjoon Eom;Jiyoon Kim;Seonhaeng Lee;Namhyun Lee;Gang-Jun Kim;Rock-Hyun Baek","doi":"10.1109/TED.2024.3469186","DOIUrl":"https://doi.org/10.1109/TED.2024.3469186","url":null,"abstract":"We propose a novel approach that combines machine learning (ML) and Pareto optimization to simultaneously enhance the program efficiency and disturbance of 3D-NAND flash memory. The relationship between program pulse (PP) shapes and threshold voltage shifts has never been investigated owing to the presence of numerous PP shapes. The complex relationship is modeled rapidly and quantitatively by leveraging ML. A multiobjective optimization problem is designed to consider the trade-off in program efficiency and disturbance. Pareto optimization facilitates determining PP shapes that achieve optimal solutions between maximizing program efficiency and minimizing program disturbance. The Pareto front provides practical and intuitive candidates for determining optimal PP shapes. Experimental results confirm that the program efficiency and disturbance can be enhanced by 14%–22% and 5%–40%, respectively. The ML-based Pareto optimization has the potential to vary the pulse conditions for desired operations in 3D-NAND flash, which is the biggest nonvolatile memory market in the semiconductor industry.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, the electrical performance and evolution of point defects in chip-level Silicon-based MOSFET under transmission line pulse (TLP) stress were investigated. The experimental results show that the threshold voltage decreased by 9.8%, and the output saturation current increased by 5.9% after the stress. An intrinsic point defect with an energy level of $0.25~pm ~0.05$ eV in Si-based MOSFET chips was observed by using deep-level transient spectroscopy (DLTS), which shifted to $0.37~pm ~0.05$ eV after the stress. The increase of the trap energy level would reduce the holes at the Si/SiO2 interface, and herein the threshold voltage reduced. This work helps to further understand the evolution of point defects in Si-based MOSFET chips.
{"title":"Evolution of Point Defects in Chip-Level Silicon-Based MOSFET Under Transmission Line Pulse Stress","authors":"Xinyuan Zheng;Huiying Li;Yibo Ning;Chengbing Pan;Kai Wang;Lixia Zhao","doi":"10.1109/TED.2024.3466840","DOIUrl":"https://doi.org/10.1109/TED.2024.3466840","url":null,"abstract":"In this study, the electrical performance and evolution of point defects in chip-level Silicon-based MOSFET under transmission line pulse (TLP) stress were investigated. The experimental results show that the threshold voltage decreased by 9.8%, and the output saturation current increased by 5.9% after the stress. An intrinsic point defect with an energy level of \u0000<inline-formula> <tex-math>$0.25~pm ~0.05$ </tex-math></inline-formula>\u0000 eV in Si-based MOSFET chips was observed by using deep-level transient spectroscopy (DLTS), which shifted to \u0000<inline-formula> <tex-math>$0.37~pm ~0.05$ </tex-math></inline-formula>\u0000 eV after the stress. The increase of the trap energy level would reduce the holes at the Si/SiO2 interface, and herein the threshold voltage reduced. This work helps to further understand the evolution of point defects in Si-based MOSFET chips.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The effect of an upstream steep down taper added onto an interaction circuit with a single smooth down taper is investigated. Explorations of the physical mechanism reveal a twofold effect: enhancement of efficiency due to better electron bunching, and a shift in the optimal interaction phase. With the adoption of an additional down taper, the optimal phase for the highest peak efficiency shifts from 0° to 180°, suggesting the potential of efficiency-enhanced double down-taper circuits. Based on the elucidated mechanism, a piecewise frequency-tunable gyrotron is proposed, where a series of TE $_{{0}{n}}$ modes tuning is expected to provide a wide tunable band across 320–480 GHz. This study contributes to the comprehension of reflective gyro-BWOs and facilitates further exploration of gyrotron oscillators toward the terahertz (THz) regime.
我们研究了在具有单一平滑向下锥度的相互作用电路上添加上游陡峭向下锥度的效果。对物理机制的探索揭示了双重效应：由于电子束化效果更好而提高了效率，以及最佳相互作用相位发生了变化。采用额外的向下锥度后，最高峰值效率的最佳相位从 0° 移动到 180°，这表明效率增强型双向下锥度电路具有潜力。基于阐明的机制，我们提出了一种片式频率可调陀螺仪，其中一系列 TE $_{{0}{n}}$ 模式调谐有望提供跨越 320-480 GHz 的宽可调频带。这项研究有助于理解反射式陀螺-BWOs，并促进对太赫兹（THz）陀螺振荡器的进一步探索。
{"title":"Theoretical Investigation on Down-Taper-Type Frequency-Tunable Reflective Gyro-BWO","authors":"Tien-Fu Yang;Chia-Chuan Chang;Hsin-Yu Yao;Tsun-Hsu Chang","doi":"10.1109/TED.2024.3468301","DOIUrl":"https://doi.org/10.1109/TED.2024.3468301","url":null,"abstract":"The effect of an upstream steep down taper added onto an interaction circuit with a single smooth down taper is investigated. Explorations of the physical mechanism reveal a twofold effect: enhancement of efficiency due to better electron bunching, and a shift in the optimal interaction phase. With the adoption of an additional down taper, the optimal phase for the highest peak efficiency shifts from 0° to 180°, suggesting the potential of efficiency-enhanced double down-taper circuits. Based on the elucidated mechanism, a piecewise frequency-tunable gyrotron is proposed, where a series of TE\u0000<inline-formula> <tex-math>$_{{0}{n}}$ </tex-math></inline-formula>\u0000 modes tuning is expected to provide a wide tunable band across 320–480 GHz. This study contributes to the comprehension of reflective gyro-BWOs and facilitates further exploration of gyrotron oscillators toward the terahertz (THz) regime.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/TED.2024.3469176
Ming Zhang;Xiao-Cui Ma;Heng-Yuan Zhang;Gang Yang;Hui Lin;Cai-Jun Zheng;Xiaoyang Du;Silu Tao
New electron-donating materials are crucial for developing efficient exciplex emitters and host matrices in simplified phosphorescent organic light-emitting diodes (PhOLEDs) with low driving voltage, high efficiency, and minimal efficiency roll-off. Herein, a spiro backbone with a highly sterically rigid structure and orthogonal configuration was attached to the commonly used 9H-carbazole (Cz) via para-linking, resulting in a new electron-donating material 9-(9, $9'$ -spirobi[fluoren]-2-yl)- 9H-Cz (SBF-Cz). The influence of the donor strength on the photophysical, electrochemical, and electroluminescent performances was studied. SBF-Cz exhibits a high T1 level, a shallow highest occupied molecular orbital (HOMO) level, and excellent thermal properties. Utilizing these properties, a simplified blue organic light-emitting diode (OLED) using SBF-Cz:2,4,6-Tris[3-(diphenylphosphinyl)phenyl]-1,3,5-triazine (PO-T2T) as the emitter achieves an EL emission peak at 476 nm and a maximum external quantum efficiency (EQEmax) of 11.2%. Furthermore, the spiro-type exciplex as a universal host was systematically investigated in blue, green, and red PhOLEDs. Notably, the EQEmax of blue, green, and red PhOLEDs using the spiro-type exciplex as host improved by 6.8%, 23.8%, and 11.1%, respectively, compared to the conventional host mCP. Additionally, the blue, green, and red PhOLEDs exhibit lower EQE roll-off of 8.7%, 8.1%, and 1.2% at a brightness of 1000 cd $cdot $ m-2 compared to the reference devices. This work underscores the significance of the spiro-type donor in developing new blue exciplexes and host matrices for OLEDs.
{"title":"Utilizing Spiro-Type Backbone Donor to Develop Exciplex Emitter and Highly Efficient Phosphorescent OLEDs With Low Efficiency Roll-Off","authors":"Ming Zhang;Xiao-Cui Ma;Heng-Yuan Zhang;Gang Yang;Hui Lin;Cai-Jun Zheng;Xiaoyang Du;Silu Tao","doi":"10.1109/TED.2024.3469176","DOIUrl":"https://doi.org/10.1109/TED.2024.3469176","url":null,"abstract":"New electron-donating materials are crucial for developing efficient exciplex emitters and host matrices in simplified phosphorescent organic light-emitting diodes (PhOLEDs) with low driving voltage, high efficiency, and minimal efficiency roll-off. Herein, a spiro backbone with a highly sterically rigid structure and orthogonal configuration was attached to the commonly used 9H-carbazole (Cz) via para-linking, resulting in a new electron-donating material 9-(9,\u0000<inline-formula> <tex-math>$9'$ </tex-math></inline-formula>\u0000-spirobi[fluoren]-2-yl)- 9H-Cz (SBF-Cz). The influence of the donor strength on the photophysical, electrochemical, and electroluminescent performances was studied. SBF-Cz exhibits a high T1 level, a shallow highest occupied molecular orbital (HOMO) level, and excellent thermal properties. Utilizing these properties, a simplified blue organic light-emitting diode (OLED) using SBF-Cz:2,4,6-Tris[3-(diphenylphosphinyl)phenyl]-1,3,5-triazine (PO-T2T) as the emitter achieves an EL emission peak at 476 nm and a maximum external quantum efficiency (EQEmax) of 11.2%. Furthermore, the spiro-type exciplex as a universal host was systematically investigated in blue, green, and red PhOLEDs. Notably, the EQEmax of blue, green, and red PhOLEDs using the spiro-type exciplex as host improved by 6.8%, 23.8%, and 11.1%, respectively, compared to the conventional host mCP. Additionally, the blue, green, and red PhOLEDs exhibit lower EQE roll-off of 8.7%, 8.1%, and 1.2% at a brightness of 1000 cd\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000m-2 compared to the reference devices. This work underscores the significance of the spiro-type donor in developing new blue exciplexes and host matrices for OLEDs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/TED.2024.3466836
Tianxing Hu;Min Li;Hua Xu;Hong Tao;Jianhua Zou;Junhong Zhou;Miao Xu;Junbiao Peng;Lei Wang
Titanium-doped InZnO (TiIZO) thin-film transistors (TFTs) with different doping concentrations were successfully fabricated using plasma-enhanced atomic layer deposition (PEALD). Specifically, TiIZO TFTs with Ti cation doping concentration of 0.5% using tetra (dimethylamino) titanium (TDMATi) exhibited a high field-effect mobility of 51.22 cm2/Vs and a small subthreshold swing (SS) of 0.24 V/decade. Furthermore, compared to undoped IZO TFTs, TiIZO TFTs exhibited enhanced bias stability under positive and negative temperature bias stress. This improvement is attributed to the appropriate Ti doping concentration, which suppresses impurity oxygen defects, reduces the trap density at the insulator/channel interface, and introduces additional charge carriers.
{"title":"A Novel Strategy to Achieve High-Performance Titanium-Doped InZnO Thin-Film Transistors Using Atomic Layer Deposition","authors":"Tianxing Hu;Min Li;Hua Xu;Hong Tao;Jianhua Zou;Junhong Zhou;Miao Xu;Junbiao Peng;Lei Wang","doi":"10.1109/TED.2024.3466836","DOIUrl":"https://doi.org/10.1109/TED.2024.3466836","url":null,"abstract":"Titanium-doped InZnO (TiIZO) thin-film transistors (TFTs) with different doping concentrations were successfully fabricated using plasma-enhanced atomic layer deposition (PEALD). Specifically, TiIZO TFTs with Ti cation doping concentration of 0.5% using tetra (dimethylamino) titanium (TDMATi) exhibited a high field-effect mobility of 51.22 cm2/Vs and a small subthreshold swing (SS) of 0.24 V/decade. Furthermore, compared to undoped IZO TFTs, TiIZO TFTs exhibited enhanced bias stability under positive and negative temperature bias stress. This improvement is attributed to the appropriate Ti doping concentration, which suppresses impurity oxygen defects, reduces the trap density at the insulator/channel interface, and introduces additional charge carriers.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/TED.2024.3469171
Sanguk Lee;Jinsu Jeong;Rock-Hyun Baek
This study examined the electrical and thermal behaviors of nanosheet (NS) field-effect transistors (NSFETs) with trimmed channels using a technology computer-aided design (TCAD) simulation. NSFETs are expected to exhibit excellent electrical behaviors owing to thin gate-all-around (GAA) channels. However, NSFETs still suffer from: 1) high punchthrough current ( ${I}_{text {PTS}}$ ) in the punchthrough stopper (PTS) region and 2) poor heat dissipation by the thin channel thickness. Thus, to resolve these problems, this study proposed NSFETs with trimmed NS channels and a trench gate in the PTS region. This structure can be formed via the deposition of thick silicon layers during Si/SiGe stacking and consequently trimming the silicon regions (NS channels, PTS region) following the channel release. Consequently, the trench gate strengthened the gate controllability for the PTS region, exhibiting remarkable ${I}_{text {PTS}}$ suppression. In addition, untrimmed thick channel ends improved heat transfer, whereas the trimmed channel centers provided excellent gate controllability. Therefore, the trimming process, which formed trimmed channels and a trench gate, is expected to simultaneously solve the inherent electrical and thermal issues encountered in NSFETs.
{"title":"Channel Trimming Process to Improve Electro-Thermal Characteristics for Sub-3-nm Node Si Nanosheet FETs","authors":"Sanguk Lee;Jinsu Jeong;Rock-Hyun Baek","doi":"10.1109/TED.2024.3469171","DOIUrl":"https://doi.org/10.1109/TED.2024.3469171","url":null,"abstract":"This study examined the electrical and thermal behaviors of nanosheet (NS) field-effect transistors (NSFETs) with trimmed channels using a technology computer-aided design (TCAD) simulation. NSFETs are expected to exhibit excellent electrical behaviors owing to thin gate-all-around (GAA) channels. However, NSFETs still suffer from: 1) high punchthrough current (\u0000<inline-formula> <tex-math>${I}_{text {PTS}}$ </tex-math></inline-formula>\u0000) in the punchthrough stopper (PTS) region and 2) poor heat dissipation by the thin channel thickness. Thus, to resolve these problems, this study proposed NSFETs with trimmed NS channels and a trench gate in the PTS region. This structure can be formed via the deposition of thick silicon layers during Si/SiGe stacking and consequently trimming the silicon regions (NS channels, PTS region) following the channel release. Consequently, the trench gate strengthened the gate controllability for the PTS region, exhibiting remarkable \u0000<inline-formula> <tex-math>${I}_{text {PTS}}$ </tex-math></inline-formula>\u0000 suppression. In addition, untrimmed thick channel ends improved heat transfer, whereas the trimmed channel centers provided excellent gate controllability. Therefore, the trimming process, which formed trimmed channels and a trench gate, is expected to simultaneously solve the inherent electrical and thermal issues encountered in NSFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/TED.2024.3468289
Yongzhou Wang;Xiao Huang;Hui Xu;Rongrong Cao;Yi Sun;Peiwen Tong;Bing Song;Wei Wang;Qingjiang Li
Threshold switching (TS) memristor with a simple structure and high biomimetic offers a more promising way to implement an efficient artificial neuron than traditional methods. To accommodate the complex environments in practical applications, previous memristor-based neurons typically incorporate auxiliary circuits to ensure tunability within circuits. However, this addition not only heightens the design complexity but also reduces the efficiency. In this work, we investigate the conduction process under different thresholds in an NbOx-based memristor and further demonstrate its potential merits in human face recognition. The negative threshold voltage of the device can be linearly modulated by positive stimuli. The conduction mechanisms under different threshold states are systematically investigated by experiments and theoretical analysis, showing that the defects concentration controlled by the electrical field is attributed to the threshold modulation. The revealed mechanism is instructive for device optimization, offering an oxygen-related fabrication method. Based on such a device, we construct a tunable spiking neuron whose threshold can be modulated by only one preoperation on the neuron without other burdensome units. By modulating the threshold based on the light intensities—a lower threshold for the bright condition and a higher threshold for the dark condition—the temporal features of the neuron outputs can be maintained at a normal condition to ensure the correct recognition under different environmental luminance. The function of the proposed tunable neuron is further evaluated in a network for human face recognition. The network finally reaches a 93.25% accuracy with tunable threshold neurons, significantly surpassing the 71.87% with fixed-threshold neurons.
{"title":"Investigation of the Modulated Threshold Memristor for Tunable Artificial Neuron","authors":"Yongzhou Wang;Xiao Huang;Hui Xu;Rongrong Cao;Yi Sun;Peiwen Tong;Bing Song;Wei Wang;Qingjiang Li","doi":"10.1109/TED.2024.3468289","DOIUrl":"https://doi.org/10.1109/TED.2024.3468289","url":null,"abstract":"Threshold switching (TS) memristor with a simple structure and high biomimetic offers a more promising way to implement an efficient artificial neuron than traditional methods. To accommodate the complex environments in practical applications, previous memristor-based neurons typically incorporate auxiliary circuits to ensure tunability within circuits. However, this addition not only heightens the design complexity but also reduces the efficiency. In this work, we investigate the conduction process under different thresholds in an NbOx-based memristor and further demonstrate its potential merits in human face recognition. The negative threshold voltage of the device can be linearly modulated by positive stimuli. The conduction mechanisms under different threshold states are systematically investigated by experiments and theoretical analysis, showing that the defects concentration controlled by the electrical field is attributed to the threshold modulation. The revealed mechanism is instructive for device optimization, offering an oxygen-related fabrication method. Based on such a device, we construct a tunable spiking neuron whose threshold can be modulated by only one preoperation on the neuron without other burdensome units. By modulating the threshold based on the light intensities—a lower threshold for the bright condition and a higher threshold for the dark condition—the temporal features of the neuron outputs can be maintained at a normal condition to ensure the correct recognition under different environmental luminance. The function of the proposed tunable neuron is further evaluated in a network for human face recognition. The network finally reaches a 93.25% accuracy with tunable threshold neurons, significantly surpassing the 71.87% with fixed-threshold neurons.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-04DOI: 10.1109/TED.2024.3467029
Xinkang Chen;Sumeet Kumar Gupta
In Part I of this work, we had presented a spatially resolved model for conductivity of interconnects capturing surface scattering based on the well-known Fuchs-Sondheimer (FS) approach. However, the proposed spatially resolved FS (SRFS) model involves computing complicated integrals making it ill-suited for circuit simulations. In this part, we build upon our SRFS model to develop a circuit-compatible conductivity model for rectangular interconnects accounting for 2-D surface scattering. The proposed circuit-compatible model offers spatial resolution of conductivity as well as explicit dependence on the physical parameters such as electron mean free path ( $lambda _{{0}}$ ), specularity (p), and interconnect geometry. We validate our circuit-compatible model over a range of physical parameters showing a close match with the physical SRFS model proposed in Part I (with error <0.7%). We also compare our circuit-compatible model with a previous spatially resolved analytical model (appropriately modified for a fair comparison) and show that our model captures the spatial resolution of conductivity and the dependence on physical parameters more accurately. Finally, we present a semi-analytical equation for the average conductivity based on our circuit-compatible model.
{"title":"Spatially Resolved Conductivity of Rectangular Interconnects Considering Surface Scattering—Part II: Circuit-Compatible Modeling","authors":"Xinkang Chen;Sumeet Kumar Gupta","doi":"10.1109/TED.2024.3467029","DOIUrl":"https://doi.org/10.1109/TED.2024.3467029","url":null,"abstract":"In Part I of this work, we had presented a spatially resolved model for conductivity of interconnects capturing surface scattering based on the well-known Fuchs-Sondheimer (FS) approach. However, the proposed spatially resolved FS (SRFS) model involves computing complicated integrals making it ill-suited for circuit simulations. In this part, we build upon our SRFS model to develop a circuit-compatible conductivity model for rectangular interconnects accounting for 2-D surface scattering. The proposed circuit-compatible model offers spatial resolution of conductivity as well as explicit dependence on the physical parameters such as electron mean free path (\u0000<inline-formula> <tex-math>$lambda _{{0}}$ </tex-math></inline-formula>\u0000), specularity (p), and interconnect geometry. We validate our circuit-compatible model over a range of physical parameters showing a close match with the physical SRFS model proposed in Part I (with error <0.7%). We also compare our circuit-compatible model with a previous spatially resolved analytical model (appropriately modified for a fair comparison) and show that our model captures the spatial resolution of conductivity and the dependence on physical parameters more accurately. Finally, we present a semi-analytical equation for the average conductivity based on our circuit-compatible model.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study investigates the issue of reducing band-to-band leakage current in low-voltage (LV) CMOS devices realized using BCD technology. Through TCAD simulations and comprehensive experimental characterization, the influence of key process parameters on leakage current in this category of devices is examined. The presented findings suggest that band-to-band tunneling (B2B) can be significantly mitigated by carefully selecting the rapid thermal processing (RTP) annealing temperature. Subsequently, we address the side effects of the modification of the process parameter on the electrical performance of the devices, aiming to recover affected electrical figures of merit through precise adjustments to the process working point. The study shows that this goal can be reached by a proper modification of the p+ implant energy. In the end, a statistical analysis is presented, with the purpose of understanding the impact of these process changes on the distribution of defects. This research not only proposes a method to tackle the well-known issue of B2B current but also provides valuable insight into the steps required to achieve substantial enhancements in the electrical performance of components by fine-tuning BCD process parameters.
{"title":"Manipulating Band-to-Band Tunneling Current in Low-Voltage pMOS Devices in BCD Technology: A TCAD and Experimental Investigation","authors":"Guglielmo Albani;Elena Rebussi;Emanuele D’Ambrosio;Annalisa Gilardini;Alessandra Manca;Pietro Miccichè;Daria Doria;Pierpaolo Monge;Elia Sora;Silvia Vangelista;Emanuele Viganò","doi":"10.1109/TED.2024.3466842","DOIUrl":"https://doi.org/10.1109/TED.2024.3466842","url":null,"abstract":"This study investigates the issue of reducing band-to-band leakage current in low-voltage (LV) CMOS devices realized using BCD technology. Through TCAD simulations and comprehensive experimental characterization, the influence of key process parameters on leakage current in this category of devices is examined. The presented findings suggest that band-to-band tunneling (B2B) can be significantly mitigated by carefully selecting the rapid thermal processing (RTP) annealing temperature. Subsequently, we address the side effects of the modification of the process parameter on the electrical performance of the devices, aiming to recover affected electrical figures of merit through precise adjustments to the process working point. The study shows that this goal can be reached by a proper modification of the p+ implant energy. In the end, a statistical analysis is presented, with the purpose of understanding the impact of these process changes on the distribution of defects. This research not only proposes a method to tackle the well-known issue of B2B current but also provides valuable insight into the steps required to achieve substantial enhancements in the electrical performance of components by fine-tuning BCD process parameters.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study discusses the application of the substrate voltage during the recovery time with the dynamic on-resistance (dynamic ${R}_{text {on}}$ ) method to extract the deep trap states in the buffer layer after the hard-switching stress in p-GaN high electron mobility transistors (p-GaN HEMTs). This method will be more suitable for the detection of the deep trap states where the carriers are difficult to de-trap in the buffer layer. Then, a hard switching stress condition is applied to the device and the degradation is caused by the mechanism of the hot electron effect and the impact ionization. The generated electrons and holes will trap into the buffer layer in the drift region at the gate edge near the drain side and the AlGaN layer under the gate, respectively. Moreover, through the novel of the dynamic ${R}_{text {on}}$ method with the substrate voltage applied, the deep trap states in the buffer can be extracted.
{"title":"An Approach to Extract the Trap States via the Dynamic Ron Method With Substrate Voltage Applied During the Recovery Time","authors":"Ya-Huan Lee;Po-Hsun Chen;Yong-Ci Zhang;Chung-Wei Wu;Sheng-Yao Chou;Yu-Bo Wang;Hung-Ming Kuo;Yu-Shan Lin;Yan-Ta Chen;Yu-Jie Tsai;Ting-Chang Chang","doi":"10.1109/TED.2024.3467038","DOIUrl":"https://doi.org/10.1109/TED.2024.3467038","url":null,"abstract":"This study discusses the application of the substrate voltage during the recovery time with the dynamic on-resistance (dynamic \u0000<inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula>\u0000) method to extract the deep trap states in the buffer layer after the hard-switching stress in p-GaN high electron mobility transistors (p-GaN HEMTs). This method will be more suitable for the detection of the deep trap states where the carriers are difficult to de-trap in the buffer layer. Then, a hard switching stress condition is applied to the device and the degradation is caused by the mechanism of the hot electron effect and the impact ionization. The generated electrons and holes will trap into the buffer layer in the drift region at the gate edge near the drain side and the AlGaN layer under the gate, respectively. Moreover, through the novel of the dynamic \u0000<inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula>\u0000 method with the substrate voltage applied, the deep trap states in the buffer can be extracted.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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