Pub Date : 2025-11-10DOI: 10.1109/TED.2025.3606893
Chao Wang;Junfeng Hu;Ziyu Liu;Xiaojin Li;Yanling Shi;Yabin Sun
{"title":"Corrections to “TCAD Simulations of Reconfigurable Field-Effect Transistor With Embedded-Fin-Contact to Improve On-Current”","authors":"Chao Wang;Junfeng Hu;Ziyu Liu;Xiaojin Li;Yanling Shi;Yabin Sun","doi":"10.1109/TED.2025.3606893","DOIUrl":"https://doi.org/10.1109/TED.2025.3606893","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6396-6396"},"PeriodicalIF":3.2,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11236985","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-10DOI: 10.1109/TED.2025.3619313
{"title":"IEEE Transactions on Electron Devices Information for Authors","authors":"","doi":"10.1109/TED.2025.3619313","DOIUrl":"https://doi.org/10.1109/TED.2025.3619313","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"C3-C3"},"PeriodicalIF":3.2,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11237001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-10DOI: 10.1109/TED.2025.3619311
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/TED.2025.3619311","DOIUrl":"https://doi.org/10.1109/TED.2025.3619311","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6397-6398"},"PeriodicalIF":3.2,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11237003","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A comprehensive electrical characterization of a p-n diode constructed from a Te/n-Si heterostructure was presented in this work. Fabricated using CMOS-compatible RF sputtering, the device exhibited a typical diode behavior. Key electrical parameters including the ideality factor, series resistance, built-in potential, and interface state density were precisely extracted from temperature-dependent current–voltage measurements and capacitance–voltage analyses. The ideality factor decreased with increasing temperature, attributed to interface states and barrier inhomogeneities, while the decrease in series resistance with increasing temperature was a result of improved semiconductor conductivity due to increased intrinsic carrier concentration, reduced contact resistance at interfaces, and enhanced conduction through activated trap states. The reverse-bias current was dominated primarily by a thermal generation mechanism rather than by diffusion. Notably, the Te/n-Si diode demonstrated promising temperature sensing capabilities with a high sensitivity.
{"title":"In-Depth Electrical Characterization of Carrier Transport in Tellurium/Silicon Heterojunction-Based p-n Diode","authors":"Yohan Kim;Gyuri Lim;Byeongjin Park;Jongwon Yoon;Yonghun Kim;Dae-Young Jeon","doi":"10.1109/TED.2025.3626337","DOIUrl":"https://doi.org/10.1109/TED.2025.3626337","url":null,"abstract":"A comprehensive electrical characterization of a p-n diode constructed from a Te/n-Si heterostructure was presented in this work. Fabricated using CMOS-compatible RF sputtering, the device exhibited a typical diode behavior. Key electrical parameters including the ideality factor, series resistance, built-in potential, and interface state density were precisely extracted from temperature-dependent current–voltage measurements and capacitance–voltage analyses. The ideality factor decreased with increasing temperature, attributed to interface states and barrier inhomogeneities, while the decrease in series resistance with increasing temperature was a result of improved semiconductor conductivity due to increased intrinsic carrier concentration, reduced contact resistance at interfaces, and enhanced conduction through activated trap states. The reverse-bias current was dominated primarily by a thermal generation mechanism rather than by diffusion. Notably, the Te/n-Si diode demonstrated promising temperature sensing capabilities with a high sensitivity.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7108-7113"},"PeriodicalIF":3.2,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-03DOI: 10.1109/TED.2025.3623957
Xinkang Chen;Sumeet Kumar Gupta
In the article referenced below [1], the following errors and their corrections should be noted. The derivations, results, and analyses in [1] use the correct equations, and therefore, these errors do not impact the other content in [1]. 1)In (3), the term $(v_{z}/v)$ in the integrand should be replaced by $(v_{z}^{2}/v)$ .2)In (5), there should be no negative sign before $(2q^{2}m_{mathrm {eff}}^{2}/h^{3})$ .3) In (6), (7), (13), and (16), the prefactor on the right-hand side multiplied with $sigma _{0}$ should be $3/(4pi)$ (instead of $3/4)$ . Similarly, in the equation for $(sigma _{mathrm {SRFS}}(y_{n})/sigma _{0})$ in (18), the prefactor on the right-hand side multiplied by the integral with respect to $theta $ should be $3/(4pi)$ (instead of $3/4)$ .
{"title":"Erratum to “Spatially Resolved Conductivity of Rectangular Interconnects Considering Surface Scattering—Part I: Physical Modeling”","authors":"Xinkang Chen;Sumeet Kumar Gupta","doi":"10.1109/TED.2025.3623957","DOIUrl":"https://doi.org/10.1109/TED.2025.3623957","url":null,"abstract":"In the article referenced below [1], the following errors and their corrections should be noted. The derivations, results, and analyses in [1] use the correct equations, and therefore, these errors do not impact the other content in [1]. 1)In (3), the term $(v_{z}/v)$ in the integrand should be replaced by $(v_{z}^{2}/v)$ .2)In (5), there should be no negative sign before $(2q^{2}m_{mathrm {eff}}^{2}/h^{3})$ .3) In (6), (7), (13), and (16), the prefactor on the right-hand side multiplied with $sigma _{0}$ should be $3/(4pi)$ (instead of $3/4)$ . Similarly, in the equation for $(sigma _{mathrm {SRFS}}(y_{n})/sigma _{0})$ in (18), the prefactor on the right-hand side multiplied by the integral with respect to $theta $ should be $3/(4pi)$ (instead of $3/4)$ .","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7190-7190"},"PeriodicalIF":3.2,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11224734","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-03DOI: 10.1109/TED.2025.3623949
Xinkang Chen;Sumeet Kumar Gupta
In [1], the following error and its correction should be noted. The derivations, results, and analyses in [1] use the correct equations, and thus, this error does not impact the other content in [1].
{"title":"Erratum to “Spatially Resolved Conductivity of Rectangular Interconnects Considering Surface Scattering—Part II: Circuit-Compatible Modeling”","authors":"Xinkang Chen;Sumeet Kumar Gupta","doi":"10.1109/TED.2025.3623949","DOIUrl":"https://doi.org/10.1109/TED.2025.3623949","url":null,"abstract":"In [1], the following error and its correction should be noted. The derivations, results, and analyses in [1] use the correct equations, and thus, this error does not impact the other content in [1].","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7191-7191"},"PeriodicalIF":3.2,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11224364","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cryogenic CMOS technology is crucial for high-performance and quantum computing, but faces significant reliability challenges from exacerbated hot carrier degradation (HCD) at ultralow temperatures. In addition, cryogenic HCD (cryo-HCD) is further complicated by the coupling of cryogenic-specific phenomena, such as band tail states. In this work, a change temperature measure-stress-measure (MSM) method is established based on FinFET, which can separate the cryo-HCD from the effects of band tail states. It is found that additional Vth shifts under cryo-HCD in pFinFET at 10 K. The physical mechanism is revealed by advanced atomic-scale characterization [transmission electron microscope (TEM)/energy-dispersive X-ray spectroscopy (EDS)/electron energy-loss spectroscopy (EELS)], which identifies directional Ge migration from Si${}_{{1}-{x}}$ Gex (SiGe) drain regions into the channel as the origin. Combined with ab initio calculations, we establish that this Ge migration suppresses band tail states, directly inducing the anomalous ${V} _{text {th}}$ shift. These findings offer fundamental insights into cryogenic degradation mechanisms, underscoring the crucial role of atomic-scale material transport, which is essential for cryogenic reliability.
{"title":"Investigation on Cryogenic Reliability in FinFETs Under Hot Carrier Stress","authors":"Zuoyuan Dong;Zirui Wang;Hongbo Wang;Xiaomei Li;Chen Luo;Jialu Huang;Lan Li;Zepeng Huang;Zixuan Sun;Yue-Yang Liu;Xing Wu;Runsheng Wang","doi":"10.1109/TED.2025.3623950","DOIUrl":"https://doi.org/10.1109/TED.2025.3623950","url":null,"abstract":"Cryogenic CMOS technology is crucial for high-performance and quantum computing, but faces significant reliability challenges from exacerbated hot carrier degradation (HCD) at ultralow temperatures. In addition, cryogenic HCD (cryo-HCD) is further complicated by the coupling of cryogenic-specific phenomena, such as band tail states. In this work, a change temperature measure-stress-measure (MSM) method is established based on FinFET, which can separate the cryo-HCD from the effects of band tail states. It is found that additional <italic>V</i><sub>th</sub> shifts under cryo-HCD in pFinFET at 10 K. The physical mechanism is revealed by advanced atomic-scale characterization [transmission electron microscope (TEM)/energy-dispersive X-ray spectroscopy (EDS)/electron energy-loss spectroscopy (EELS)], which identifies directional Ge migration from Si<inline-formula> <tex-math>${}_{{1}-{x}}$ </tex-math></inline-formula>Ge<italic><sub>x</sub></i> (SiGe) drain regions into the channel as the origin. Combined with <italic>ab initio</i> calculations, we establish that this Ge migration suppresses band tail states, directly inducing the anomalous <inline-formula> <tex-math>${V} _{text {th}}$ </tex-math></inline-formula> shift. These findings offer fundamental insights into cryogenic degradation mechanisms, underscoring the crucial role of atomic-scale material transport, which is essential for cryogenic reliability.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7153-7160"},"PeriodicalIF":3.2,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-24DOI: 10.1109/TED.2025.3616087
Fabia Farlin Athena;Jimin Kang;Matthias Passlack;Nathaniel Safron;Didem Dede;Koustav Jana;Balreen Saini;Xinxin Wang;Shuhan Liu;Jonathan Hartanto;Ethan Boneh;Hugo J.-Y. Chen;Chi-Hsin Huang;Qing Lin;Donglai Zhong;Kaitlyn Leitherer;Paul C. McIntyre;Gregory Pitner;Iuliana P. Radu;H.-S. Philip Wong
We demonstrate that inserting an ultrathin (<1> $mathrm {Al_{2}O_{3}}$ layer between an oxide–semiconductor (OS) channel and a high-$kappa $ gate dielectric creates an interface dipole (ID) that shifts the threshold voltage ($textit {V} {_{text {T}}}$ ) of OS transistors. The ID engineering process by $mathrm {Al_{2}O_{3}}$ layer integration raises $textit {V} {_{text {T}}}$ of 2% W-doped indium tungsten oxide (IWO) FETs by ~450 mV relative to a reference $mathrm {HfO_{2}}$ stack, enabling normally-OFF operation with negligible degradation in mobility or subthreshold swing (SS). The $textit {V} {_{text {T}}}$ shift remains stable from 85 °C down to cryogenic temperatures. Under a worst case + 2-V positive bias stress at 85 °C, ID-engineered oxide–semiconductor field-effect transistors (OSFETs) exhibit a ~60-mV shift versus ~300 mV for the baseline device. The technique is effective across multiple OS channels [$mathrm {In_{2}O_{3}}$ , indium–tin oxide (ITO) and indium–gallium–zinc oxide (IGZO)] and gate lengths down to ~50 nm. Simulations calibrated to the measured devices show that the leakage reduction afforded by ID engineering decreases refresh energy of two transistor gain cell (2T-GC) arrays by $sim {5}times {10} ^{{4}} times $ , establishing ID engineering as a low thermal budget knob for energy-efficient, high-density GC memories.
我们证明了在氧化物半导体（OS）通道和高$kappa $栅极电介质之间插入超薄（$mathrm {Al_{2}O_{3}}$层）可以产生界面偶极子（ID），从而移动OS晶体管的阈值电压（$textit {V} {_{text {T}}}$）。ID工程过程由$mathrm {Al_{2}O_{3}}$层集成提出$textit {V} {_{text {T}}}$的2个% W-doped indium tungsten oxide (IWO) FETs by ~450 mV relative to a reference $mathrm {HfO_{2}}$ stack, enabling normally-OFF operation with negligible degradation in mobility or subthreshold swing (SS). The $textit {V} {_{text {T}}}$ shift remains stable from 85 °C down to cryogenic temperatures. Under a worst case + 2-V positive bias stress at 85 °C, ID-engineered oxide–semiconductor field-effect transistors (OSFETs) exhibit a ~60-mV shift versus ~300 mV for the baseline device. The technique is effective across multiple OS channels [ $mathrm {In_{2}O_{3}}$ , indium–tin oxide (ITO) and indium–gallium–zinc oxide (IGZO)] and gate lengths down to ~50 nm. Simulations calibrated to the measured devices show that the leakage reduction afforded by ID engineering decreases refresh energy of two transistor gain cell (2T-GC) arrays by $sim {5}times {10} ^{{4}} times $ , establishing ID engineering as a low thermal budget knob for energy-efficient, high-density GC memories.
{"title":"Multi-VT in Oxide--Semiconductor Transistors Leveraging Sub-1-nm Dipoles for Low-Refresh Energy Gain Cell Memory","authors":"Fabia Farlin Athena;Jimin Kang;Matthias Passlack;Nathaniel Safron;Didem Dede;Koustav Jana;Balreen Saini;Xinxin Wang;Shuhan Liu;Jonathan Hartanto;Ethan Boneh;Hugo J.-Y. Chen;Chi-Hsin Huang;Qing Lin;Donglai Zhong;Kaitlyn Leitherer;Paul C. McIntyre;Gregory Pitner;Iuliana P. Radu;H.-S. Philip Wong","doi":"10.1109/TED.2025.3616087","DOIUrl":"https://doi.org/10.1109/TED.2025.3616087","url":null,"abstract":"We demonstrate that inserting an ultrathin (<1> <tex-math>$mathrm {Al_{2}O_{3}}$ </tex-math></inline-formula> layer between an oxide–semiconductor (OS) channel and a high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> gate dielectric creates an interface dipole (ID) that shifts the threshold voltage (<inline-formula> <tex-math>$textit {V} {_{text {T}}}$ </tex-math></inline-formula>) of OS transistors. The ID engineering process by <inline-formula> <tex-math>$mathrm {Al_{2}O_{3}}$ </tex-math></inline-formula> layer integration raises <inline-formula> <tex-math>$textit {V} {_{text {T}}}$ </tex-math></inline-formula> of 2% W-doped indium tungsten oxide (IWO) FETs by ~450 mV relative to a reference <inline-formula> <tex-math>$mathrm {HfO_{2}}$ </tex-math></inline-formula> stack, enabling normally-OFF operation with negligible degradation in mobility or subthreshold swing (SS). The <inline-formula> <tex-math>$textit {V} {_{text {T}}}$ </tex-math></inline-formula> shift remains stable from 85 °C down to cryogenic temperatures. Under a worst case + 2-V positive bias stress at 85 °C, ID-engineered oxide–semiconductor field-effect transistors (OSFETs) exhibit a ~60-mV shift versus ~300 mV for the baseline device. The technique is effective across multiple OS channels [<inline-formula> <tex-math>$mathrm {In_{2}O_{3}}$ </tex-math></inline-formula>, indium–tin oxide (ITO) and indium–gallium–zinc oxide (IGZO)] and gate lengths down to ~50 nm. Simulations calibrated to the measured devices show that the leakage reduction afforded by ID engineering decreases refresh energy of two transistor gain cell (2T-GC) arrays by <inline-formula> <tex-math>$sim {5}times {10} ^{{4}} times $ </tex-math></inline-formula>, establishing ID engineering as a low thermal budget knob for energy-efficient, high-density GC memories.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7161-7166"},"PeriodicalIF":3.2,"publicationDate":"2025-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-14DOI: 10.1109/TED.2025.3613466
Dasom Lee;Tsu-Jae King Liu
Relevant to the cryogenic operation of CMOS integrated circuits, random telegraph noise (RTN) temperature dependence was investigated using FinFET devices fabricated using Samsung’s 14-nm process technology. Transistor drive current degradation due to trapped charge in the gate oxide is experimentally observed to worsen with decreasing temperature. A newfound dependence of trap capture and emission rates on drain voltage is observed and explained. Technology computer-aided design (TCAD) simulations using models calibrated to the measured data are then performed to investigate trends in RTN temperature dependence with transistor scaling (3-nm FinFET) and evolution [2-nm gate-all-around field-effect transistor (GAAFET)].
{"title":"Study of Defect-Induced Noise in Advanced MOSFETs for Cryogenic Operation","authors":"Dasom Lee;Tsu-Jae King Liu","doi":"10.1109/TED.2025.3613466","DOIUrl":"https://doi.org/10.1109/TED.2025.3613466","url":null,"abstract":"Relevant to the cryogenic operation of CMOS integrated circuits, random telegraph noise (RTN) temperature dependence was investigated using FinFET devices fabricated using Samsung’s 14-nm process technology. Transistor drive current degradation due to trapped charge in the gate oxide is experimentally observed to worsen with decreasing temperature. A newfound dependence of trap capture and emission rates on drain voltage is observed and explained. Technology computer-aided design (TCAD) simulations using models calibrated to the measured data are then performed to investigate trends in RTN temperature dependence with transistor scaling (3-nm FinFET) and evolution [2-nm gate-all-around field-effect transistor (GAAFET)].","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6379-6382"},"PeriodicalIF":3.2,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The switching efficiency of conventional silicon-based field-effect transistors (FETs) is fundamentally constrained by their 60-mV/dec subthreshold swing (SS) lower bound. Recently, we proposed an Al-drain FET to overcome this limitation. In this work, we further design and experimentally demonstrate dual types of (p/n) silicon transistors featuring various metal-drain (MD) structure MD field effect transistor (MDFET). Particularly, Al and Ti are selected for n-type MDFET, while Pt is adapted for p-type MDFET based on their work function. Measurement results show that both n-type and p-type MDFETs achieve ultrasteep average SS ($ll$ 10 mV/dec) over multiple decades of current. In addition, TCAD simulations have been performed, and the simulation results agree well with experimental data qualitatively. Detailed analysis reveals that the Schottky junction at the metal–silicon drain interface induces a localized electric field amplification ($gt 1.66times $ compared to conventional doped silicon drain) and extends the depletion region, synergistically enhancing impact ionization (II) of carriers. This mechanism establishes a regenerative feedback loop, enabling ultrasteep switching behavior. Finally, a compact model of MDFET is created for circuit simulation, and an inverter circuit composed of pMOS and n-type MDFET is constructed experimentally. Both measured data and model simulation agree well, illustrating the potential of MDFET for CMOS-compatible low-power logic applications.
{"title":"Ultrasteep Subthreshold Slope Metal-Drain Dual-Type (p/n) Silicon Transistors: Characterization, Analysis, and Application","authors":"Zhibo Chen;Baowei Yuan;Haobo Huang;Weiao Chen;Biyu Guo;Chengjie Tang;Yingxin Chen;Weizhuo Gan;Chunsong Zhao;Zhaozhao Hou;Qiang Zhang;Jiachen Gao;Jiale Wang;Jeffrey Xu;Guangxi Hu;Jing Wan;Ye Lu","doi":"10.1109/TED.2025.3612318","DOIUrl":"https://doi.org/10.1109/TED.2025.3612318","url":null,"abstract":"The switching efficiency of conventional silicon-based field-effect transistors (FETs) is fundamentally constrained by their 60-mV/dec subthreshold swing (SS) lower bound. Recently, we proposed an Al-drain FET to overcome this limitation. In this work, we further design and experimentally demonstrate dual types of (p/n) silicon transistors featuring various metal-drain (MD) structure MD field effect transistor (MDFET). Particularly, Al and Ti are selected for n-type MDFET, while Pt is adapted for p-type MDFET based on their work function. Measurement results show that both n-type and p-type MDFETs achieve ultrasteep average SS (<inline-formula> <tex-math>$ll$ </tex-math></inline-formula> 10 mV/dec) over multiple decades of current. In addition, TCAD simulations have been performed, and the simulation results agree well with experimental data qualitatively. Detailed analysis reveals that the Schottky junction at the metal–silicon drain interface induces a localized electric field amplification (<inline-formula> <tex-math>$gt 1.66times $ </tex-math></inline-formula> compared to conventional doped silicon drain) and extends the depletion region, synergistically enhancing impact ionization (II) of carriers. This mechanism establishes a regenerative feedback loop, enabling ultrasteep switching behavior. Finally, a compact model of MDFET is created for circuit simulation, and an inverter circuit composed of pMOS and n-type MDFET is constructed experimentally. Both measured data and model simulation agree well, illustrating the potential of MDFET for CMOS-compatible low-power logic applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6355-6360"},"PeriodicalIF":3.2,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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