Synaptic transistors are fabricated using chitosan as the gate dielectric and CuI with sputtered ITO as the channel. Surface charge-transfer doping from the ITO enhanced the performance and operational stability of the devices. Meanwhile, the application of voltage pulses enables the devices to emulate synaptic characteristics, including excitatory postsynaptic currents (EPSCs), inhibitory postsynaptic currents (IPSCs), paired-pulse facilitation (PPF), short-term plasticity (STP), and spike-frequency-dependent plasticity (SFDP). Furthermore, the transistors exhibit the capacity to modulate synaptic weights bidirectionally by realizing both long-term potentiation (LTP) and long-term depression (LTD), with good repeatability. The biomimetic synaptic properties of the devices enable them to emulate the learning behaviors observed in biological systems. These findings highlight the potential of CuI-ITO transistors in neuromorphic applications that demand adaptive learning and real-time signal processing, thereby offering a promising pathway toward the advancement of artificial intelligence systems.
{"title":"Synaptic Plasticity and Learning Behavior Emulated in CuI-ITO Transistors","authors":"Yuling Peng;Wei Dou;Jiangyun Lei;Pengfei Chen;Xiaodong Xu;Dongsheng Tang","doi":"10.1109/TED.2025.3609305","DOIUrl":"https://doi.org/10.1109/TED.2025.3609305","url":null,"abstract":"Synaptic transistors are fabricated using chitosan as the gate dielectric and CuI with sputtered ITO as the channel. Surface charge-transfer doping from the ITO enhanced the performance and operational stability of the devices. Meanwhile, the application of voltage pulses enables the devices to emulate synaptic characteristics, including excitatory postsynaptic currents (EPSCs), inhibitory postsynaptic currents (IPSCs), paired-pulse facilitation (PPF), short-term plasticity (STP), and spike-frequency-dependent plasticity (SFDP). Furthermore, the transistors exhibit the capacity to modulate synaptic weights bidirectionally by realizing both long-term potentiation (LTP) and long-term depression (LTD), with good repeatability. The biomimetic synaptic properties of the devices enable them to emulate the learning behaviors observed in biological systems. These findings highlight the potential of CuI-ITO transistors in neuromorphic applications that demand adaptive learning and real-time signal processing, thereby offering a promising pathway toward the advancement of artificial intelligence systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6336-6340"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/TED.2025.3608840
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Reliability of Advanced Nodes","authors":"","doi":"10.1109/TED.2025.3608840","DOIUrl":"https://doi.org/10.1109/TED.2025.3608840","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 10","pages":"5772-5773"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11176794","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145121310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we report performance enhancement and reliability improvement of oxide semiconductor FETs (OS FETs) by polycrystalline Ga-doped InOx (poly-IGO). Atomic layer deposition (ALD) and post-deposition annealing (PDA) were employed to achieve crystallization of IGO. A systematic study of bottom-gate (BG) FETs with varied Ga concentrations and film thicknesses identified optimized conditions yielding a mobility up to 81 cm2/V $cdot $ s. Low-temperature measurements were conducted to physically understand the mobility improvement. The carrier transport mechanisms were discussed. Then, we developed a novel selective crystallization method in the OS stack for process integration and device operation of gate-all-around (GAA) nanosheet (NS) IGO FETs. The fabricated GAA IGO FETs showed normally-off operation, high on-current of $326~mu $ A/$mu $ m, and a steep subthreshold slope of 68 mV/dec. In addition, GAA NS FETs exhibited further improved bias stress stability. This work provides a scalable strategy of poly-OS channels for monolithic 3-D (M3D) integration and 3-D memory such as 3-D DRAM and 3-D NAND.
{"title":"A Gate-All-Around Oxide Semiconductor FETs With Selectively Crystallized InGaOₓ Channel for Performance and Reliability Improvement","authors":"Ki-Woong Park;Anlan Chen;Kota Sakai;Sunbin Hwang;Xingyu Huang;Takuya Saraya;Toshiro Hiramoto;Takanori Takahashi;Mutsunori Uenuma;Yukiharu Uraoka;Masaharu Kobayashi","doi":"10.1109/TED.2025.3605574","DOIUrl":"https://doi.org/10.1109/TED.2025.3605574","url":null,"abstract":"In this article, we report performance enhancement and reliability improvement of oxide semiconductor FETs (OS FETs) by polycrystalline Ga-doped InOx (poly-IGO). Atomic layer deposition (ALD) and post-deposition annealing (PDA) were employed to achieve crystallization of IGO. A systematic study of bottom-gate (BG) FETs with varied Ga concentrations and film thicknesses identified optimized conditions yielding a mobility up to 81 cm2/V <inline-formula> <tex-math>$cdot $ </tex-math></inline-formula> s. Low-temperature measurements were conducted to physically understand the mobility improvement. The carrier transport mechanisms were discussed. Then, we developed a novel selective crystallization method in the OS stack for process integration and device operation of gate-all-around (GAA) nanosheet (NS) IGO FETs. The fabricated GAA IGO FETs showed normally-<sc>off</small> operation, high <sc>on</small>-current of <inline-formula> <tex-math>$326~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, and a steep subthreshold slope of 68 mV/dec. In addition, GAA NS FETs exhibited further improved bias stress stability. This work provides a scalable strategy of poly-OS channels for monolithic 3-D (M3D) integration and 3-D memory such as 3-D DRAM and 3-D NAND.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7128-7135"},"PeriodicalIF":3.2,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1109/TED.2025.3605320
Yuzhuo Yuan;Guangshun Li;Daohui Ge;Tingting Liu;Qian Xin;Aimin Song
Neuromorphic system may overcome von Neumann bottleneck and achieve higher computational efficiency. Among various approaches, oxide-based synaptic transistors have gained significant attention due to their tunable physical properties and compatibility with large-area industrial manufacturing. However, most reported artificial synapses are n-type, while p-type remain scarce. In this article, p-type tin monoxide (SnO) transistor with high hysteresis current of 1157.5 nA is realized by optimizing the annealing condition. Both excitatory and inhibitory plasticity can be realized within a single thin-film transistor (TFT) device, enhancing its functionality for neuromorphic applications. The observed linear dependence of postsynaptic current on the spike voltage simplifies computation complexity and enhancing efficiency. Additionally, essential synaptic functions including spike-duration dependent plasticity (SDDP), paired-pulse facilitation (PPF), paired-pulse depression (PPD), AtkinsonShiffrin memory mode, high-pass filter, spike-timingdependent plasticity (STDP), and anti-STDP are also successfully simulated. Furthermore, the p-type SnO material demonstrates low cytotoxicity. The synaptic plasticity of p-type SnO-based synaptic transistor effectively mimics biological synapse behavior, highlighting its potential to construct high-performance complementary neuromorphic systems.
{"title":"Gate-Tunable Synaptic Transistors Based on P-Type SnO for Complementary Neuromorphic System","authors":"Yuzhuo Yuan;Guangshun Li;Daohui Ge;Tingting Liu;Qian Xin;Aimin Song","doi":"10.1109/TED.2025.3605320","DOIUrl":"https://doi.org/10.1109/TED.2025.3605320","url":null,"abstract":"Neuromorphic system may overcome von Neumann bottleneck and achieve higher computational efficiency. Among various approaches, oxide-based synaptic transistors have gained significant attention due to their tunable physical properties and compatibility with large-area industrial manufacturing. However, most reported artificial synapses are n-type, while p-type remain scarce. In this article, p-type tin monoxide (SnO) transistor with high hysteresis current of 1157.5 nA is realized by optimizing the annealing condition. Both excitatory and inhibitory plasticity can be realized within a single thin-film transistor (TFT) device, enhancing its functionality for neuromorphic applications. The observed linear dependence of postsynaptic current on the spike voltage simplifies computation complexity and enhancing efficiency. Additionally, essential synaptic functions including spike-duration dependent plasticity (SDDP), paired-pulse facilitation (PPF), paired-pulse depression (PPD), AtkinsonShiffrin memory mode, high-pass filter, spike-timingdependent plasticity (STDP), and anti-STDP are also successfully simulated. Furthermore, the p-type SnO material demonstrates low cytotoxicity. The synaptic plasticity of p-type SnO-based synaptic transistor effectively mimics biological synapse behavior, highlighting its potential to construct high-performance complementary neuromorphic systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6315-6320"},"PeriodicalIF":3.2,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-09DOI: 10.1109/TED.2025.3606424
Sang-Won Lee;Seong-Yun Yun;Yang-Kyu Choi
The p-n-p bi-stable resistor (biristor), complementary to an n-p-n biristor, is demonstrated on a bulk substrate in the form of a silicon nanowire (SiNW). It consists of a ${p}^{+}$ -emitter, ${n}^{{0}}$ -base, and ${p}^{+}$ -collector, with each electrode having inverted polarity compared to an n-p-n biristor. This p-n-p biristor also exhibits the characteristics of a single-transistor latch (STL), similar to its counterpart, the n-p-n biristor. The p-n-p biristor can also be applied to a steep slope device, a ternary device, an artificial neuron, a relaxation oscillator, and a true random number generator, akin to n-p-n biristor applications.
{"title":"p-n-p Biristor With a Silicon Nanowire","authors":"Sang-Won Lee;Seong-Yun Yun;Yang-Kyu Choi","doi":"10.1109/TED.2025.3606424","DOIUrl":"https://doi.org/10.1109/TED.2025.3606424","url":null,"abstract":"The p-n-p bi-stable resistor (biristor), complementary to an n-p-n biristor, is demonstrated on a bulk substrate in the form of a silicon nanowire (SiNW). It consists of a <inline-formula> <tex-math>${p}^{+}$ </tex-math></inline-formula>-emitter, <inline-formula> <tex-math>${n}^{{0}}$ </tex-math></inline-formula>-base, and <inline-formula> <tex-math>${p}^{+}$ </tex-math></inline-formula>-collector, with each electrode having inverted polarity compared to an n-p-n biristor. This p-n-p biristor also exhibits the characteristics of a single-transistor latch (STL), similar to its counterpart, the n-p-n biristor. The p-n-p biristor can also be applied to a steep slope device, a ternary device, an artificial neuron, a relaxation oscillator, and a true random number generator, akin to n-p-n biristor applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6375-6378"},"PeriodicalIF":3.2,"publicationDate":"2025-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gallium-doped hafnium oxide (HGO) exhibits excellent ferroelectricity with remarkable reliability and improved endurance characteristics. However, the requisite high-temperature annealing ($gt 600~^{circ }$ C) poses challenges for CMOS back-end-of-line (BEOL) integration. To achieve ferroelectric (FE) HGO at low temperatures (below $400~^{circ }$ C), we carried out an in-depth analysis on the role of N2 flow during rapid thermal annealing (RTA) on ferroelectricity at $400~^{circ }$ C. Low-N2-flow-rate annealing under reduced pressure lowers the energy barrier for stabilizing the FE orthorhombic phase (o-phase) in HGO, though at the expense of cooling efficiency. Strategic flow parameter optimization enables FE for the HGO capacitor under BEOL-compatible annealing conditions. In addition, the FE behavior of HGO films with different Ga doping concentrations was investigated. The identified Ga doping window (4.17–9.09 atomic%) redefines the phase stability criteria for 10 nm HGO FEs. The remnant polarization $(2{P}_{r})$ of $24.8~mu $ C/cm2 was achieved for HGO samples with 6.14 atomic% Ga processed at $400~^{circ }$ C. Furthermore, due to the decrease in process temperature, the devices exhibit robust performance, including low leakage current and high endurance ($gt 10^{{9}}$ ). This work establishes a BEOL-compatible hafnium-based FE material system through low-temperature process engineering.
{"title":"A Back-End-of-Line-Compatible Ferroelectric Ga-Doped HfO₂ Capacitor With Low Thermal Budget (400°C)","authors":"Peng Yuan;Xufang Zhang;Peng Peng;Xinzhong Zhu;Heng Ye;Xiaomin Lai;Yuan Qiu;Pengfei Jiang;Qing Luo;Jing Zhang","doi":"10.1109/TED.2025.3604777","DOIUrl":"https://doi.org/10.1109/TED.2025.3604777","url":null,"abstract":"Gallium-doped hafnium oxide (HGO) exhibits excellent ferroelectricity with remarkable reliability and improved endurance characteristics. However, the requisite high-temperature annealing (<inline-formula> <tex-math>$gt 600~^{circ }$ </tex-math></inline-formula>C) poses challenges for CMOS back-end-of-line (BEOL) integration. To achieve ferroelectric (FE) HGO at low temperatures (below <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C), we carried out an in-depth analysis on the role of N2 flow during rapid thermal annealing (RTA) on ferroelectricity at <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C. Low-N2-flow-rate annealing under reduced pressure lowers the energy barrier for stabilizing the FE orthorhombic phase (o-phase) in HGO, though at the expense of cooling efficiency. Strategic flow parameter optimization enables FE for the HGO capacitor under BEOL-compatible annealing conditions. In addition, the FE behavior of HGO films with different Ga doping concentrations was investigated. The identified Ga doping window (4.17–9.09 atomic%) redefines the phase stability criteria for 10 nm HGO FEs. The remnant polarization <inline-formula> <tex-math>$(2{P}_{r})$ </tex-math></inline-formula> of <inline-formula> <tex-math>$24.8~mu $ </tex-math></inline-formula>C/cm2 was achieved for HGO samples with 6.14 atomic% Ga processed at <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C. Furthermore, due to the decrease in process temperature, the devices exhibit robust performance, including low leakage current and high endurance (<inline-formula> <tex-math>$gt 10^{{9}}$ </tex-math></inline-formula>). This work establishes a BEOL-compatible hafnium-based FE material system through low-temperature process engineering.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6387-6390"},"PeriodicalIF":3.2,"publicationDate":"2025-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we have experimentally studied the response of electrolyte-gated graphene field-effect transistors (EG-gFETs) under various stress and relaxation conditions at different voltage bias values and temperatures. We fit all the experimental data with an analytical model based on charge trapping at the silicon oxide substrate defects in contact with the graphene channel. In the model, the electron transitions require overcoming an energetic barrier leading to the new state and, consequently, the process is temperature- and gate-bias-dependent. The fit parameters to the experimental data are then used for the first time to construct the capture–emission time maps (CET maps) of the EG-gFET devices, or the capture/emission time distribution of the oxide defects and their contribution to the device’s drift and noise at each timescale. Studying these maps as a function of the bias and temperature allows us to gain insight into the best experimental conditions to minimize electrical noise during measurements, to propose improved protocols when using EG-gFETs in applications and to guide circuit designers on deciding the best operating conditions.
{"title":"Temperature- and Bias-Dependent Capture–Emission Time Maps in Electrolyte-Gated Graphene Field-Effect Transistors","authors":"Adriana Oliveira;Henrique Nóbrega;Telma Domingues;Jérôme Borme;Pedro Alpuim;João Mouro","doi":"10.1109/TED.2025.3603796","DOIUrl":"https://doi.org/10.1109/TED.2025.3603796","url":null,"abstract":"In this work, we have experimentally studied the response of electrolyte-gated graphene field-effect transistors (EG-gFETs) under various stress and relaxation conditions at different voltage bias values and temperatures. We fit all the experimental data with an analytical model based on charge trapping at the silicon oxide substrate defects in contact with the graphene channel. In the model, the electron transitions require overcoming an energetic barrier leading to the new state and, consequently, the process is temperature- and gate-bias-dependent. The fit parameters to the experimental data are then used for the first time to construct the capture–emission time maps (CET maps) of the EG-gFET devices, or the capture/emission time distribution of the oxide defects and their contribution to the device’s drift and noise at each timescale. Studying these maps as a function of the bias and temperature allows us to gain insight into the best experimental conditions to minimize electrical noise during measurements, to propose improved protocols when using EG-gFETs in applications and to guide circuit designers on deciding the best operating conditions.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6321-6328"},"PeriodicalIF":3.2,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TED.2025.3598553
{"title":"IEEE Transactions on Electron Devices Publication Information","authors":"","doi":"10.1109/TED.2025.3598553","DOIUrl":"https://doi.org/10.1109/TED.2025.3598553","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"C2-C2"},"PeriodicalIF":3.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142505","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TED.2025.3598557
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Reliability of Advanced Nodes","authors":"","doi":"10.1109/TED.2025.3598557","DOIUrl":"https://doi.org/10.1109/TED.2025.3598557","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5261-5262"},"PeriodicalIF":3.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142481","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-26DOI: 10.1109/TED.2025.3598555
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices on Wide Band Gap Semiconductors for Automotive Applications","authors":"","doi":"10.1109/TED.2025.3598555","DOIUrl":"https://doi.org/10.1109/TED.2025.3598555","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5259-5260"},"PeriodicalIF":3.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142480","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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