Pub Date : 2024-08-01DOI: 10.1109/TED.2024.3433835
Yan-Kui Liang;Wei-Li Li;Yu-Lon Lin;Dong-Ru Hsieh;Tsung-Ying Yang;Tsung-Te Chou;Chi-Chung Kei;Huai-Ying Huang;Yu-Ming Lin;Yuan-Chieh Tseng;Tien-Sheng Chao;Edward Yi Chang;Kasidit Toprasertpong;Shinichi Takagi;Chun-Hsiung Lin
In this study, we investigated the impact of inserting an interfacial layer (IL) between the InZnO channel and ZrO2/HfO2 superlattice (SL) ferroelectric (FE) gate-stack on the performance and stability of highly scaled FE thin-film transistors (FeTFTs). FeTFTs with various channel lengths (50–750 nm) were characterized to reveal the impact of two IL (i.e., TiO2 and Al2O3) on device characteristics. All the memory window (MW) contours of FeTFTs with a pulsewidth of 1 ms–100 ns and an amplitude of 2.5–5 V have been investigated. The FeTFT with TiO2 IL demonstrated impressive stability in MW ( $boldsymbol {Delta } $ MW/MW $_{{1}text {st cy}text {cle}}~boldsymbol {le } ~3.6$ %) up to 108 cycles for a program/erase voltage of $boldsymbol {pm }3$ V and pulsewidth of $1~boldsymbol {mu } $ s. It was suggested that the FeTFT with a higher dielectric constant $(k)$ TiO2 IL may reduce the electrical field and depolarization field at the interface between the channel and gate dielectric, as well as improve interfacial quality, thereby enhancing the reliability of FeTFTs.
{"title":"Improved Stability of BEOL-Compatible Highly Scaled Ultrathin InZnO Channel Ferroelectric Thin-Film Transistor With TiO₂ Interfacial Layer","authors":"Yan-Kui Liang;Wei-Li Li;Yu-Lon Lin;Dong-Ru Hsieh;Tsung-Ying Yang;Tsung-Te Chou;Chi-Chung Kei;Huai-Ying Huang;Yu-Ming Lin;Yuan-Chieh Tseng;Tien-Sheng Chao;Edward Yi Chang;Kasidit Toprasertpong;Shinichi Takagi;Chun-Hsiung Lin","doi":"10.1109/TED.2024.3433835","DOIUrl":"10.1109/TED.2024.3433835","url":null,"abstract":"In this study, we investigated the impact of inserting an interfacial layer (IL) between the InZnO channel and ZrO2/HfO2 superlattice (SL) ferroelectric (FE) gate-stack on the performance and stability of highly scaled FE thin-film transistors (FeTFTs). FeTFTs with various channel lengths (50–750 nm) were characterized to reveal the impact of two IL (i.e., TiO2 and Al2O3) on device characteristics. All the memory window (MW) contours of FeTFTs with a pulsewidth of 1 ms–100 ns and an amplitude of 2.5–5 V have been investigated. The FeTFT with TiO2 IL demonstrated impressive stability in MW (\u0000<inline-formula> <tex-math>$boldsymbol {Delta } $ </tex-math></inline-formula>\u0000 MW/MW\u0000<inline-formula> <tex-math>$_{{1}text {st cy}text {cle}}~boldsymbol {le } ~3.6$ </tex-math></inline-formula>\u0000%) up to 108 cycles for a program/erase voltage of \u0000<inline-formula> <tex-math>$boldsymbol {pm }3$ </tex-math></inline-formula>\u0000 V and pulsewidth of \u0000<inline-formula> <tex-math>$1~boldsymbol {mu } $ </tex-math></inline-formula>\u0000 s. It was suggested that the FeTFT with a higher dielectric constant \u0000<inline-formula> <tex-math>$(k)$ </tex-math></inline-formula>\u0000 TiO2 IL may reduce the electrical field and depolarization field at the interface between the channel and gate dielectric, as well as improve interfacial quality, thereby enhancing the reliability of FeTFTs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141881602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-01DOI: 10.1109/TED.2024.3433836
Chunlan Wang;Yuchao Jiao;Chi Luo;Yongle Song;Hao Huang;Hongbing Lu;Jingli Wang
The amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with Cu/Al stacked contacts to restrain the transferring of Cu to a-IGZO were prepared by thermal evaporation and magnetron sputtering. Compared to Cu contacts, the devices of stacked contacts offered improved performance and stability. When Al thickness was increased to 5 nm, the devices of stacked contacts exhibited field effect mobility ( $mu _{text {FE}}text {)}$ of 25 cm2/V $cdot $ s and the subthreshold swing (SS) of 0.49 V/dec. Particularly, the threshold voltage shift ( $Delta $ V ${}_{text {th}}text {)}$ of the devices with stacked contacts was -0.29 V under the negative bias stress. Furthermore, the devices with stacked contacts of 5 nm Al presented outstanding contact characteristics by transmission line mode analysis. The results suggested that Cu/Al electrodes were expected to become useful electrodes for optimizing metal oxide TFTs.
{"title":"Evolution of Enhanced Performance of a-IGZO TFTs With Cu/Al-Based Contacts","authors":"Chunlan Wang;Yuchao Jiao;Chi Luo;Yongle Song;Hao Huang;Hongbing Lu;Jingli Wang","doi":"10.1109/TED.2024.3433836","DOIUrl":"10.1109/TED.2024.3433836","url":null,"abstract":"The amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with Cu/Al stacked contacts to restrain the transferring of Cu to a-IGZO were prepared by thermal evaporation and magnetron sputtering. Compared to Cu contacts, the devices of stacked contacts offered improved performance and stability. When Al thickness was increased to 5 nm, the devices of stacked contacts exhibited field effect mobility (\u0000<inline-formula> <tex-math>$mu _{text {FE}}text {)}$ </tex-math></inline-formula>\u0000 of 25 cm2/V\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000s and the subthreshold swing (SS) of 0.49 V/dec. Particularly, the threshold voltage shift (\u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000V\u0000<inline-formula> <tex-math>${}_{text {th}}text {)}$ </tex-math></inline-formula>\u0000 of the devices with stacked contacts was -0.29 V under the negative bias stress. Furthermore, the devices with stacked contacts of 5 nm Al presented outstanding contact characteristics by transmission line mode analysis. The results suggested that Cu/Al electrodes were expected to become useful electrodes for optimizing metal oxide TFTs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141881514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, an innovative layout is introduced to reduce the stray inductance of the multichip power modules (MCPMs) through reverse coupling of current in parallel power loops, which effectively cancels out mutual inductance. A half-bridge silicon carbide (SiC) MOSFET power module was designed based on this novel layout. The fabricated SiC power module was experimentally validated, demonstrating a measured stray inductance of about 3.5 nH. Experimental results confirmed that the proposed module outperforms counterpart commercial SiC MOSFET power modules in terms of turn-off overshoot voltage and switching loss reduction, highlighting the advantage of the reverse-coupling current approach in enhancing power module performance. The principle of enhancing negative mutual inductance and dynamic current sharing in circuits through the reverse coupling parallel loops is discussed.
{"title":"Innovative Reverse Current Coupling Layout of SiC Power Module for Parasitic Inductance Reduction","authors":"Ying Wang;Xi Jiang;Song Yuan;Nianlong Ma;Runze Ouyang;Daoyong Jia;Xiaowu Gong;Zhenjiang Pang;Lei Wen;Haimin Hong;Hao Niu","doi":"10.1109/TED.2024.3433319","DOIUrl":"10.1109/TED.2024.3433319","url":null,"abstract":"In this article, an innovative layout is introduced to reduce the stray inductance of the multichip power modules (MCPMs) through reverse coupling of current in parallel power loops, which effectively cancels out mutual inductance. A half-bridge silicon carbide (SiC) MOSFET power module was designed based on this novel layout. The fabricated SiC power module was experimentally validated, demonstrating a measured stray inductance of about 3.5 nH. Experimental results confirmed that the proposed module outperforms counterpart commercial SiC MOSFET power modules in terms of turn-off overshoot voltage and switching loss reduction, highlighting the advantage of the reverse-coupling current approach in enhancing power module performance. The principle of enhancing negative mutual inductance and dynamic current sharing in circuits through the reverse coupling parallel loops is discussed.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141881522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The gate-bias stability of amorphous indium-tin-zinc-oxide (a-ITZO) field-effect transistors (FETs) is critical for their display and emerging memory applications. However, a-ITZO FETs suffer from insufficient gate-bias stability induced by oxygen vacancies in the channel layer. To address this issue, we examined the impact of source/drain (S/D) electrode materials (W, Mo, and Ni) on the oxygen vacancy formation and electrical characteristics in the a-ITZO FETs. Through X-ray photoelectron spectroscopy (XPS) analysis, we found that the Ni S/D electrode is effective in forming fewer oxygen vacancies in the a-ITZO channel, whereas W and Mo induce many oxygen vacancies. Our proposed model suggests that the Ni electrode absorbing less oxygen from the a-ITZO films compared to other electrodes leads to fewer oxygen vacancies in the a-ITZO channel. Notably, the a-ITZO FETs incorporating Ni S/D electrodes exhibit not only excellent electrical performance, including a high field-effect mobility of 27.6 cm2/Vs, a steep subthreshold swing (SS) of 71.8 mV/decade, and high on/off ratio of $sim 10^{{7}}$ , but also an outstanding gate-bias stability ( $Delta V_{text {th}} = -0.04$ V) under negative bias stress (NBS) testing. These findings underscore the potential of Ni S/D electrodes in advancing the development of high-performance, stable a-ITZO FETs for the next-generation semiconductor devices.
非晶铟锡锌氧化物（a-ITZO）场效应晶体管（FET）的栅极偏压稳定性对其显示和新兴存储器应用至关重要。然而，a-ITZO 场效应晶体管因沟道层中的氧空位而导致栅极偏压稳定性不足。为了解决这个问题，我们研究了源电极/漏极（S/D）材料（W、Mo 和 Ni）对 a-ITZO FET 中氧空位形成和电气特性的影响。通过 X 射线光电子能谱 (XPS) 分析，我们发现镍 S/D 电极能有效地在 a-ITZO 沟道中形成较少的氧空位，而 W 和 Mo 则会诱发许多氧空位。我们提出的模型表明，与其他电极相比，镍电极从 a-ITZO 薄膜中吸收的氧气更少，从而导致 a-ITZO 沟道中的氧空位更少。值得注意的是，采用镍 S/D 电极的 a-ITZO FET 不仅具有出色的电气性能，包括 27.6 cm2/Vs 的高场效应迁移率、71.8 mV/decade 的陡峭阈下摆动 (SS) 和 $sim 10^{7}}$ 的高导通/关断比，而且在负偏压测试下具有出色的栅偏稳定性（$Delta V_{text {th}} = -0.04$ V）。这些发现凸显了镍 S/D 电极在推动高性能、稳定的 a-ITZO FET 开发方面的潜力，可用于下一代半导体器件。
{"title":"Effect of Source/Drain Electrode Materials on the Electrical Performance and Stability of Amorphous Indium-Tin-Zinc-Oxide FETs","authors":"Seong Ui An;Dae-Hwan Ahn;Gijun Ju;Simin Chen;Yo Seop Ji;Jae-Hoon Han;Jaekyun Kim;Younghyun Kim","doi":"10.1109/TED.2024.3433831","DOIUrl":"10.1109/TED.2024.3433831","url":null,"abstract":"The gate-bias stability of amorphous indium-tin-zinc-oxide (a-ITZO) field-effect transistors (FETs) is critical for their display and emerging memory applications. However, a-ITZO FETs suffer from insufficient gate-bias stability induced by oxygen vacancies in the channel layer. To address this issue, we examined the impact of source/drain (S/D) electrode materials (W, Mo, and Ni) on the oxygen vacancy formation and electrical characteristics in the a-ITZO FETs. Through X-ray photoelectron spectroscopy (XPS) analysis, we found that the Ni S/D electrode is effective in forming fewer oxygen vacancies in the a-ITZO channel, whereas W and Mo induce many oxygen vacancies. Our proposed model suggests that the Ni electrode absorbing less oxygen from the a-ITZO films compared to other electrodes leads to fewer oxygen vacancies in the a-ITZO channel. Notably, the a-ITZO FETs incorporating Ni S/D electrodes exhibit not only excellent electrical performance, including a high field-effect mobility of 27.6 cm2/Vs, a steep subthreshold swing (SS) of 71.8 mV/decade, and high on/off ratio of \u0000<inline-formula> <tex-math>$sim 10^{{7}}$ </tex-math></inline-formula>\u0000, but also an outstanding gate-bias stability (\u0000<inline-formula> <tex-math>$Delta V_{text {th}} = -0.04$ </tex-math></inline-formula>\u0000 V) under negative bias stress (NBS) testing. These findings underscore the potential of Ni S/D electrodes in advancing the development of high-performance, stable a-ITZO FETs for the next-generation semiconductor devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141881518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-01DOI: 10.1109/TED.2024.3430251
Vandana Kumari;Manoj Saxena;Mridula Gupta
The work presented in this study examines the behavior of InAlN/GaN high electron mobility transistor (HEMT) by scaling down the device geometry, including the gate length and barrier thickness, at various operating temperatures. Extensive simulation has been performed using Silvaco’s Victory TCAD simulator tool to analyze the dc and RF performance of InAlN HEMT in terms of ${I}_{text {on}}/{I}_{text {off}}$ , intrinsic gain, DIBL, and cutoff frequency. To strengthen the RF performance at increased device length, dual gate (DG) architecture [i.e., Gate 1 (G1) and Gate 2 (G2)] has been adopted, and different gate biasing combinations have been used to investigate the device performance. A tradeoff among intrinsic gain and cutoff frequency is noted from the results. An increment in the cutoff frequency of nearly 57% has been obtained with the introduction of DG along with a deterioration in intrinsic gain.
{"title":"RF Performance Augmentation Using DG-InAlN/GaN HEMT","authors":"Vandana Kumari;Manoj Saxena;Mridula Gupta","doi":"10.1109/TED.2024.3430251","DOIUrl":"10.1109/TED.2024.3430251","url":null,"abstract":"The work presented in this study examines the behavior of InAlN/GaN high electron mobility transistor (HEMT) by scaling down the device geometry, including the gate length and barrier thickness, at various operating temperatures. Extensive simulation has been performed using Silvaco’s Victory TCAD simulator tool to analyze the dc and RF performance of InAlN HEMT in terms of \u0000<inline-formula> <tex-math>${I}_{text {on}}/{I}_{text {off}}$ </tex-math></inline-formula>\u0000, intrinsic gain, DIBL, and cutoff frequency. To strengthen the RF performance at increased device length, dual gate (DG) architecture [i.e., Gate 1 (G1) and Gate 2 (G2)] has been adopted, and different gate biasing combinations have been used to investigate the device performance. A tradeoff among intrinsic gain and cutoff frequency is noted from the results. An increment in the cutoff frequency of nearly 57% has been obtained with the introduction of DG along with a deterioration in intrinsic gain.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141881516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A nanosecond pulse generator (NSPG), with a high peak voltage, short-duration pulsewidth, high repetition rate, and fast rise/fall times, has gained traction and is now used in several applications such as plasma, biomedical, and industrial. The pulse characteristics vary with the type of application and these are affected by the choice of the switching devices in any topology and other elements of NSPG. Therefore, a variety of NSPGs have been researched, which makes the selection of any particular topology for NSPG development a challenging task. Thus, to address this gap, the literature presents a review of several conventional and state-of-the-art topologies of NSPG with high-power (HP) switching devices such as spark gap, solid-state switches, magnetic switches, and other elements for various applications. It also presents the pulse’s duration, voltage, current, power, rise/fall time, and repetition frequency for different applications. Furthermore, strategies for minimizing switching losses and other losses that substantially lower pulse generator efficiency are also discussed. Finally, a concise evaluation of available switching devices and other elements of NSPG, their pros and cons, and future directions are discussed to provide a clear understanding to designers and researchers.
{"title":"Review of Nanosecond Pulse Generator With High-Power Switching Devices","authors":"Aashish Ranjan;Anand Abhishek;Niraj Kumar;Brijendra Kumar Verma","doi":"10.1109/TED.2024.3429300","DOIUrl":"10.1109/TED.2024.3429300","url":null,"abstract":"A nanosecond pulse generator (NSPG), with a high peak voltage, short-duration pulsewidth, high repetition rate, and fast rise/fall times, has gained traction and is now used in several applications such as plasma, biomedical, and industrial. The pulse characteristics vary with the type of application and these are affected by the choice of the switching devices in any topology and other elements of NSPG. Therefore, a variety of NSPGs have been researched, which makes the selection of any particular topology for NSPG development a challenging task. Thus, to address this gap, the literature presents a review of several conventional and state-of-the-art topologies of NSPG with high-power (HP) switching devices such as spark gap, solid-state switches, magnetic switches, and other elements for various applications. It also presents the pulse’s duration, voltage, current, power, rise/fall time, and repetition frequency for different applications. Furthermore, strategies for minimizing switching losses and other losses that substantially lower pulse generator efficiency are also discussed. Finally, a concise evaluation of available switching devices and other elements of NSPG, their pros and cons, and future directions are discussed to provide a clear understanding to designers and researchers.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141881517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-01DOI: 10.1109/TED.2024.3433313
Yu Zhao;Zhikai Gan;Chun Lin;Quanzhi Sun;Liqi Zhu;Songmin Zhou;Xi Wang;Xun Li
Small-pitch HgCdTe detector is a strong trend in IR imaging. It requires focal plane arrays with small pixels. The key factors including injection dose and Hg vacancy concentration during HgCdTe junction formation were studied. A special designed junction spacing experiment was used to directly measure the junction expansion. The simulation of junction expansion through numerical method was carried out to interpret the physical mechanism of junction expansion in HgCdTe. Moreover, a pixel array test using the suggested parameters obtained in junction spacing experiment and simulation was also carried out. It validates the correctness and effectiveness of the experiment and the numerical model. This work gives fundamental concept of junction formation in HgCdTe, shows the proper parameters for fabricating the small-pitch detectors, and provides numerical model for simulation and optimization of HgCdTe junction design.
{"title":"Junction Formation Processing of MWIR Small-Pitch HgCdTe Detectors","authors":"Yu Zhao;Zhikai Gan;Chun Lin;Quanzhi Sun;Liqi Zhu;Songmin Zhou;Xi Wang;Xun Li","doi":"10.1109/TED.2024.3433313","DOIUrl":"10.1109/TED.2024.3433313","url":null,"abstract":"Small-pitch HgCdTe detector is a strong trend in IR imaging. It requires focal plane arrays with small pixels. The key factors including injection dose and Hg vacancy concentration during HgCdTe junction formation were studied. A special designed junction spacing experiment was used to directly measure the junction expansion. The simulation of junction expansion through numerical method was carried out to interpret the physical mechanism of junction expansion in HgCdTe. Moreover, a pixel array test using the suggested parameters obtained in junction spacing experiment and simulation was also carried out. It validates the correctness and effectiveness of the experiment and the numerical model. This work gives fundamental concept of junction formation in HgCdTe, shows the proper parameters for fabricating the small-pitch detectors, and provides numerical model for simulation and optimization of HgCdTe junction design.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141881601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cd (3%)-doped ZnO TF/ZnO TF heterostructure (HS) was fabricated and studied for UV-Visible broadband photodetection application. X-ray diffraction (XRD) and field emission scanning electron microscope (FESEM) images confirmed the structural and morphological integrity of the HS. The HS showed better device performance both in UV and visible regions when compared with a reference ZnO TF sample. Enhancement in absorption intensity due to replacement of Zn ions by larger Cd ions and large photocurrent generation due to increase in carrier concentration via doping can be credited for the improved performance of the hybrid HS. Thus, achieving high spectral responsivity, R $_{lambda }$ [20.5 A/W (UV), 18 A/W (visible)] and fast photoresponse [ ${T}_{text {rise}} =0.31$ s, ${T}_{text {fall}} =0.53$ s (UV) and ${T}_{text {rise}} =0.27$ s, ${T}_{text {fall}} =0.29$ s (visible)] from the hybrid sample.
{"title":"Design of High-Performance UV-Visible Broadband Photodetector Using Cd-Doped ZnO/ZnO Thin-Film Heterostructure","authors":"Chiru Deepak Kalepu;Vasanthi Kondepati;K. Moatemsu Aier;Jay Chandra Dhar","doi":"10.1109/TED.2024.3433315","DOIUrl":"10.1109/TED.2024.3433315","url":null,"abstract":"Cd (3%)-doped ZnO TF/ZnO TF heterostructure (HS) was fabricated and studied for UV-Visible broadband photodetection application. X-ray diffraction (XRD) and field emission scanning electron microscope (FESEM) images confirmed the structural and morphological integrity of the HS. The HS showed better device performance both in UV and visible regions when compared with a reference ZnO TF sample. Enhancement in absorption intensity due to replacement of Zn ions by larger Cd ions and large photocurrent generation due to increase in carrier concentration via doping can be credited for the improved performance of the hybrid HS. Thus, achieving high spectral responsivity, R\u0000<inline-formula> <tex-math>$_{lambda }$ </tex-math></inline-formula>\u0000 [20.5 A/W (UV), 18 A/W (visible)] and fast photoresponse [\u0000<inline-formula> <tex-math>${T}_{text {rise}} =0.31$ </tex-math></inline-formula>\u0000 s, \u0000<inline-formula> <tex-math>${T}_{text {fall}} =0.53$ </tex-math></inline-formula>\u0000 s (UV) and \u0000<inline-formula> <tex-math>${T}_{text {rise}} =0.27$ </tex-math></inline-formula>\u0000 s, \u0000<inline-formula> <tex-math>${T}_{text {fall}} =0.29$ </tex-math></inline-formula>\u0000 s (visible)] from the hybrid sample.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141865409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To address the concerns on the retention loss of HfO2-based ferroelectric (FE) devices in versatile applications, we conduct a comprehensive wide temperature range (250–400 K) characterization on a 9-nm Hf0.5Zr0.5O2 (HZO) film. It reveals that the retention will be damaged by the high temperature and incomplete polarization (fast speed and low amplitude operation). The dominant mechanism is believed to be the imprint effect, which occurs due to the migration of charged defects to the interface along the internal field caused by incomplete polarization. By addressing the intricacies of imprint behaviors and incomplete polarization, this work illuminates crucial aspects of retention loss in FE-HZO thin films.
{"title":"Imprint-Correlated Retention Loss in Hf₀.₅Zr₀.₅O₂ Ferroelectric Thin Film Through Wide-Temperature Characterizations","authors":"Xiaopeng Li;Lu Tai;Pengpeng Sang;Xiaoyu Dou;Xuepeng Zhan;Hao Xu;Xiaolei Wang;Jixuan Wu;Jiezhi Chen","doi":"10.1109/TED.2024.3433317","DOIUrl":"10.1109/TED.2024.3433317","url":null,"abstract":"To address the concerns on the retention loss of HfO2-based ferroelectric (FE) devices in versatile applications, we conduct a comprehensive wide temperature range (250–400 K) characterization on a 9-nm Hf0.5Zr0.5O2 (HZO) film. It reveals that the retention will be damaged by the high temperature and incomplete polarization (fast speed and low amplitude operation). The dominant mechanism is believed to be the imprint effect, which occurs due to the migration of charged defects to the interface along the internal field caused by incomplete polarization. By addressing the intricacies of imprint behaviors and incomplete polarization, this work illuminates crucial aspects of retention loss in FE-HZO thin films.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141865410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-30DOI: 10.1109/TED.2024.3421179
Srijeet Tripathy;Ambika Kumari;Tarun Kanti Bhattacharyya
In continuation to the preceding article, this part presents a study of electrical transport in Ohmic contact carbon nanotube thin film transistors (CNT TFTs). Here, the transistor model is implemented as a special case of the previously presented generalized model. Based on comparisons between simulated and experimental data, it is observed that optical phonon scattering in Ohmic contact CNT TFTs is fairly independent of gate and drain biases as opposed to the Schottky contact counterparts. Moreover, it is observed that transport is significantly affected by the channel length and alignment between CNTs as optical phonon scattering is found to be more pronounced for smaller channel lengths and greater alignments. The success of the model is supported by good agreement between simulations and a wide range of experimental data. This is verified by calculating the relative root mean square error (RMSE) which shows an average deviation in the order of ~15%. In comparison to previous CNT TFT models, this work introduces a generalized model, considering both Schottky and Ohmic contact-induced ambipolar and unipolar modes of transport, closely following the essential transport physics.
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