Pub Date : 2024-11-14DOI: 10.1109/TED.2024.3493064
Bilawal Ali;Yubin Gong;Shaomeng Wang;Yang Dong;Jibran Latif;Muhammad Khawar Nadeem;Atif Jameel;Zhanliang Wang
A C-band angular bi-periodic angular radial EIO (BPAREIO) is proposed for high-power microwave (HPM) applications. It offers miniaturization, high efficiency, and low magnetic field operation. A divergent angular radial sheet electron beam (ARSEB) with an angle of 14° and a current of 101 A is employed to operate the seven-gap angular radial cavities. Angular radial cavities are coupled by two sectoral cavities having an opening angle $beta $ . Cavity characteristics, such as dispersion, scattering parameters, normalized beam conductance, electric field distribution, and stability, are analyzed to optimize the design for $pi $ -mode operation. To further enhance the performance of BPAREIO, ridges are incorporated into interaction gaps near the beam tunnel. This modification leads to an enhanced radial electric field near the beam tunnel, increasing characteristic impedance (R/Q). In particle-in cell (PIC) simulations, ridge-loaded BPAREIO demonstrated in modeling an RF peak output power of 6.2 MW at a frequency of 5.805 GHz when applying a beam voltage of 89 kV and a magnetic field of 0.3 T, yielding a peak power efficiency of 69.5%. In contrast, the BPAREIO without ridges expected a peak output power of 5.4 MW and an efficiency of 59.5% at 5.885 GHz, using the same beam parameters. Consequently, the ridge-loaded BPAREIO predicted a 16.7% increase in peak electronic efficiency compared with the BPAREIO without ridges. Moreover, ridge-loaded BPAREIO is fabricated, and experimental results closely match those obtained from simulation.
提出了一种用于高功率微波（HPM）应用的c波段角双周期角径向EIO （BPAREIO）。它具有小型化、高效率和低磁场操作的特点。采用角为14°、电流为101 A的发散角径向片状电子束（ARSEB）对七间隙角径向腔进行操作。角径向腔由两个具有开口角$beta $的扇形腔耦合。分析了色散、散射参数、归一化光束电导、电场分布和稳定性等空腔特性，以优化$pi $模式工作的设计。为了进一步提高BPAREIO的性能，在光束隧道附近的相互作用间隙中加入了脊。这种改变导致光束隧道附近的径向电场增强，特性阻抗（R/Q）增加。在粒子池（PIC）模拟中，脊载BPAREIO在施加89 kV的波束电压和0.3 T的磁场时，在5.805 GHz的频率下建模了6.2 MW的射频峰值输出功率，产生了69.5的峰值功率效率%. In contrast, the BPAREIO without ridges expected a peak output power of 5.4 MW and an efficiency of 59.5% at 5.885 GHz, using the same beam parameters. Consequently, the ridge-loaded BPAREIO predicted a 16.7% increase in peak electronic efficiency compared with the BPAREIO without ridges. Moreover, ridge-loaded BPAREIO is fabricated, and experimental results closely match those obtained from simulation.
{"title":"Design and Cold Testing of a Bi-Periodic Angular Radial RF Circuit for a C-Band Extended Interaction Oscillator","authors":"Bilawal Ali;Yubin Gong;Shaomeng Wang;Yang Dong;Jibran Latif;Muhammad Khawar Nadeem;Atif Jameel;Zhanliang Wang","doi":"10.1109/TED.2024.3493064","DOIUrl":"https://doi.org/10.1109/TED.2024.3493064","url":null,"abstract":"A C-band angular bi-periodic angular radial EIO (BPAREIO) is proposed for high-power microwave (HPM) applications. It offers miniaturization, high efficiency, and low magnetic field operation. A divergent angular radial sheet electron beam (ARSEB) with an angle of 14° and a current of 101 A is employed to operate the seven-gap angular radial cavities. Angular radial cavities are coupled by two sectoral cavities having an opening angle \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000. Cavity characteristics, such as dispersion, scattering parameters, normalized beam conductance, electric field distribution, and stability, are analyzed to optimize the design for \u0000<inline-formula> <tex-math>$pi $ </tex-math></inline-formula>\u0000-mode operation. To further enhance the performance of BPAREIO, ridges are incorporated into interaction gaps near the beam tunnel. This modification leads to an enhanced radial electric field near the beam tunnel, increasing characteristic impedance (R/Q). In particle-in cell (PIC) simulations, ridge-loaded BPAREIO demonstrated in modeling an RF peak output power of 6.2 MW at a frequency of 5.805 GHz when applying a beam voltage of 89 kV and a magnetic field of 0.3 T, yielding a peak power efficiency of 69.5%. In contrast, the BPAREIO without ridges expected a peak output power of 5.4 MW and an efficiency of 59.5% at 5.885 GHz, using the same beam parameters. Consequently, the ridge-loaded BPAREIO predicted a 16.7% increase in peak electronic efficiency compared with the BPAREIO without ridges. Moreover, ridge-loaded BPAREIO is fabricated, and experimental results closely match those obtained from simulation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"417-423"},"PeriodicalIF":2.9,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-13DOI: 10.1109/TED.2024.3488683
Pooja Kawde;Anuja Singh;Bhaskaran Muralidharan
Type-II superlattices (T2SLs) are currently technologically favored absorbers for infrared (IR) photodetectors due to their tunable band gap, lower Auger recombination rates, and higher effective masses in comparison to traditional bulk ternary alloys such as HgCdTe. The pBn barrier configuration is usually preferred to improve the dark current characteristics of the InAs/GaSb T2SL IR photodetectors. To investigate conclusively the impact of a barrier on the dark current, we present a comprehensive study featuring a pBn and a p-i-n device configuration at 77 K. In the pBn configuration, the doping levels in the barrier and absorber layer suppress the band-to-band tunneling (BTBT) and the trap-assisted tunneling (TAT) current dominates. In the p-i-n detector, the TAT current prevails with a small contribution of BTBT current near ${V}=-1~text {V}$ , as a function of absorber doping. It is shown that the pBn detector exhibits 104 times less TAT current when compared with the p-i-n detector at ${V}=-{0.1}~text {V}$ . As the dark current varies with the number of monolayers of InAs and GaSb in a given period, we then focus on the dark current minimization of three pBn detectors with an absorber layer consisting of a symmetric superlattice (SL), InAs-rich SL, and GaSb-rich SL each with an energy band gap of 0.23 eV. We conclusively ascertain and demonstrate the barrier and absorber configurations along with the bias conditions that minimize the dark currents thereby setting a stage to systematically engineer barriers with the aim of minimizing dark currents via a component-by-component analysis.
{"title":"Dark Current Performance Enhancement in Type-II Superlattice Photodetectors via pBn Barrier Engineering","authors":"Pooja Kawde;Anuja Singh;Bhaskaran Muralidharan","doi":"10.1109/TED.2024.3488683","DOIUrl":"https://doi.org/10.1109/TED.2024.3488683","url":null,"abstract":"Type-II superlattices (T2SLs) are currently technologically favored absorbers for infrared (IR) photodetectors due to their tunable band gap, lower Auger recombination rates, and higher effective masses in comparison to traditional bulk ternary alloys such as HgCdTe. The pBn barrier configuration is usually preferred to improve the dark current characteristics of the InAs/GaSb T2SL IR photodetectors. To investigate conclusively the impact of a barrier on the dark current, we present a comprehensive study featuring a pBn and a p-i-n device configuration at 77 K. In the pBn configuration, the doping levels in the barrier and absorber layer suppress the band-to-band tunneling (BTBT) and the trap-assisted tunneling (TAT) current dominates. In the p-i-n detector, the TAT current prevails with a small contribution of BTBT current near \u0000<inline-formula> <tex-math>${V}=-1~text {V}$ </tex-math></inline-formula>\u0000, as a function of absorber doping. It is shown that the pBn detector exhibits 104 times less TAT current when compared with the p-i-n detector at \u0000<inline-formula> <tex-math>${V}=-{0.1}~text {V}$ </tex-math></inline-formula>\u0000. As the dark current varies with the number of monolayers of InAs and GaSb in a given period, we then focus on the dark current minimization of three pBn detectors with an absorber layer consisting of a symmetric superlattice (SL), InAs-rich SL, and GaSb-rich SL each with an energy band gap of 0.23 eV. We conclusively ascertain and demonstrate the barrier and absorber configurations along with the bias conditions that minimize the dark currents thereby setting a stage to systematically engineer barriers with the aim of minimizing dark currents via a component-by-component analysis.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7628-7636"},"PeriodicalIF":2.9,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142790225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the pursuit of advancing memory density, the vertically stacked dynamic random-access memory (VS-DRAM) architecture shows promise but encounters significant obstacles. This study focuses on optimizing the device geometry of VS-DRAM access transistors to achieve a delicate balance between reducing charge loss and maintaining carrier mobility. We developed a robust modeling methodology to quantify both the charge loss induced by the floating body effect (FBE) and the carrier mobility limited by surface roughness (SR). Our investigation carefully examines how thinning the transistor channel can mitigate FBE while avoiding adverse effects on surface scattering of charge carriers, all while considering the emerging geometry confinement effect. Through meticulous analysis, we aim to identify the optimal channel thickness range for VS-DRAM transistors, offering essential insights for the advancement of high-density memory technologies.
{"title":"Balancing Charge Loss and Carrier Mobility: A Multiscale Modeling Approach for Device Geometry Optimization of VS-DRAM Dual-Gate Access Transistors","authors":"Jun Deng;Xinhe Wang;Yangyi Ou;Z. Bai;Tun Wang;Xiaomeng Liu;Mingli Liu;Qi Hu;Xiangsheng Wang;Guilei Wang;Chao Zhao","doi":"10.1109/TED.2024.3493066","DOIUrl":"https://doi.org/10.1109/TED.2024.3493066","url":null,"abstract":"In the pursuit of advancing memory density, the vertically stacked dynamic random-access memory (VS-DRAM) architecture shows promise but encounters significant obstacles. This study focuses on optimizing the device geometry of VS-DRAM access transistors to achieve a delicate balance between reducing charge loss and maintaining carrier mobility. We developed a robust modeling methodology to quantify both the charge loss induced by the floating body effect (FBE) and the carrier mobility limited by surface roughness (SR). Our investigation carefully examines how thinning the transistor channel can mitigate FBE while avoiding adverse effects on surface scattering of charge carriers, all while considering the emerging geometry confinement effect. Through meticulous analysis, we aim to identify the optimal channel thickness range for VS-DRAM transistors, offering essential insights for the advancement of high-density memory technologies.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"199-205"},"PeriodicalIF":2.9,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study demonstrates that memory window (MW) narrowing under low voltage is caused by fatigue (polarization decrease) and can be recovered, whereas that under high voltage is caused by interface degradation and is not easily recoverable. Furthermore, we have found that the electrical field across Hf0.5Zr0.5O2 (HZO) layer ( ${E}_{text {HZO}}$ ) is the key to determine the recoverable ferroelectric fatigue, while the voltage applied on the gate ( ${V}_{text {g}}$ ) is associated with the interface degradation. Thus, thin HZO ferroelectric FETs (FeFETs) can prevent severe interface degradation through low-voltage operation (low ${V}_{text {g}}$ ). Moreover, by systematically studying the endurance behavior and recovery strategies, we show that a recovery scheme with bipolar pulses with suitable voltage and short total time of a few microseconds is effective to recover MW narrowing of FeFETs due to ferroelectric fatigue. As a result, HZO thickness scaling is effective to achieve high endurance characteristics of FeFETs via recovery.
{"title":"Recovery Strategy of Fatigue-Limited Endurance in Si FeFETs With Thin HfZrO₂ Films","authors":"Zuocheng Cai;Zhenhong Liu;Yan-Kui Liang;Xueyang Han;Shin-Yi Min;Eishin Nako;Seong-Kun Cho;Chia-Tsong Chen;Mitsuru Takenaka;Kasidit Toprasertpong;Shinichi Takagi","doi":"10.1109/TED.2024.3493065","DOIUrl":"https://doi.org/10.1109/TED.2024.3493065","url":null,"abstract":"This study demonstrates that memory window (MW) narrowing under low voltage is caused by fatigue (polarization decrease) and can be recovered, whereas that under high voltage is caused by interface degradation and is not easily recoverable. Furthermore, we have found that the electrical field across Hf0.5Zr0.5O2 (HZO) layer (\u0000<inline-formula> <tex-math>${E}_{text {HZO}}$ </tex-math></inline-formula>\u0000) is the key to determine the recoverable ferroelectric fatigue, while the voltage applied on the gate (\u0000<inline-formula> <tex-math>${V}_{text {g}}$ </tex-math></inline-formula>\u0000) is associated with the interface degradation. Thus, thin HZO ferroelectric FETs (FeFETs) can prevent severe interface degradation through low-voltage operation (low \u0000<inline-formula> <tex-math>${V}_{text {g}}$ </tex-math></inline-formula>\u0000). Moreover, by systematically studying the endurance behavior and recovery strategies, we show that a recovery scheme with bipolar pulses with suitable voltage and short total time of a few microseconds is effective to recover MW narrowing of FeFETs due to ferroelectric fatigue. As a result, HZO thickness scaling is effective to achieve high endurance characteristics of FeFETs via recovery.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"467-473"},"PeriodicalIF":2.9,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To minimize the rise time and full-width at half-maximum (FWHM) of the output waveform, we have designed and fabricated a novel integrated device based on semi-insulated silicon carbide (SiC) material, which we call cPCSS device, whose structure includes a photoconductive semiconductor switch (PCSS) and a charging capacitor. Test results indicate that, owing to optimized circuit connections and a simplified electrical length in cPCSS, the parasitic capacitance and inductance in the test circuit are decreased. Consequently, the cPCSS device exhibits faster signal while maintaining basically equal conductivity. At the incident laser energy ( $10~mu $ J), cPCSS obtains the output signal with the fastest rise time of 122 ps (10%–90%) and FWHM of 375 ps. In addition, the cPCSS device can maintain a peak output voltage exceeding 10 kV and continuously output signals for more than 180 000 times without any faults.
{"title":"Ultrafast Characteristics of Integrated High-Power Photoconductive Semiconductor Switch Based on 4H-SiC Substrate","authors":"Yangfan Li;Longfei Xiao;Chongbiao Luan;Xun Sun;Huiru Sha;Jian Jiao;Biao Yang;Deqiang Li;Yan Qin;Xiufang Chen;Hongtao Li;Xiangang Xu","doi":"10.1109/TED.2024.3492149","DOIUrl":"https://doi.org/10.1109/TED.2024.3492149","url":null,"abstract":"To minimize the rise time and full-width at half-maximum (FWHM) of the output waveform, we have designed and fabricated a novel integrated device based on semi-insulated silicon carbide (SiC) material, which we call cPCSS device, whose structure includes a photoconductive semiconductor switch (PCSS) and a charging capacitor. Test results indicate that, owing to optimized circuit connections and a simplified electrical length in cPCSS, the parasitic capacitance and inductance in the test circuit are decreased. Consequently, the cPCSS device exhibits faster signal while maintaining basically equal conductivity. At the incident laser energy (\u0000<inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>\u0000J), cPCSS obtains the output signal with the fastest rise time of 122 ps (10%–90%) and FWHM of 375 ps. In addition, the cPCSS device can maintain a peak output voltage exceeding 10 kV and continuously output signals for more than 180 000 times without any faults.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"128-134"},"PeriodicalIF":2.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-12DOI: 10.1109/TED.2024.3487821
Yu Heng Deng;Rui Su;Weichao Jiang;Hao Sun;Qing He Wang;Lu Liu;Jingping Xu;Peter T. Lai
A hybrid wet transfer method for the fabrication of MoS2 field-effect transistor (FET) array is demonstrated by using polymethyl methacrylate (PMMA) support and hydrofluoric (HF) assistance, which significantly reduces the fabrication complexity and cost. The MoS2FET array is fabricated with amorphous HfO2 as a gate dielectric, undoped CVD monolayer MoS2 as a conduction channel, and Ag as source/drain (S/D) electrodes. Transmission electron microscopy, Raman spectroscopy, and photoluminescence spectrum confirm the integrity of the monolayer MoS2 film and the well-fit, damage-free interface between MoS2 and Ag or HfO2, demonstrating the feasibility of this transfer method. The FET exhibits an impressive on-off current ratio of up to $3.1 times 10^{{8}}$ at a drain voltage ( ${V}_{text {DS}}$ ) of 1 V and a substantial on-current up to $271 ; mu $ A $mu $ m $^{-{1}}$ at ${V}_{text {DS}} = 3$ V and gate voltage = 5 V. The electrical measurements of 200 transistors show a low threshold voltage of 0.72 V with a standard deviation of 0.17 V and a high field-effect mobility of 69.9 cm $^{{2}}cdot text {V}^{-{1}}cdot text {s}^{-{1}}$ with a standard deviation of 9.8 cm $^{{2}}cdot text {V}^{-{1}}cdot text {s}^{-{1}}$ . Furthermore, the devices exhibit a low contact resistance of 1.49 k $Omega cdot mu $ m with a standard deviation of 0.33 k $Omega $ , indicating good electrical uniformity and exceptional performance for the Ag S/D electrodes.
采用聚甲基丙烯酸甲酯（PMMA）为载体，氢氟酸（HF）为助剂，提出了一种制备MoS2场效应晶体管（FET）阵列的混合湿转移方法，大大降低了制备的复杂性和成本。该MoS2FET阵列采用非晶态HfO2作为栅极介质，未掺杂CVD单层MoS2作为导通通道，Ag作为源极/漏极（S/D）电极。透射电子显微镜、拉曼光谱和光致发光光谱证实了MoS2单层膜的完整性，以及MoS2与Ag或HfO2之间良好贴合、无损伤的界面，证明了该转移方法的可行性。在漏极电压（${V}_{text {DS}}$）为1 V时，FET的通断电流比高达$3.1 times 10^{{8}}$，在${V}_{text {DS}} = 3$ V和栅极电压= 5 V时，通断电流高达$271 ; mu $ a $mu $ m $^{-{1}}$。对200个晶体管的电学测量结果表明，其阈值电压为0.72 V，标准差为0.17 V，场效应迁移率为69.9 cm $^{{2}}cdot text {V}^{-{1}}cdot text {s}^{-{1}}$，标准差为9.8 cm $^{{2}}cdot text {V}^{-{1}}cdot text {s}^{-{1}}$。此外，该器件具有1.49 k $Omega cdot mu $ m的低接触电阻，标准偏差为0.33 k $Omega $，表明银S/D电极具有良好的电均匀性和卓越的性能。
{"title":"Improved Electrical Uniformity and Performance via Low-Cost Hybrid Wet Transfer Method for van der Waals Source/Drain Contact Formation in MoS₂ Field-Effect Transistors","authors":"Yu Heng Deng;Rui Su;Weichao Jiang;Hao Sun;Qing He Wang;Lu Liu;Jingping Xu;Peter T. Lai","doi":"10.1109/TED.2024.3487821","DOIUrl":"https://doi.org/10.1109/TED.2024.3487821","url":null,"abstract":"A hybrid wet transfer method for the fabrication of MoS2 field-effect transistor (FET) array is demonstrated by using polymethyl methacrylate (PMMA) support and hydrofluoric (HF) assistance, which significantly reduces the fabrication complexity and cost. The MoS2FET array is fabricated with amorphous HfO2 as a gate dielectric, undoped CVD monolayer MoS2 as a conduction channel, and Ag as source/drain (S/D) electrodes. Transmission electron microscopy, Raman spectroscopy, and photoluminescence spectrum confirm the integrity of the monolayer MoS2 film and the well-fit, damage-free interface between MoS2 and Ag or HfO2, demonstrating the feasibility of this transfer method. The FET exhibits an impressive on-off current ratio of up to \u0000<inline-formula> <tex-math>$3.1 times 10^{{8}}$ </tex-math></inline-formula>\u0000 at a drain voltage (\u0000<inline-formula> <tex-math>${V}_{text {DS}}$ </tex-math></inline-formula>\u0000) of 1 V and a substantial on-current up to \u0000<inline-formula> <tex-math>$271 ; mu $ </tex-math></inline-formula>\u0000A\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m\u0000<inline-formula> <tex-math>$^{-{1}}$ </tex-math></inline-formula>\u0000 at \u0000<inline-formula> <tex-math>${V}_{text {DS}} = 3$ </tex-math></inline-formula>\u0000 V and gate voltage = 5 V. The electrical measurements of 200 transistors show a low threshold voltage of 0.72 V with a standard deviation of 0.17 V and a high field-effect mobility of 69.9 cm\u0000<inline-formula> <tex-math>$^{{2}}cdot text {V}^{-{1}}cdot text {s}^{-{1}}$ </tex-math></inline-formula>\u0000 with a standard deviation of 9.8 cm\u0000<inline-formula> <tex-math>$^{{2}}cdot text {V}^{-{1}}cdot text {s}^{-{1}}$ </tex-math></inline-formula>\u0000. Furthermore, the devices exhibit a low contact resistance of 1.49 k\u0000<inline-formula> <tex-math>$Omega cdot mu $ </tex-math></inline-formula>\u0000m with a standard deviation of 0.33 k\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, indicating good electrical uniformity and exceptional performance for the Ag S/D electrodes.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7943-7947"},"PeriodicalIF":2.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-12DOI: 10.1109/TED.2024.3487080
P. Zhao;L. Witters;A. Jourdain;M. Stucchi;N. Jourdan;J. W. Maes;H. Bana;C. Zhu;R. Chukka;F. Sebaai;K. Vandersmissen;N. Heylen;D. Montero;S. Wang;K. D’Havé;F. Schleicher;J. De Vos;G. Beyer;A. Miller;E. Beyne
Backside power delivery network (BSPDN) has gained much attention due to its potential to independently optimize signal and power routing. In this work, long slit nano through silicon vias (nTSVs) is used for high-density connections between frontside (FS)-patterned buried power rails (BPRs) and orthogonally patterned metal rails on the wafer backside (BS). These nTSVs are in situ patterned on top of BPR with self-alignment using FS lithography, and the length of the slits can also be tuned. This design relaxes overlay requirements for BS patterning that are typically stringent due to wafer grid distortions during bonding. Additionally, extreme wafer thinning stopping on a 10 nm Si0.75Ge0.25 etch stop layer (ESL) is enabled using an optimized thinning sequence with excellent total thickness variation (TTV) control. For the first time, low resistance barrier-free Molybdenum (Mo)-filled nTSVs are demonstrated, confirming the potential for further scaling compared to TiN/W-filled counterparts.
{"title":"Backside Power Delivery With Relaxed Overlay for Backside Patterning Using Extreme Wafer Thinning and Molybdenum-Filled Slit Nano Through Silicon Vias","authors":"P. Zhao;L. Witters;A. Jourdain;M. Stucchi;N. Jourdan;J. W. Maes;H. Bana;C. Zhu;R. Chukka;F. Sebaai;K. Vandersmissen;N. Heylen;D. Montero;S. Wang;K. D’Havé;F. Schleicher;J. De Vos;G. Beyer;A. Miller;E. Beyne","doi":"10.1109/TED.2024.3487080","DOIUrl":"https://doi.org/10.1109/TED.2024.3487080","url":null,"abstract":"Backside power delivery network (BSPDN) has gained much attention due to its potential to independently optimize signal and power routing. In this work, long slit nano through silicon vias (nTSVs) is used for high-density connections between frontside (FS)-patterned buried power rails (BPRs) and orthogonally patterned metal rails on the wafer backside (BS). These nTSVs are in situ patterned on top of BPR with self-alignment using FS lithography, and the length of the slits can also be tuned. This design relaxes overlay requirements for BS patterning that are typically stringent due to wafer grid distortions during bonding. Additionally, extreme wafer thinning stopping on a 10 nm Si0.75Ge0.25 etch stop layer (ESL) is enabled using an optimized thinning sequence with excellent total thickness variation (TTV) control. For the first time, low resistance barrier-free Molybdenum (Mo)-filled nTSVs are demonstrated, confirming the potential for further scaling compared to TiN/W-filled counterparts.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7963-7969"},"PeriodicalIF":2.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Scalability and the absence of moving components are excellent advantages for integrated thermoelectric (TE) devices in microelectronic applications. Both TE coolers (TECs) and TE generators (TEGs) could enhance computer chip efficiency and reliability. We show the fabrication of CMOS-compatible silicon-germanium (SiGe)-based TEC and TEG multistage structures for lateral temperature gradients with microelectronic manufacturing processes on 300-mm wafers. The smallest structures have a size of 1500 $times $ 500 nm and achieved a cooling temperature difference of around 0.13 K. The TEGs of equal dimensions reached a maximum voltage factor of 545 mV $cdot $ mm $^{-{2}} cdot $ K $^{-{1}}$ and a specific power generation factor of 2.1 nW $cdot $ mm $^{-{2}} cdot $ K $^{-{2}}$ near room temperature. Three different n-type SiGe materials were compared and examined regarding their TE properties. To address the challenge of contacting the TE element, we have captured and analyzed transmission electron microscopy (TEM) images for defect identification.
可扩展性和无运动元件是集成热电（TE）器件在微电子应用中的优异优势。TE冷却器（tec）和TE发生器（teg）都可以提高计算机芯片的效率和可靠性。我们展示了在300毫米晶圆上采用微电子制造工艺制造的用于横向温度梯度的cmos兼容硅锗（SiGe）基TEC和TEG多级结构。最小的结构尺寸为1500 × 500 nm，冷却温差约为0.13 K。等维teg在室温下的最大电压因子为545 mV $cdot $ mm $^{-{2}} cdot $ K $^{-{1}}$，比功率因子为2.1 nW $cdot $ mm $^{-{2}} cdot $ K $^{-{2}}$。对三种不同的n型SiGe材料的TE性能进行了比较和研究。为了解决接触TE元素的挑战，我们捕获并分析了透射电子显微镜（TEM）图像以进行缺陷识别。
{"title":"Embedded Silicon-Germanium-Based Thermoelectric Devices on 300-mm Wafer","authors":"C. Schwinge;R. Hoffmann;K. Biedermann;M. Czernohorsky;J. Kannan;M. Rudolph;F. Mende;M. Wagner-Reetz;G. Gerlach;W. Weinreich","doi":"10.1109/TED.2024.3482259","DOIUrl":"https://doi.org/10.1109/TED.2024.3482259","url":null,"abstract":"Scalability and the absence of moving components are excellent advantages for integrated thermoelectric (TE) devices in microelectronic applications. Both TE coolers (TECs) and TE generators (TEGs) could enhance computer chip efficiency and reliability. We show the fabrication of CMOS-compatible silicon-germanium (SiGe)-based TEC and TEG multistage structures for lateral temperature gradients with microelectronic manufacturing processes on 300-mm wafers. The smallest structures have a size of 1500 \u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 500 nm and achieved a cooling temperature difference of around 0.13 K. The TEGs of equal dimensions reached a maximum voltage factor of 545 mV\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000mm\u0000<inline-formula> <tex-math>$^{-{2}} cdot $ </tex-math></inline-formula>\u0000K\u0000<inline-formula> <tex-math>$^{-{1}}$ </tex-math></inline-formula>\u0000 and a specific power generation factor of 2.1 nW\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000mm\u0000<inline-formula> <tex-math>$^{-{2}} cdot $ </tex-math></inline-formula>\u0000K\u0000<inline-formula> <tex-math>$^{-{2}}$ </tex-math></inline-formula>\u0000 near room temperature. Three different n-type SiGe materials were compared and examined regarding their TE properties. To address the challenge of contacting the TE element, we have captured and analyzed transmission electron microscopy (TEM) images for defect identification.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7794-7801"},"PeriodicalIF":2.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10750481","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-12DOI: 10.1109/TED.2024.3489603
Yifei Chang;Jiaxuan Wang;Hao Guan;Pan Liu
Power electronics are widely used in new energy vehicles, photovoltaics, and other fields. Its robustness has been concerned, and short-circuit robustness is an essential part of it, which is worth in-depth research. In this work, a 1200-V Trench-field-stop (FS) insulated-gate bipolar transistor (IGBT) was focused on for its short-circuit safe operating area (SCSOA) capability analysis. First, a model based on the actual process flow was set up, aligned with the scanning electron microscope (SEM) results, with the discrepancy between its static and dynamic electrical characteristics controlled within 5% and 12%, respectively. Subsequently, two primary failure modes and mechanisms of the device under test (DUT) under short-circuit conditions were identified, analyzed through TCAD modeling, and verified through actual short-circuit tests. Finally, the Technique for Order of Preference by Similarity to Ideal Solution (TOPSIS) method for multiple-criteria decision-making (MCDM) was applied to optimize the SCSOA, enhancing the short-circuit robustness of the device by 4% with minimal loss to other electrical performances.
{"title":"1200-V Trench-FS IGBT: Process-Based Modeling and Short-Circuit Safe Operating Area (SCSOA) Optimization With the TOPSIS Method","authors":"Yifei Chang;Jiaxuan Wang;Hao Guan;Pan Liu","doi":"10.1109/TED.2024.3489603","DOIUrl":"https://doi.org/10.1109/TED.2024.3489603","url":null,"abstract":"Power electronics are widely used in new energy vehicles, photovoltaics, and other fields. Its robustness has been concerned, and short-circuit robustness is an essential part of it, which is worth in-depth research. In this work, a 1200-V Trench-field-stop (FS) insulated-gate bipolar transistor (IGBT) was focused on for its short-circuit safe operating area (SCSOA) capability analysis. First, a model based on the actual process flow was set up, aligned with the scanning electron microscope (SEM) results, with the discrepancy between its static and dynamic electrical characteristics controlled within 5% and 12%, respectively. Subsequently, two primary failure modes and mechanisms of the device under test (DUT) under short-circuit conditions were identified, analyzed through TCAD modeling, and verified through actual short-circuit tests. Finally, the Technique for Order of Preference by Similarity to Ideal Solution (TOPSIS) method for multiple-criteria decision-making (MCDM) was applied to optimize the SCSOA, enhancing the short-circuit robustness of the device by 4% with minimal loss to other electrical performances.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7716-7726"},"PeriodicalIF":2.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142790240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dispersive effects such as trapping play a vital role in determining the performance of AlGaN/gallium nitride (GaN) high-electron mobility transistors (HEMTs) for RF and power applications—necessitating accurate modeling for robust circuit designs. This work presents a rigorous SPICE model to capture the transient and large-signal impact of traps in AlGaN/GaN HEMTs. The model has been implemented in the industry-standard ASM-HEMT compact-model framework. The model accurately accounts for the variation in threshold voltage and change in 2DEG charge carrier concentration in the source- and drain-side access regions under various drain-lag and gate-lag quiescent conditions. Threshold voltage and 2DEG charge carrier concentration at the source- and drain-side access regions show a linear dependence on drain-lag and gate-lag quiescent conditions, respectively. The results obtained using the developed model are in good agreement with the measured data. This model is valid for transient current simulations at different quiescent conditions and accurately captures the large-signal behavior at the optimal load impedance. Finally, pulsed IV characteristics at different temperatures have been validated against device measurements.
{"title":"A Broadband and Transient-Accurate AlGaN/GaN HEMT SPICE Model for X-Band RF Applications","authors":"Raghvendra Dangi;Ahtisham Pampori;Praveen Pal;Mohammad Sajid Nazir;Pragya Kushwaha;Yogesh Singh Chauhan","doi":"10.1109/TED.2024.3487959","DOIUrl":"https://doi.org/10.1109/TED.2024.3487959","url":null,"abstract":"Dispersive effects such as trapping play a vital role in determining the performance of AlGaN/gallium nitride (GaN) high-electron mobility transistors (HEMTs) for RF and power applications—necessitating accurate modeling for robust circuit designs. This work presents a rigorous SPICE model to capture the transient and large-signal impact of traps in AlGaN/GaN HEMTs. The model has been implemented in the industry-standard ASM-HEMT compact-model framework. The model accurately accounts for the variation in threshold voltage and change in 2DEG charge carrier concentration in the source- and drain-side access regions under various drain-lag and gate-lag quiescent conditions. Threshold voltage and 2DEG charge carrier concentration at the source- and drain-side access regions show a linear dependence on drain-lag and gate-lag quiescent conditions, respectively. The results obtained using the developed model are in good agreement with the measured data. This model is valid for transient current simulations at different quiescent conditions and accurately captures the large-signal behavior at the optimal load impedance. Finally, pulsed IV characteristics at different temperatures have been validated against device measurements.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7390-7397"},"PeriodicalIF":2.9,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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