We proposed an effective strategy involving a differential distribution of voltages among dynodes to significantly enhance the gain and stability of discrete dynode electron multipliers (DEMs) under continuous electron bombardment. The effects of the differential voltage distribution on the DEM performance were systematically investigated through experiments and numerical simulations. The differential voltage distribution of 7:7:7:7:7:5:5:5:5 enables the DEM to achieve a gain of $3.4times 10^{{4}}$ , representing a substantial increase by 2.1 times at an operating voltage of 1200 V, and the operating voltage at a gain of 106 to be reduced to 1949 V with a decrease of 186 V in comparison to the traditional uniform voltage distribution of 1:1:1:1:1:1:1:1:1. The gain enhancement is closely related to the increased average secondary electron emission (SEE) coefficients of dynodes D2-D6 and the improved electron collection efficiencies of dynodes D3 and D6. Additionally, the differential voltage also reduced the gain decay rate to 16.7%/mC, reflecting a decrease of 14.8% due to the suppression of SEE degradations in dynodes D7-D9, which can be attributed to their lower average SEE coefficients. Overall, the proposed strategy of differential voltage distribution, characterized by higher voltages among earlier dynodes and lower voltages among latter dynodes, presents a novel and universal approach for optimizing the structure of electron multipliers, addressing the need for highly sensitive and reliable detection of ultraweak or even single charged particles.
{"title":"Enhancement of the Gain and Stability in a Discrete Dynode Electron Multiplier Through Differential Voltage Distribution Among Dynodes","authors":"Jishi Yang;Jie Li;Wanru Zhao;Li He;Ruozheng Wang;Yuan Zhao;Wenbo Hu;Jinshou Tian;Shengli Wu","doi":"10.1109/TED.2024.3503536","DOIUrl":"https://doi.org/10.1109/TED.2024.3503536","url":null,"abstract":"We proposed an effective strategy involving a differential distribution of voltages among dynodes to significantly enhance the gain and stability of discrete dynode electron multipliers (DEMs) under continuous electron bombardment. The effects of the differential voltage distribution on the DEM performance were systematically investigated through experiments and numerical simulations. The differential voltage distribution of 7:7:7:7:7:5:5:5:5 enables the DEM to achieve a gain of \u0000<inline-formula> <tex-math>$3.4times 10^{{4}}$ </tex-math></inline-formula>\u0000, representing a substantial increase by 2.1 times at an operating voltage of 1200 V, and the operating voltage at a gain of 106 to be reduced to 1949 V with a decrease of 186 V in comparison to the traditional uniform voltage distribution of 1:1:1:1:1:1:1:1:1. The gain enhancement is closely related to the increased average secondary electron emission (SEE) coefficients of dynodes D2-D6 and the improved electron collection efficiencies of dynodes D3 and D6. Additionally, the differential voltage also reduced the gain decay rate to 16.7%/mC, reflecting a decrease of 14.8% due to the suppression of SEE degradations in dynodes D7-D9, which can be attributed to their lower average SEE coefficients. Overall, the proposed strategy of differential voltage distribution, characterized by higher voltages among earlier dynodes and lower voltages among latter dynodes, presents a novel and universal approach for optimizing the structure of electron multipliers, addressing the need for highly sensitive and reliable detection of ultraweak or even single charged particles.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"439-444"},"PeriodicalIF":2.9,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A junctionless ferroelectric thin-film transistor (JL-FeTFT) that combines a highly doped polycrystalline-silicon (poly-Si) channel with a ferroelectric gate insulator is proposed and investigates its nonvolatile memory (NVM) characteristics for application in high-density vertically stacked memory structures in neuromorphic computing. Compared to the conventional inversion mode FeTFT (IM-FeTFT) with undoped poly-Si channel, the JL-FeTFT demonstrates significant advantages. First, the JL-FeTFT operates at a lower voltage due to the higher electron concentration in the channel, resulting in a reduction of the threshold voltage ( ${V} _{text {TH}}$ ) by 0.522 V. Second, the transconductance of JL-FeTFT is 6.28 times higher than that of IM-FeTFT. Additionally, the ${V} _{text {TH}}$ modulation in JL-FeTFT is significantly higher than in IM-FeTFT across various pulse widths, particularly excelling under short pulse widths and low operating voltages. Furthermore, the JL-FeTFT exhibits endurance of $2times 10^{{5}}$ cycles at a 300 ns pulsewidth, substantially surpassing the $5times 10^{{4}}$ cycles of the IM-FeTFT. The JL-FeTFT also shows better stability and reliability, with a smaller reduction in the memory window (MW) after up to 106 program/erase (PRG/ERS) cycles. Moreover, after 106 PRG/ERS cycles, the JL-FeTFT maintains lower degradation in ON-current, subthreshold swing (SS), and transconductance compared to the IM-FeTFT. Additionally, the JL-FeTFT operates at lower voltages and achieves endurance of 105 cycles at a 100 ns pulsewidth, making it suitable for high-speed and low-voltage NVM applications. Consequently, the JL-FeTFT demonstrates advantages in terms of low operating voltage, high ON-current, excellent endurance, and reliability, positioning it as a promising candidate for future high-density and high-performance memory.
{"title":"High-Performance Junctionless Ferroelectric Thin-Film Transistor for Low-Voltage and High-Speed Nonvolatile Memory Applications","authors":"William Cheng-Yu Ma;Chun-Jung Su;Kuo-Hsing Kao;Yu-Chieh Yen;Ji-Min Yang;Yi-Han Li;Yen-Chen Chen;Jhe-Yu Lin;Hui-Wen Chang","doi":"10.1109/TED.2024.3503539","DOIUrl":"https://doi.org/10.1109/TED.2024.3503539","url":null,"abstract":"A junctionless ferroelectric thin-film transistor (JL-FeTFT) that combines a highly doped polycrystalline-silicon (poly-Si) channel with a ferroelectric gate insulator is proposed and investigates its nonvolatile memory (NVM) characteristics for application in high-density vertically stacked memory structures in neuromorphic computing. Compared to the conventional inversion mode FeTFT (IM-FeTFT) with undoped poly-Si channel, the JL-FeTFT demonstrates significant advantages. First, the JL-FeTFT operates at a lower voltage due to the higher electron concentration in the channel, resulting in a reduction of the threshold voltage (\u0000<inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula>\u0000) by 0.522 V. Second, the transconductance of JL-FeTFT is 6.28 times higher than that of IM-FeTFT. Additionally, the \u0000<inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula>\u0000 modulation in JL-FeTFT is significantly higher than in IM-FeTFT across various pulse widths, particularly excelling under short pulse widths and low operating voltages. Furthermore, the JL-FeTFT exhibits endurance of \u0000<inline-formula> <tex-math>$2times 10^{{5}}$ </tex-math></inline-formula>\u0000 cycles at a 300 ns pulsewidth, substantially surpassing the \u0000<inline-formula> <tex-math>$5times 10^{{4}}$ </tex-math></inline-formula>\u0000 cycles of the IM-FeTFT. The JL-FeTFT also shows better stability and reliability, with a smaller reduction in the memory window (MW) after up to 106 program/erase (PRG/ERS) cycles. Moreover, after 106 PRG/ERS cycles, the JL-FeTFT maintains lower degradation in ON-current, subthreshold swing (SS), and transconductance compared to the IM-FeTFT. Additionally, the JL-FeTFT operates at lower voltages and achieves endurance of 105 cycles at a 100 ns pulsewidth, making it suitable for high-speed and low-voltage NVM applications. Consequently, the JL-FeTFT demonstrates advantages in terms of low operating voltage, high ON-current, excellent endurance, and reliability, positioning it as a promising candidate for future high-density and high-performance memory.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"247-252"},"PeriodicalIF":2.9,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/TED.2024.3503534
Xinyi Huang;Huihui Wang;Laqun Liu;Dagang Liu;Zhijie Li
An electromagnetic particle-in-cell (PIC) simulation technique is used to analyze multipactor discharge on a dielectric with a beat wave composed of multiple high-power microwaves (HPMs) with similar frequencies. Unlike the single-frequency HPM, the strength of ${E}_{text {n}}$ of the multipactor with a beat wave fluctuates greatly with time, resulting in the root-mean-square value of ${E}_{text {n}}$ (strongly related to the average deposition power) being significantly greater than the absolute value of the arithmetic mean of ${E}_{text {n}}$ (the traditional indicator of the multipactor strength), where ${E}_{text {n}}$ is the electric field due to the deposited charges induced by multipactor. In this article, the influence of double-frequency and triple-frequency beat waves on multipactor is studied from the perspective of the root-mean-square value and absolute value of the arithmetic mean of ${E}_{text {n}}$ . The results show that the strong multipactor with a beat wave is unaffected by the spectra of the beat wave and the beat wave cannot inhibit the strong multipactor strength in contrast to a single-frequency HPM with the same average microwave power while the inhibition effect of a beat wave on a moderated multipactor is obvious. Further analysis shows that the suppression effect of a beat wave on a moderated multipactor is greatest when both the frequencies and phases of the beat wave are arranged in an arithmetic progression and the moderated multipactor can also be suppressed substantially when the amplitudes of the beat wave deviate slightly from the condition of equal amplitude.
{"title":"Suppression of Multipactor Discharge on a Dielectric With a Beat Wave","authors":"Xinyi Huang;Huihui Wang;Laqun Liu;Dagang Liu;Zhijie Li","doi":"10.1109/TED.2024.3503534","DOIUrl":"https://doi.org/10.1109/TED.2024.3503534","url":null,"abstract":"An electromagnetic particle-in-cell (PIC) simulation technique is used to analyze multipactor discharge on a dielectric with a beat wave composed of multiple high-power microwaves (HPMs) with similar frequencies. Unlike the single-frequency HPM, the strength of \u0000<inline-formula> <tex-math>${E}_{text {n}}$ </tex-math></inline-formula>\u0000 of the multipactor with a beat wave fluctuates greatly with time, resulting in the root-mean-square value of \u0000<inline-formula> <tex-math>${E}_{text {n}}$ </tex-math></inline-formula>\u0000 (strongly related to the average deposition power) being significantly greater than the absolute value of the arithmetic mean of \u0000<inline-formula> <tex-math>${E}_{text {n}}$ </tex-math></inline-formula>\u0000 (the traditional indicator of the multipactor strength), where \u0000<inline-formula> <tex-math>${E}_{text {n}}$ </tex-math></inline-formula>\u0000 is the electric field due to the deposited charges induced by multipactor. In this article, the influence of double-frequency and triple-frequency beat waves on multipactor is studied from the perspective of the root-mean-square value and absolute value of the arithmetic mean of \u0000<inline-formula> <tex-math>${E}_{text {n}}$ </tex-math></inline-formula>\u0000. The results show that the strong multipactor with a beat wave is unaffected by the spectra of the beat wave and the beat wave cannot inhibit the strong multipactor strength in contrast to a single-frequency HPM with the same average microwave power while the inhibition effect of a beat wave on a moderated multipactor is obvious. Further analysis shows that the suppression effect of a beat wave on a moderated multipactor is greatest when both the frequencies and phases of the beat wave are arranged in an arithmetic progression and the moderated multipactor can also be suppressed substantially when the amplitudes of the beat wave deviate slightly from the condition of equal amplitude.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"445-452"},"PeriodicalIF":2.9,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/TED.2024.3496435
Zhiqiang Tian;Gang Zhang;Yuhua Huang;Shizhao Wang;Sheng Liu
The advent of 3-D NAND architecture has introduced new integration challenges, particularly regarding the impact of thermal-mechanical stress during manufacturing, which significantly affects device performance. This study establishes a 3-D NAND flash memory process mechanics model using a local representative volume element (RVE) finite element modeling framework. We thoroughly analyze the causes of warpage during the 3-D NAND manufacturing process and monitor the evolution of mechanical stress and related structural deformations. Additionally, we examine the deformation distribution under sequential processes and investigate how different process conditions impact asymmetric deformation. Our findings have potential significance for improving device structure reliability and optimizing process parameters in 3-D NAND memory manufacturing. By providing insights into stress evolution and deformation mechanisms, this work contributes to addressing the challenges associated with increasing storage density in 3-D NAND technology.
{"title":"Process Mechanics Model and Asymmetric Residual Stress Analysis During 3-D NAND Manufacturing","authors":"Zhiqiang Tian;Gang Zhang;Yuhua Huang;Shizhao Wang;Sheng Liu","doi":"10.1109/TED.2024.3496435","DOIUrl":"https://doi.org/10.1109/TED.2024.3496435","url":null,"abstract":"The advent of 3-D NAND architecture has introduced new integration challenges, particularly regarding the impact of thermal-mechanical stress during manufacturing, which significantly affects device performance. This study establishes a 3-D NAND flash memory process mechanics model using a local representative volume element (RVE) finite element modeling framework. We thoroughly analyze the causes of warpage during the 3-D NAND manufacturing process and monitor the evolution of mechanical stress and related structural deformations. Additionally, we examine the deformation distribution under sequential processes and investigate how different process conditions impact asymmetric deformation. Our findings have potential significance for improving device structure reliability and optimizing process parameters in 3-D NAND memory manufacturing. By providing insights into stress evolution and deformation mechanisms, this work contributes to addressing the challenges associated with increasing storage density in 3-D NAND technology.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"193-198"},"PeriodicalIF":2.9,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A normally-off high-performance hydrogenated diamond (H-diamond) field-effect transistor (FET) has been fabricated and investigated. The deep X-ray photoelectron spectroscopy (XPS) analysis reveals the Gd2O3/Gd double layer gate structure. The threshold voltage ( ${V}_{text {TH}}$ ) is up to −1.4 V with 6- $mu $ m gate length, which demonstrates the normally-off operation caused by the low work function of Gd and the fixed positive charge of Gd2O3 layer. The gate leakage current density J is as low as $5.8times 10^{-{6}}$ A/cm2 and ON/OFF ratio is as high as $10^{{10}}$ , which both can be due to the suppression by Gd2O3 layer. The maximum drain current density, transconductance, OFF-state drain leakage current, subthreshold swing, maximum gate oxide capacitance, and effective mobility with 6- $mu $ m gate length are −100 mA/mm, 18.9 mS/mm, $10^{-{8}}$ mA/mm, 121 mV/dec, $0.24~mu $ F/cm2, and 417.7 cm2/V $cdot $ s, respectively. The trapped charge density, fixed charge density, and interface state density are $4.87times 10^{{11}}$ cm $^{-{2}}$ , $3.57times 10^{{12}}$ cm $^{-{2}}$ , and $1.52times 10^{{12}}$ cm $^{-{2}}cdot $ eV $^{-{1}}$ , respectively. This work demonstrates a simple fabrication approach to achieve normally-off FET with large ${V}_{text {TH}}$ and low leakage current, which contributes to the advancement of diamond for circuit applications.
制备并研究了一种高性能常关氢化金刚石场效应晶体管（FET）。深x射线光电子能谱（XPS）分析揭示了Gd2O3/Gd双层栅结构。阈值电压（${V}_{text {TH}}$）高达- 1.4 V，栅极长度为6- $mu $ m，表明Gd的低功函数和Gd2O3层的固定正电荷导致了常关工作。栅极漏电流密度J低至$5.8 × 10^{-{6}}$ A/cm2， ON/OFF比高至$10^{{10}}$，均可归因于Gd2O3层的抑制作用。最大漏极电流密度、跨导、关断漏极漏电流、亚阈值摆幅、最大栅极氧化物电容和栅极长度为6- $ $ $ m时的有效迁移率分别为- 100 mA/mm、18.9 mS/mm、$10^{- $ {8}}$ mA/mm、121 mV/dec、$0.24~mu $ F/cm2和417.7 cm2/V $ $ cdot $ s。捕获电荷密度、固定电荷密度和界面态密度分别为$4.87乘以10^{{11}}$ cm $^{-{2}}$、$3.57乘以10^{{12}}$ cm $^{-{2}}$和$1.52乘以10^{{12}}$ cm $^{-{2}}cdot $ eV $^{-{1}}$。本工作展示了一种简单的制造方法来实现具有大${V}_{text {TH}}$和低漏电流的常关场效应管，这有助于推进金刚石在电路应用中的应用。
{"title":"Normally-Off High-Performance Diamond FET With Large VTH and Low Leakage Current","authors":"Yuesong Liang;Wei Wang;Tianlin Niu;Genqiang Chen;Fei Wang;Yuxiang Du;Minghui Zhang;Yanfeng Wang;Feng Wen;Hong-Xing Wang","doi":"10.1109/TED.2024.3496447","DOIUrl":"https://doi.org/10.1109/TED.2024.3496447","url":null,"abstract":"A normally-off high-performance hydrogenated diamond (H-diamond) field-effect transistor (FET) has been fabricated and investigated. The deep X-ray photoelectron spectroscopy (XPS) analysis reveals the Gd2O3/Gd double layer gate structure. The threshold voltage (\u0000<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>\u0000) is up to −1.4 V with 6-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m gate length, which demonstrates the normally-off operation caused by the low work function of Gd and the fixed positive charge of Gd2O3 layer. The gate leakage current density J is as low as \u0000<inline-formula> <tex-math>$5.8times 10^{-{6}}$ </tex-math></inline-formula>\u0000 A/cm2 and ON/OFF ratio is as high as \u0000<inline-formula> <tex-math>$10^{{10}}$ </tex-math></inline-formula>\u0000, which both can be due to the suppression by Gd2O3 layer. The maximum drain current density, transconductance, OFF-state drain leakage current, subthreshold swing, maximum gate oxide capacitance, and effective mobility with 6-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m gate length are −100 mA/mm, 18.9 mS/mm, \u0000<inline-formula> <tex-math>$10^{-{8}}$ </tex-math></inline-formula>\u0000 mA/mm, 121 mV/dec, \u0000<inline-formula> <tex-math>$0.24~mu $ </tex-math></inline-formula>\u0000F/cm2, and 417.7 cm2/V\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000s, respectively. The trapped charge density, fixed charge density, and interface state density are \u0000<inline-formula> <tex-math>$4.87times 10^{{11}}$ </tex-math></inline-formula>\u0000 cm\u0000<inline-formula> <tex-math>$^{-{2}}$ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$3.57times 10^{{12}}$ </tex-math></inline-formula>\u0000 cm\u0000<inline-formula> <tex-math>$^{-{2}}$ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$1.52times 10^{{12}}$ </tex-math></inline-formula>\u0000 cm\u0000<inline-formula> <tex-math>$^{-{2}}cdot $ </tex-math></inline-formula>\u0000eV\u0000<inline-formula> <tex-math>$^{-{1}}$ </tex-math></inline-formula>\u0000, respectively. This work demonstrates a simple fabrication approach to achieve normally-off FET with large \u0000<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>\u0000 and low leakage current, which contributes to the advancement of diamond for circuit applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"12-16"},"PeriodicalIF":2.9,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/TED.2024.3499945
Dan Zhang;Jiarong Liang;Han Cai;Weisen Li;Zhao Wang;Qijun Sun;Xingui Tang;Wei Zheng
Lutetium oxide (Lu2O3), an ultrawide bandgap (UWB) (5.5–6.2 eV) rare-Earth oxide, has been proposed as a potential material for constructing vacuum-ultraviolet (VUV) photodetectors. In this work, an ultrathin (4 nm) aluminum oxide (Al2O3) layer is deposited at the interface of Lu2O3/GaN heterojunction to fabricate a Lu2O3 VUV photovoltaic detector with high performance. At 0 V bias and under VUV illumination, the Lu2O3/Al2O3/GaN photodetector presents a photoresponsivity of 17.2 mA/W (at 192 nm), a decay time of 54.9 ms, and a detectivity of $1.2times 10^{{12}}$ Jones. The excellent performance of the device comes from the ultrathin Al2O3 layer deposited at the heterojunction interface, which not only acts as a buffer layer but also as a hole-blocking layer, improving the quality of the photosensitive layer and the separation efficiency of photo-generated carriers. Furthermore, with an increase in the thickness of the Al2O3 layer (>4 nm), a deterioration of optoelectronic properties of the Lu2O3/Al2O3/GaN device can be observed, which is attributed to an increase in the transport distance of the photo-generated carrier and a reduction in the probability of electron tunneling. This work can provide a reference for the preparation of high-performance Lu2O3-based VUV photovoltaic detectors in the future.
{"title":"Interface Engineering of Rare-Earth Oxide-GaN Heterojunction for Improving Vacuum-Ultraviolet Photodetection","authors":"Dan Zhang;Jiarong Liang;Han Cai;Weisen Li;Zhao Wang;Qijun Sun;Xingui Tang;Wei Zheng","doi":"10.1109/TED.2024.3499945","DOIUrl":"https://doi.org/10.1109/TED.2024.3499945","url":null,"abstract":"Lutetium oxide (Lu2O3), an ultrawide bandgap (UWB) (5.5–6.2 eV) rare-Earth oxide, has been proposed as a potential material for constructing vacuum-ultraviolet (VUV) photodetectors. In this work, an ultrathin (4 nm) aluminum oxide (Al2O3) layer is deposited at the interface of Lu2O3/GaN heterojunction to fabricate a Lu2O3 VUV photovoltaic detector with high performance. At 0 V bias and under VUV illumination, the Lu2O3/Al2O3/GaN photodetector presents a photoresponsivity of 17.2 mA/W (at 192 nm), a decay time of 54.9 ms, and a detectivity of \u0000<inline-formula> <tex-math>$1.2times 10^{{12}}$ </tex-math></inline-formula>\u0000 Jones. The excellent performance of the device comes from the ultrathin Al2O3 layer deposited at the heterojunction interface, which not only acts as a buffer layer but also as a hole-blocking layer, improving the quality of the photosensitive layer and the separation efficiency of photo-generated carriers. Furthermore, with an increase in the thickness of the Al2O3 layer (>4 nm), a deterioration of optoelectronic properties of the Lu2O3/Al2O3/GaN device can be observed, which is attributed to an increase in the transport distance of the photo-generated carrier and a reduction in the probability of electron tunneling. This work can provide a reference for the preparation of high-performance Lu2O3-based VUV photovoltaic detectors in the future.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"289-294"},"PeriodicalIF":2.9,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/TED.2024.3493056
Xuanming Zhang;Yuanlei Zhang;Jiachen Duan;Zhiwei Sun;Weisheng Wang;Ye Liang;Xuelin Yang;Lisheng Zhang;Zhenghao Chen;Jie Zhang;Kain Lu Low;Wen Liu
This article presents the enhancement-mode (E-mode) GaN p-channel heterojunction field-effect transistors (p-FETs) with p-Al0.05Ga0.95N etching-target layer (ETL). The optimized high-selectivity etching technique achieves an etch rate of approximately 1 nm/min for p-GaN, while also generating a selectivity ratio of 4:1 between p-GaN and p-Al0.05Ga0.95N. High-yield E-mode p-FET with ETL has been obtained as the etching process window was expanded to 10 min. The devices achieved the characteristics of a threshold voltage ( ${V}_{text {th}}$ ) of −1.15 V and a maximum current density ( ${I}_{{D},max }$ ) of 6.16 mA/mm. Furthermore, the characteristics of multiple devices demonstrate the high consistency and reproducibility of p-FETs’ ${V}_{text {th}}$ and ${I}_{text {ON}}$ , thus providing significant opportunities for developing complementary circuit integration.
{"title":"High-Yield Enhancement-Mode GaN p-FET With Etching-Target Layer and High-Selectivity Etching Techniques","authors":"Xuanming Zhang;Yuanlei Zhang;Jiachen Duan;Zhiwei Sun;Weisheng Wang;Ye Liang;Xuelin Yang;Lisheng Zhang;Zhenghao Chen;Jie Zhang;Kain Lu Low;Wen Liu","doi":"10.1109/TED.2024.3493056","DOIUrl":"https://doi.org/10.1109/TED.2024.3493056","url":null,"abstract":"This article presents the enhancement-mode (E-mode) GaN p-channel heterojunction field-effect transistors (p-FETs) with p-Al0.05Ga0.95N etching-target layer (ETL). The optimized high-selectivity etching technique achieves an etch rate of approximately 1 nm/min for p-GaN, while also generating a selectivity ratio of 4:1 between p-GaN and p-Al0.05Ga0.95N. High-yield E-mode p-FET with ETL has been obtained as the etching process window was expanded to 10 min. The devices achieved the characteristics of a threshold voltage (\u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000) of −1.15 V and a maximum current density (\u0000<inline-formula> <tex-math>${I}_{{D},max }$ </tex-math></inline-formula>\u0000) of 6.16 mA/mm. Furthermore, the characteristics of multiple devices demonstrate the high consistency and reproducibility of p-FETs’ \u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>\u0000, thus providing significant opportunities for developing complementary circuit integration.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"312-316"},"PeriodicalIF":2.9,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/TED.2024.3499941
Han-Lin Zhao;Sung-Jin Kim
The p-type conductivity often observed in single-wall carbon nanotube (SW-CNT) thin-film transistors (TFTs) is usually attributed to the doping effect of oxygen adsorption when SW-CNT are exposed to air caused by differences in the figure of merit, which results in asymmetric electron and hole injection. We performed comparative tests by doping SW-CNTs into the Indium oxide (In2O3/SW-CNT) channel layer, fabricated semiconductor devices, and investigated the device performance and film properties. It was determined that both In2O3 and In2O3/SW-CNT devices exhibit n-type behavior with significant saturation behavior and gate control under positive bias. The In2O3/SW-CNT TFTs have higher saturation mobility ( $mu _{text {sat}}$ ) and on/off current ratio ( ${I}_{text {ON}}/{I}_{text {OFF}}$ ). In particular, the $mu _{text {sat}}$ is increased by ~3 times, and the ${I}_{text {ON}}/{I}_{text {OFF}}$ is increased to $sim 10^{{6}}$ . Also, under negative bias stress (NBS), it exhibits better stability and signal inversion capability by resistive loading of the inverter. These results indicate that solution-prepared In2O3/SW-CNT TFTs can be used in low-cost, low-temperature, high-performance electronic devices.
{"title":"Effect of Single-Wall Carbon Nanotube Doping on Solution-Processed Indium Oxide Thin-Film Transistors","authors":"Han-Lin Zhao;Sung-Jin Kim","doi":"10.1109/TED.2024.3499941","DOIUrl":"https://doi.org/10.1109/TED.2024.3499941","url":null,"abstract":"The p-type conductivity often observed in single-wall carbon nanotube (SW-CNT) thin-film transistors (TFTs) is usually attributed to the doping effect of oxygen adsorption when SW-CNT are exposed to air caused by differences in the figure of merit, which results in asymmetric electron and hole injection. We performed comparative tests by doping SW-CNTs into the Indium oxide (In2O3/SW-CNT) channel layer, fabricated semiconductor devices, and investigated the device performance and film properties. It was determined that both In2O3 and In2O3/SW-CNT devices exhibit n-type behavior with significant saturation behavior and gate control under positive bias. The In2O3/SW-CNT TFTs have higher saturation mobility (\u0000<inline-formula> <tex-math>$mu _{text {sat}}$ </tex-math></inline-formula>\u0000) and on/off current ratio (\u0000<inline-formula> <tex-math>${I}_{text {ON}}/{I}_{text {OFF}}$ </tex-math></inline-formula>\u0000). In particular, the \u0000<inline-formula> <tex-math>$mu _{text {sat}}$ </tex-math></inline-formula>\u0000 is increased by ~3 times, and the \u0000<inline-formula> <tex-math>${I}_{text {ON}}/{I}_{text {OFF}}$ </tex-math></inline-formula>\u0000 is increased to \u0000<inline-formula> <tex-math>$sim 10^{{6}}$ </tex-math></inline-formula>\u0000. Also, under negative bias stress (NBS), it exhibits better stability and signal inversion capability by resistive loading of the inverter. These results indicate that solution-prepared In2O3/SW-CNT TFTs can be used in low-cost, low-temperature, high-performance electronic devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"271-276"},"PeriodicalIF":2.9,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-26DOI: 10.1109/TED.2024.3499934
Kejun Xia
In this article, we present a method to analytically model the subthreshold swing (SS) in bulk MOSFET compact models down to cryogenic temperatures by incorporating interface states into the surface potential equation (SPE). The impact of the interface states is captured by a gate voltage shift. To derive a close-form solution, the shift is first calculated for the actively charging region of the gate voltage using a linear approximation of the interface states. The shift is then smoothly clamped to zero at lower gate voltages, where the interface states are empty, and to a saturated value at higher gate voltages, where the interface states are fully charged. This approach differs from the empirical or behavioral methods typically used in compact models. The method effectively models the SS and its saturation at cryogenic temperatures and has been validated with measurement data down to 4.2 K in an n-channel Si MOSFET from a 28-nm bulk CMOS process for both linear and saturation regions. This method does not account for the band-tail effect, and self-heating is not considered, as it is negligible in the subthreshold region. The approach is straightforward and can be easily applied to other types of MOSFETs.
{"title":"Subthreshold Swing Modeling Down to Cryogenic Temperatures for MOSFET Compact Models","authors":"Kejun Xia","doi":"10.1109/TED.2024.3499934","DOIUrl":"https://doi.org/10.1109/TED.2024.3499934","url":null,"abstract":"In this article, we present a method to analytically model the subthreshold swing (SS) in bulk MOSFET compact models down to cryogenic temperatures by incorporating interface states into the surface potential equation (SPE). The impact of the interface states is captured by a gate voltage shift. To derive a close-form solution, the shift is first calculated for the actively charging region of the gate voltage using a linear approximation of the interface states. The shift is then smoothly clamped to zero at lower gate voltages, where the interface states are empty, and to a saturated value at higher gate voltages, where the interface states are fully charged. This approach differs from the empirical or behavioral methods typically used in compact models. The method effectively models the SS and its saturation at cryogenic temperatures and has been validated with measurement data down to 4.2 K in an n-channel Si MOSFET from a 28-nm bulk CMOS process for both linear and saturation regions. This method does not account for the band-tail effect, and self-heating is not considered, as it is negligible in the subthreshold region. The approach is straightforward and can be easily applied to other types of MOSFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"68-74"},"PeriodicalIF":2.9,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-26DOI: 10.1109/TED.2024.3486261
Lisa Sarkar;Soumen Paul;Avik Sett;Ambika Kumari;Tarun Kanti Bhattacharyya
Uncontrolled release of various harmful gases from automobiles and chemical industries demands accurate methods for gas classification and detection. In this context, this article proposes an effective method to classify and detect four gases—ammonia, formaldehyde, toluene, and acetone using a single field-effect transistor (FET)-based gas sensor. The gate voltage of the FET sensor played a pivotal role in this classification mechanism. L-ascorbic acid functionalized graphene oxide (GO) was used as the sensing material of the FET device. Initially, various features of the fabricated FET sensor (i.e., % of response, response time, and recovery time) were captured by varying the applied gate voltage. Furthermore, classification algorithms such as decision tree (DT), support vector machine (SVM), gradient boosting (GB), and random forest (RF) were trained to automatically predict the target gases. An accuracy of 73% was achieved for all three classifiers other than the SVM classifier. The use of machine learning algorithms was fruitful to accurately detect four gases at different gate voltages when any unknown one among the four was exposed to the single gate-tuned sensor. Moreover, it also saved the system’s power consumption as a single sensor was behaving like several sensors.
{"title":"Classification of Gases With Single FET-Based Gas Sensor Through Gate Voltage Sweeping and Machine Learning","authors":"Lisa Sarkar;Soumen Paul;Avik Sett;Ambika Kumari;Tarun Kanti Bhattacharyya","doi":"10.1109/TED.2024.3486261","DOIUrl":"https://doi.org/10.1109/TED.2024.3486261","url":null,"abstract":"Uncontrolled release of various harmful gases from automobiles and chemical industries demands accurate methods for gas classification and detection. In this context, this article proposes an effective method to classify and detect four gases—ammonia, formaldehyde, toluene, and acetone using a single field-effect transistor (FET)-based gas sensor. The gate voltage of the FET sensor played a pivotal role in this classification mechanism. L-ascorbic acid functionalized graphene oxide (GO) was used as the sensing material of the FET device. Initially, various features of the fabricated FET sensor (i.e., % of response, response time, and recovery time) were captured by varying the applied gate voltage. Furthermore, classification algorithms such as decision tree (DT), support vector machine (SVM), gradient boosting (GB), and random forest (RF) were trained to automatically predict the target gases. An accuracy of 73% was achieved for all three classifiers other than the SVM classifier. The use of machine learning algorithms was fruitful to accurately detect four gases at different gate voltages when any unknown one among the four was exposed to the single gate-tuned sensor. Moreover, it also saved the system’s power consumption as a single sensor was behaving like several sensors.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"376-382"},"PeriodicalIF":2.9,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：