The quasi-ballistic transport characteristics in the Ge pMOSFETs with NiGe metal source/drain (S/D) are analyzed. It is found that the Ge pMOSFETs represent a remarkable velocity overshoot and the injection velocity of the hole achieves $1.8times ,, 10^{{7}}$ cm/s. Additionally, the Ge pMOSFETs with metal S/D exhibit a much smaller 1/Bsat than those in Ge-OI pMOSFETs with conventional ion implantation S/D. These phenomena are attributable to the improved lateral electrical field at the metal S/D edge. It is suggested that the metal S/D structure is an effective booster to increase the electrical performance of ballistic transport Ge pMOSFETs.
分析了金属源极/漏极（S/D）锗pmosfet的准弹道输运特性。结果表明，Ge pmosfet表现出显著的速度超调，空穴注入速度达到$1.8倍，,10^{{7}}$ cm/s。此外，与传统离子注入S/D的Ge- oi pmosfet相比，采用金属S/D的Ge- oi pmosfet表现出更小的1/Bsat。这些现象可归因于金属S/D边侧电场的改善。结果表明，金属S/D结构是提高弹道输运Ge pmosfet电性能的有效助推器。
{"title":"Evaluation of Quasi-Ballistic Transport Behaviors in Ge pMOSFETs With NiGe Metal Source/Drain","authors":"Rui Su;Jing Yan;Dawei Gao;Junkang Li;John Robertson;Rui Zhang","doi":"10.1109/TED.2025.3590364","DOIUrl":"https://doi.org/10.1109/TED.2025.3590364","url":null,"abstract":"The quasi-ballistic transport characteristics in the Ge pMOSFETs with NiGe metal source/drain (S/D) are analyzed. It is found that the Ge pMOSFETs represent a remarkable velocity overshoot and the injection velocity of the hole achieves <inline-formula> <tex-math>$1.8times ,, 10^{{7}}$ </tex-math></inline-formula> cm/s. Additionally, the Ge pMOSFETs with metal S/D exhibit a much smaller 1/Bsat than those in Ge-OI pMOSFETs with conventional ion implantation S/D. These phenomena are attributable to the improved lateral electrical field at the metal S/D edge. It is suggested that the metal S/D structure is an effective booster to increase the electrical performance of ballistic transport Ge pMOSFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4679-4684"},"PeriodicalIF":3.2,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-13DOI: 10.1109/TED.2025.3591752
Jing Jing Dai;Jie Wang;Wei Li;Jian Jun Luo;Sheng Nan Li;Zhi Yong Wang;Sisi Zhao;Peng Zhuo Wang
To mitigate the central heat accumulation in vertical-cavity surface-emitting laser (VCSEL) arrays during operation, homogenize the temperature field distribution, and enhance the overall output power of the laser array, this article establishes a 3-D thermoelectric coupling physical model. The study investigates the impact of missing units at different positions within the array on thermal crosstalk and proposes an algorithm aimed at minimizing the difference in the array’s thermal coupling factor matrix. The effectiveness of this algorithm in homogenizing the array’s thermal distribution is verified through thermal simulations. Various array configurations with different layouts are designed and fabricated, and the power–current characteristics and spectral data of the devices before and after optimization are successfully obtained. For the optimized $3times 3$ and $5times 5$ arrays, the peak powers reach 150.1 and 175.4 mW, respectively. The photoelectric conversion efficiency is improved by 23.92% and 13.63% compared to the pre-optimization state. Moreover, the optimized array structures reduce the wavelength redshift by 3.29 and 1.24 nm. By optimizing the layout of VCSEL array units, the optimized devices exhibit superior thermal characteristics.
{"title":"Research on the Thermal Distribution Homogenization of High-Power Vertical-Cavity Surface-Emitting Lasers","authors":"Jing Jing Dai;Jie Wang;Wei Li;Jian Jun Luo;Sheng Nan Li;Zhi Yong Wang;Sisi Zhao;Peng Zhuo Wang","doi":"10.1109/TED.2025.3591752","DOIUrl":"https://doi.org/10.1109/TED.2025.3591752","url":null,"abstract":"To mitigate the central heat accumulation in vertical-cavity surface-emitting laser (VCSEL) arrays during operation, homogenize the temperature field distribution, and enhance the overall output power of the laser array, this article establishes a 3-D thermoelectric coupling physical model. The study investigates the impact of missing units at different positions within the array on thermal crosstalk and proposes an algorithm aimed at minimizing the difference in the array’s thermal coupling factor matrix. The effectiveness of this algorithm in homogenizing the array’s thermal distribution is verified through thermal simulations. Various array configurations with different layouts are designed and fabricated, and the power–current characteristics and spectral data of the devices before and after optimization are successfully obtained. For the optimized <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> and <inline-formula> <tex-math>$5times 5$ </tex-math></inline-formula> arrays, the peak powers reach 150.1 and 175.4 mW, respectively. The photoelectric conversion efficiency is improved by 23.92% and 13.63% compared to the pre-optimization state. Moreover, the optimized array structures reduce the wavelength redshift by 3.29 and 1.24 nm. By optimizing the layout of VCSEL array units, the optimized devices exhibit superior thermal characteristics.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4600-4607"},"PeriodicalIF":3.2,"publicationDate":"2025-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work systematically investigates the electrostatic discharge (ESD) robustness of Schottky-gate p-GaN high electron mobility transistors (HEMTs) under different gate and drain bias conditions. Gate-terminal ESD robustness is severely compromised under high ${V}_{text {DS}}$ ($ge 40$ V), where synergistic high voltage/current induces thermal runaway, causing irreversible damage. At ${V}_{text {DS}} =5$ –30 V, trap-dominated ${V}_{text {TH}}$ shifts (up to 0.68 V) correlate with $1200times {N}_{text {it0}}$ increases, partially recoverable over time. With the drain in the floating state, the trap-dominated ${V}_{text {TH}}$ shift (about 0.47 V) correlate with $140times {N}_{text {it}}$ increases, nearly fully recoverable over time. Under the drain-terminal ESD events, the device with the gate in floating state exhibits superior ESD robustness, accompanied by only a 0.12-V negative ${V} _{text {TH}}$ shift and high ${V}_{text {HBM}}$ of over 8.61 kV. The devices with gate biased at off/semi-on/on states achieve ${V}_{text {HBM}}$ from 0.27 to 30 kV, with (semi-on) on-state configurations meeting 2-kV industrial standards. This work bridges the gap in understanding multistress ESD interactions, providing critical insights for optimizing p-GaN HEMT reliability.
{"title":"The ESD Robustness of Schottky-Gate p-GaN HEMT Under Different States","authors":"Yijun Shi;Dongsheng Zhao;Zhipeng Shen;Lijuan Wu;Liang He;Xingchuan Jiang;Guanglin Yang;Qingzong Xiao;Xinghuan Chen;Yuan Chen;Guoguang Lu","doi":"10.1109/TED.2025.3592633","DOIUrl":"https://doi.org/10.1109/TED.2025.3592633","url":null,"abstract":"This work systematically investigates the electrostatic discharge (ESD) robustness of Schottky-gate p-GaN high electron mobility transistors (HEMTs) under different gate and drain bias conditions. Gate-terminal ESD robustness is severely compromised under high <inline-formula> <tex-math>${V}_{text {DS}}$ </tex-math></inline-formula> (<inline-formula> <tex-math>$ge 40$ </tex-math></inline-formula> V), where synergistic high voltage/current induces thermal runaway, causing irreversible damage. At <inline-formula> <tex-math>${V}_{text {DS}} =5$ </tex-math></inline-formula>–30 V, trap-dominated <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> shifts (up to 0.68 V) correlate with <inline-formula> <tex-math>$1200times {N}_{text {it0}}$ </tex-math></inline-formula> increases, partially recoverable over time. With the drain in the floating state, the trap-dominated <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> shift (about 0.47 V) correlate with <inline-formula> <tex-math>$140times {N}_{text {it}}$ </tex-math></inline-formula> increases, nearly fully recoverable over time. Under the drain-terminal ESD events, the device with the gate in floating state exhibits superior ESD robustness, accompanied by only a 0.12-V negative <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> shift and high <inline-formula> <tex-math>${V}_{text {HBM}}$ </tex-math></inline-formula> of over 8.61 kV. The devices with gate biased at off/semi-on/on states achieve <inline-formula> <tex-math>${V}_{text {HBM}}$ </tex-math></inline-formula> from 0.27 to 30 kV, with (semi-on) on-state configurations meeting 2-kV industrial standards. This work bridges the gap in understanding multistress ESD interactions, providing critical insights for optimizing p-GaN HEMT reliability.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4810-4816"},"PeriodicalIF":3.2,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-11DOI: 10.1109/TED.2025.3595113
Hsin-Hung Yeh;Min-Hsun Chuang;Jiaw-Ren Shih;Chrong Jung Lin;Ya-Chin King
This research introduces an advanced analog memory cell architecture based on a floating-gate inverter, implemented in the FinFET technology node. The cell integrates a CMOS logic gate, where its analog levels are directly influenced by the amount of charge stored within the floating gate. This unique shared-floating-gate configuration allows precise control over the stored analog values, making it possible to achieve a wider range of signal levels compared to traditional designs. The complementary design approach further enhances the flexibility and robustness of the memory cell, enabling versatile readout methods that are resilient to variations in process and operating conditions. Additionally, the pulse-controlled modulation of the analog levels, combined with innovative readout techniques tailored to this structure, has been successfully demonstrated in this study, showcasing the potential for high-performance, low-power, and scalable analog memory solutions in future advanced CMOS technologies.
{"title":"FinFET-Based Logic-Compatible Low-Voltage Linear-Injection Analog Memory","authors":"Hsin-Hung Yeh;Min-Hsun Chuang;Jiaw-Ren Shih;Chrong Jung Lin;Ya-Chin King","doi":"10.1109/TED.2025.3595113","DOIUrl":"https://doi.org/10.1109/TED.2025.3595113","url":null,"abstract":"This research introduces an advanced analog memory cell architecture based on a floating-gate inverter, implemented in the FinFET technology node. The cell integrates a CMOS logic gate, where its analog levels are directly influenced by the amount of charge stored within the floating gate. This unique shared-floating-gate configuration allows precise control over the stored analog values, making it possible to achieve a wider range of signal levels compared to traditional designs. The complementary design approach further enhances the flexibility and robustness of the memory cell, enabling versatile readout methods that are resilient to variations in process and operating conditions. Additionally, the pulse-controlled modulation of the analog levels, combined with innovative readout techniques tailored to this structure, has been successfully demonstrated in this study, showcasing the potential for high-performance, low-power, and scalable analog memory solutions in future advanced CMOS technologies.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4922-4928"},"PeriodicalIF":3.2,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-08DOI: 10.1109/TED.2025.3594603
Michael Jin;Hengyu Yu;Monikuntala Bhattacharya;Jiashu Qian;Shiva Houshmand;Atsushi Shimbori;Marvin H. White;Anant K. Agarwal
This study estimates the intrinsic gate oxide lifetime of two generations of commercial planar SiC MOSFETs using pulse-voltage time-dependent dielectric breakdown (PV-TDDB) and constant-voltage (CV) time-dependent dielectric breakdown (TDDB) at $150~^{circ }$ C. Compared to the conventional CV time-dependent-dielectric-breakdown (CV-TDDB) method, the proposed PV-TDDB method yields significantly higher predicted lifetimes at the same oxide electric field, with estimated lifetimes closer to actual operational lifetimes. Furthermore, the gate leakage current behaviors under both conditions are analyzed. The effects of charge trapping in the gate oxide on the gate leakage current and the lifetime are examined, along with the effects of the high-frequency gate voltage pulses on the gate oxide and trapped charges. Finally, the gate oxide lifetime of the two generations of devices is compared. The proposed PV-TDDB method enhances conventional CV-TDDB testing by incorporating pulsed gate oxide voltages, thereby providing a more representative assessment of oxide lifetime under real operating conditions.
{"title":"Investigation of Time-Dependent Dielectric Breakdown on Commercial SiC MOSFETs Using Constant-Voltage and Pulse-Voltage","authors":"Michael Jin;Hengyu Yu;Monikuntala Bhattacharya;Jiashu Qian;Shiva Houshmand;Atsushi Shimbori;Marvin H. White;Anant K. Agarwal","doi":"10.1109/TED.2025.3594603","DOIUrl":"https://doi.org/10.1109/TED.2025.3594603","url":null,"abstract":"This study estimates the intrinsic gate oxide lifetime of two generations of commercial planar SiC MOSFETs using pulse-voltage time-dependent dielectric breakdown (PV-TDDB) and constant-voltage (CV) time-dependent dielectric breakdown (TDDB) at <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C. Compared to the conventional CV time-dependent-dielectric-breakdown (CV-TDDB) method, the proposed PV-TDDB method yields significantly higher predicted lifetimes at the same oxide electric field, with estimated lifetimes closer to actual operational lifetimes. Furthermore, the gate leakage current behaviors under both conditions are analyzed. The effects of charge trapping in the gate oxide on the gate leakage current and the lifetime are examined, along with the effects of the high-frequency gate voltage pulses on the gate oxide and trapped charges. Finally, the gate oxide lifetime of the two generations of devices is compared. The proposed PV-TDDB method enhances conventional CV-TDDB testing by incorporating pulsed gate oxide voltages, thereby providing a more representative assessment of oxide lifetime under real operating conditions.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4714-4720"},"PeriodicalIF":3.2,"publicationDate":"2025-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-06DOI: 10.1109/TED.2025.3593989
Long Huang;Zhiyuan Wang;Zihao Cheng;Tianye Wei;Jiawei Zhang;Aimin Song
The oxide thin-film transistors (TFTs) have developed rapidly in the past years and are entering more and more commercial applications, such as display drivers and dynamic random access memories. In contrast to a vast amount of experimental work, very limited work has been carried out on the modeling, particularly with the newly explored artificial neural network (ANN) approach, which is capable of precise modeling. Here, ANN models are established for both n-type indium-gallium-zinc oxide (IGZO) and p-type tin monoxide (SnO) TFTs. Our ANN models include three layers of neurons in order to balance the accuracy and the complexity. The modeled TFT currents agree with the experimental data over a wide range of more than four orders of magnitude. The relative error of the model in the entire experimental current and voltage ranges is no more than 0.47% and 0.29% for the IGZO and SnO TFTs, respectively. The ability for the model to predict nonmeasured device current also allows for circuit modeling, as evidenced by the agreement between the predicted oxide inverter and nand gate characteristics and the experimental data.
{"title":"Oxide Thin-Film Transistor and Circuit Modeling Using Artificial Neural Network","authors":"Long Huang;Zhiyuan Wang;Zihao Cheng;Tianye Wei;Jiawei Zhang;Aimin Song","doi":"10.1109/TED.2025.3593989","DOIUrl":"https://doi.org/10.1109/TED.2025.3593989","url":null,"abstract":"The oxide thin-film transistors (TFTs) have developed rapidly in the past years and are entering more and more commercial applications, such as display drivers and dynamic random access memories. In contrast to a vast amount of experimental work, very limited work has been carried out on the modeling, particularly with the newly explored artificial neural network (ANN) approach, which is capable of precise modeling. Here, ANN models are established for both n-type indium-gallium-zinc oxide (IGZO) and p-type tin monoxide (SnO) TFTs. Our ANN models include three layers of neurons in order to balance the accuracy and the complexity. The modeled TFT currents agree with the experimental data over a wide range of more than four orders of magnitude. The relative error of the model in the entire experimental current and voltage ranges is no more than 0.47% and 0.29% for the IGZO and SnO TFTs, respectively. The ability for the model to predict nonmeasured device current also allows for circuit modeling, as evidenced by the agreement between the predicted oxide inverter and <sc>nand</small> gate characteristics and the experimental data.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5011-5016"},"PeriodicalIF":3.2,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The CdZnTe (CZT) photon-counting detector with energy discrimination capabilities is one of the primary development directions for future medical X-ray imaging. Over the past few decades, the melt growth method has been commonly used for preparing CZT photon-counting detectors. However, this method has a long growth cycle and high cost due to the difficulty in manufacturing defect-free large-area wafers. CZT single crystals grown by closed-spaced sublimation (CSS) vapor phase growth method are expected to enable effective cost reduction. In this study, epitaxial CZT crystals grown by the CSS method were annealed in a Te2 atmosphere, resulting in a significant enhancement of the detectors’ photon-counting performance. The research investigates the relationship between annealing temperature and carrier transport properties, as well as the regulation of deep-level defects in CZT crystals and their impact on photon-counting characteristics. The goal is to determine the optimal annealing temperature as an effective strategy for improving the performance of CZT epitaxial crystal detectors. We systematically analyzed the electrical properties of detectors, such as resistivity, leakage current, energy resolution, and carrier mobility-lifetime product, and developed a CZT photon-counting detector with a high counting rate of 2.87M CPS/mm2. The results offer valuable theoretical and experimental foundations guidance for enhancing the performance of CZT epitaxial crystal detectors.
{"title":"Preparation of CdZnTe Photon-Counting Detectors by CSS Method: Annealing Regulation in Te2 Atmosphere","authors":"Heming Wei;Kun Cao;Tingting Tan;Shixuan Luo;Xin Wan;Ran Jiang;Qingpei Li;Jiahu Liu;Gangqiang Zha","doi":"10.1109/TED.2025.3589198","DOIUrl":"https://doi.org/10.1109/TED.2025.3589198","url":null,"abstract":"The CdZnTe (CZT) photon-counting detector with energy discrimination capabilities is one of the primary development directions for future medical X-ray imaging. Over the past few decades, the melt growth method has been commonly used for preparing CZT photon-counting detectors. However, this method has a long growth cycle and high cost due to the difficulty in manufacturing defect-free large-area wafers. CZT single crystals grown by closed-spaced sublimation (CSS) vapor phase growth method are expected to enable effective cost reduction. In this study, epitaxial CZT crystals grown by the CSS method were annealed in a Te2 atmosphere, resulting in a significant enhancement of the detectors’ photon-counting performance. The research investigates the relationship between annealing temperature and carrier transport properties, as well as the regulation of deep-level defects in CZT crystals and their impact on photon-counting characteristics. The goal is to determine the optimal annealing temperature as an effective strategy for improving the performance of CZT epitaxial crystal detectors. We systematically analyzed the electrical properties of detectors, such as resistivity, leakage current, energy resolution, and carrier mobility-lifetime product, and developed a CZT photon-counting detector with a high counting rate of 2.87M CPS/mm2. The results offer valuable theoretical and experimental foundations guidance for enhancing the performance of CZT epitaxial crystal detectors.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5031-5037"},"PeriodicalIF":3.2,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The heavy ion-induced leakage current increase is reported for the 650-V p-gallium nitride (GaN) gate HEMTs. The degradation of leakage current increase in GaN HEMTs caused by heavy ions is related to the linear energy transfer (LET) value of the heavy ions and the bias voltage. The increased leakage current is only observed under Ta ion irradiation with an LET value of 60.5 MeV$cdot $ cm2/mg but not under Kr ion irradiation with an LET value of 20.0 MeV$cdot $ cm2/mg. Moreover, a higher bias voltage leads to a more pronounced degradation of leakage current increase. When the device is biased at 100 V, heavy ion-induced leakage pathways exist between the drain and source. However, when the voltage is increased to 200 V, in addition to the leakage between the drain and source, leakage pathways form between the drain and gate. Heavy ion-induced damages and morphological changes of the field plate are observed in the irradiated devices, which may contribute to the leakage degradation. The damage mechanism has also been verified through TCAD simulations.
{"title":"Mechanism of Heavy Ion-Induced Leakage Current Increase in Normally-OFF p-GaN Gate HEMTs","authors":"Chao Peng;Zhifeng Lei;Teng Ma;Hong Zhang;Zhangang Zhang;Yujuan He;Kai Lyu;Yiqiang Chen","doi":"10.1109/TED.2025.3591093","DOIUrl":"https://doi.org/10.1109/TED.2025.3591093","url":null,"abstract":"The heavy ion-induced leakage current increase is reported for the 650-V p-gallium nitride (GaN) gate HEMTs. The degradation of leakage current increase in GaN HEMTs caused by heavy ions is related to the linear energy transfer (LET) value of the heavy ions and the bias voltage. The increased leakage current is only observed under Ta ion irradiation with an LET value of 60.5 MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/mg but not under Kr ion irradiation with an LET value of 20.0 MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/mg. Moreover, a higher bias voltage leads to a more pronounced degradation of leakage current increase. When the device is biased at 100 V, heavy ion-induced leakage pathways exist between the drain and source. However, when the voltage is increased to 200 V, in addition to the leakage between the drain and source, leakage pathways form between the drain and gate. Heavy ion-induced damages and morphological changes of the field plate are observed in the irradiated devices, which may contribute to the leakage degradation. The damage mechanism has also been verified through TCAD simulations.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4788-4794"},"PeriodicalIF":3.2,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-05DOI: 10.1109/TED.2025.3594607
Minsang Ryu;Minki Suh;Jonghyeon Ha;Dabok Lee;Hojoon Lee;Hyunchul Sagong;Jungsik Kim
In this study, single-event upset (SEU) and total ionizing dose (TID) effects on DDR4 dynamic random access memory (DRAM) under 48-MeV proton radiation and various temperatures (153–373 K) were investigated. The SEU-induced error density reached a maximum of $5.59times 10^{-{6}}$ at 373 K and a minimum of $9.77times 10^{-{10}}$ at 153 K, which correlates with the increase in gate-induced drain leakage (GIDL) as temperature rises. After the device under test (DUT) was irradiated at 153, 300, and 373 K, the TID-induced error density was estimated. The generation of interface traps was higher at 373 K than at 153 K, leading to an increase in the TID-induced error density. However, the error density at 300 K was 1.1 times as high as that at 373 K. This occurs because the DUT irradiated at 373 K is more favorable for defect recovery via annealing than at 300 K.
{"title":"Single-Event Upset and Total Ionizing Dose Effects on DDR4 DRAM Due to Proton Irradiation Under Different Temperatures","authors":"Minsang Ryu;Minki Suh;Jonghyeon Ha;Dabok Lee;Hojoon Lee;Hyunchul Sagong;Jungsik Kim","doi":"10.1109/TED.2025.3594607","DOIUrl":"https://doi.org/10.1109/TED.2025.3594607","url":null,"abstract":"In this study, single-event upset (SEU) and total ionizing dose (TID) effects on DDR4 dynamic random access memory (DRAM) under 48-MeV proton radiation and various temperatures (153–373 K) were investigated. The SEU-induced error density reached a maximum of <inline-formula> <tex-math>$5.59times 10^{-{6}}$ </tex-math></inline-formula> at 373 K and a minimum of <inline-formula> <tex-math>$9.77times 10^{-{10}}$ </tex-math></inline-formula> at 153 K, which correlates with the increase in gate-induced drain leakage (GIDL) as temperature rises. After the device under test (DUT) was irradiated at 153, 300, and 373 K, the TID-induced error density was estimated. The generation of interface traps was higher at 373 K than at 153 K, leading to an increase in the TID-induced error density. However, the error density at 300 K was 1.1 times as high as that at 373 K. This occurs because the DUT irradiated at 373 K is more favorable for defect recovery via annealing than at 300 K.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5243-5246"},"PeriodicalIF":3.2,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We experimentally analyze the incremental step pulse programming (ISPP) characteristics of gate-side injection type MIFIS FeFETs, which feature a metal – gate interlayer (G.IL) – ferroelectrics – channel interlayer (Ch.IL) – Si stack, with a focus on the role of the G.IL. We also propose a mathematical model considering ferroelectric (FE) switching behavior. MIFIS FeFETs have recently garnered attention due to their ability to achieve lower program (PGM) voltages and wider memory windows (MWs) compared to typical channel-side injection type charge trap flash (CTF) devices, thanks to the injection of charges (${Q}_{text {it}}'$ ) from the gate and polarization switching dynamics. However, guidelines on the influence of the G.IL on ISPP characteristics and endurance, critical for nand cell, are lacking. Here, we experimentally investigate the impact of the G.IL on the ISPP slope of MIFIS FeFETs and, through mathematical modeling, propose a G.IL design to optimize MIFIS FeFET performance. Furthermore, we analyze the degradation of endurance characteristics depending on the type of G.IL, suggesting that the excessive ${Q}_{text {it}}$ injected from the Ch.IL, together with polarization pinning, contributes to overall endurance degradation. Lastly, we demonstrate that by utilizing a low-$kappa $ SiO2 G.IL (6 nm), a MW of 6.5 V and an ISPP slope greater than 3 can be achieved. Our MIFIS FeFET also exhibits disturbance immunity even at voltages exceeding 14 V, which is critical in preventing ${V}_{text {th}}$ shifts during various disturbances. Our research and model can provide valuable guidelines for the study of gate-injection type FeFET, which are actively being explored as next-generation nand Flash memory technologies.
{"title":"Experimental Analysis and Mathematical Modeling of Program Efficiency in Gate-Side Injection Type FeFETs Depending on the Gate Interlayer","authors":"Giuk Kim;Taeho Kim;Hyojun Choi;Seokjoong Shin;Hoon Kim;Sanghyun Park;Kwangyou Seo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon","doi":"10.1109/TED.2025.3592164","DOIUrl":"https://doi.org/10.1109/TED.2025.3592164","url":null,"abstract":"We experimentally analyze the incremental step pulse programming (ISPP) characteristics of gate-side injection type MIFIS FeFETs, which feature a metal – gate interlayer (G.IL) – ferroelectrics – channel interlayer (Ch.IL) – Si stack, with a focus on the role of the G.IL. We also propose a mathematical model considering ferroelectric (FE) switching behavior. MIFIS FeFETs have recently garnered attention due to their ability to achieve lower program (PGM) voltages and wider memory windows (MWs) compared to typical channel-side injection type charge trap flash (CTF) devices, thanks to the injection of charges (<inline-formula> <tex-math>${Q}_{text {it}}'$ </tex-math></inline-formula>) from the gate and polarization switching dynamics. However, guidelines on the influence of the G.IL on ISPP characteristics and endurance, critical for <sc>nand</small> cell, are lacking. Here, we experimentally investigate the impact of the G.IL on the ISPP slope of MIFIS FeFETs and, through mathematical modeling, propose a G.IL design to optimize MIFIS FeFET performance. Furthermore, we analyze the degradation of endurance characteristics depending on the type of G.IL, suggesting that the excessive <inline-formula> <tex-math>${Q}_{text {it}}$ </tex-math></inline-formula> injected from the Ch.IL, together with polarization pinning, contributes to overall endurance degradation. Lastly, we demonstrate that by utilizing a low-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> SiO2 G.IL (6 nm), a MW of 6.5 V and an ISPP slope greater than 3 can be achieved. Our MIFIS FeFET also exhibits disturbance immunity even at voltages exceeding 14 V, which is critical in preventing <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> shifts during various disturbances. Our research and model can provide valuable guidelines for the study of gate-injection type FeFET, which are actively being explored as next-generation <sc>nand</small> Flash memory technologies.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4896-4901"},"PeriodicalIF":3.2,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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