Pub Date : 2025-11-24DOI: 10.1109/TED.2025.3627189
D. K. Nguyen;A. Pilotto;D. Lizzit;M. Pala;P. Dollfus;D. Esseni
This article investigates the operation and design of Dirac-source FETs (DSFETs), by using ab initio transport simulations based on the NEGF formalism, which seems appropriate given the novelty of the physics and of the device architecture introduced by DSFETs. In particular, we first discuss the limitations in terms of drive current of DSFETs based on a graphene-MoS2 van der Waals heterojunction. Then, we propose a novel p-type DSFET based on hydrogenated graphene (HGr). Our simulation results suggest that the HGr-DSFET has a robust sub-60 mV/dec operation and an ${textsc{on}}$ -current between $text{2}times $ and $text{4}times $ larger than the graphene-MoS2 DSFET counterpart. Our study investigates the influence on the device operation of several material and design parameters, using either ballistic simulations or simulations accounting for electron–phonon scattering.
{"title":"Operation and Design of Dirac-Source FETs Using Ab Initio Transport Simulations: Subthreshold Swing and Drive Current","authors":"D. K. Nguyen;A. Pilotto;D. Lizzit;M. Pala;P. Dollfus;D. Esseni","doi":"10.1109/TED.2025.3627189","DOIUrl":"https://doi.org/10.1109/TED.2025.3627189","url":null,"abstract":"This article investigates the operation and design of Dirac-source FETs (DSFETs), by using ab initio transport simulations based on the NEGF formalism, which seems appropriate given the novelty of the physics and of the device architecture introduced by DSFETs. In particular, we first discuss the limitations in terms of drive current of DSFETs based on a graphene-MoS<sub>2</sub> van der Waals heterojunction. Then, we propose a novel p-type DSFET based on hydrogenated graphene (HGr). Our simulation results suggest that the HGr-DSFET has a robust sub-60 mV/dec operation and an <inline-formula> <tex-math>${textsc{on}}$ </tex-math></inline-formula>-current between <inline-formula> <tex-math>$text{2}times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$text{4}times $ </tex-math></inline-formula> larger than the graphene-MoS<sub>2</sub> DSFET counterpart. Our study investigates the influence on the device operation of several material and design parameters, using either ballistic simulations or simulations accounting for electron–phonon scattering.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7114-7121"},"PeriodicalIF":3.2,"publicationDate":"2025-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-20DOI: 10.1109/TED.2025.3629592
Yong-Ci Zhang;Kai-Chun Chang;Po-Hsun Chen;Ting-Chang Chang;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Hung-Ming Kuo
This research presents a new method for detecting GaN buffer traps in GaN high electron mobility transistors with p-type gates (p-GaN HEMTs). It is demonstrated that the hysteresis window during the transfer curve sweeping can be used to analyze the GaN buffer quality. The hysteresis behavior of p-GaN HEMTs is experimentally investigated in this research. Transfer curve sweeping with the varied $textit{V}_{text {g}}$ range and gate bias stress is tested on the device to clarify the physical model of the hysteresis window in p-GaN HEMTs. A hysteresis behavioral model in p-GaN HEMTs can correlate the hysteresis window with the buffer quality, providing an effective technique for the instantaneous detection of GaN buffer quality. The method is also verified by a dynamic $textit{R}_{text {on}}$ test on two devices with different buffer processes. The dynamic $textit{R}_{text {on}}$ degradation has a good correlation with the hysteresis window, which indicates that this new method is effective for detecting p-GaN HEMT buffer quality. The method proposed in this study has the potential to accelerate the detection of buffer traps in p-GaN HEMT devices. Through the technology developed in this research, we can identify and address these defects more quickly, and it is expected to achieve better performance for p-GaN HEMT in the field of high-power components.
{"title":"A Method to Detect Buffer Traps by the Hysteresis Window of p-GaN HEMTs","authors":"Yong-Ci Zhang;Kai-Chun Chang;Po-Hsun Chen;Ting-Chang Chang;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Hung-Ming Kuo","doi":"10.1109/TED.2025.3629592","DOIUrl":"https://doi.org/10.1109/TED.2025.3629592","url":null,"abstract":"This research presents a new method for detecting GaN buffer traps in GaN high electron mobility transistors with p-type gates (p-GaN HEMTs). It is demonstrated that the hysteresis window during the transfer curve sweeping can be used to analyze the GaN buffer quality. The hysteresis behavior of p-GaN HEMTs is experimentally investigated in this research. Transfer curve sweeping with the varied <inline-formula> <tex-math>$textit{V}_{text {g}}$ </tex-math></inline-formula> range and gate bias stress is tested on the device to clarify the physical model of the hysteresis window in p-GaN HEMTs. A hysteresis behavioral model in p-GaN HEMTs can correlate the hysteresis window with the buffer quality, providing an effective technique for the instantaneous detection of GaN buffer quality. The method is also verified by a dynamic <inline-formula> <tex-math>$textit{R}_{text {on}}$ </tex-math></inline-formula> test on two devices with different buffer processes. The dynamic <inline-formula> <tex-math>$textit{R}_{text {on}}$ </tex-math></inline-formula> degradation has a good correlation with the hysteresis window, which indicates that this new method is effective for detecting p-GaN HEMT buffer quality. The method proposed in this study has the potential to accelerate the detection of buffer traps in p-GaN HEMT devices. Through the technology developed in this research, we can identify and address these defects more quickly, and it is expected to achieve better performance for p-GaN HEMT in the field of high-power components.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7186-7189"},"PeriodicalIF":3.2,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1109/TED.2025.3628365
Yi Gu;Wendi Wei;Kun Chen;Chen Wang;Qingqing Sun;David Wei Zhang
A universal model for drain-induced barrier lowering (DIBL) that accounts for time-dependent hot carrier degradation (HCD) in fin field-effect transistor (FinFET) has been presented. The model demonstrates agreement with experimental data from advanced 14-nm ultralow threshold voltage (ULVT) FinFET devices, accurately predicting DIBL degradation under HCD stress, where DIBL values become independent of $textit{V}_{text {ds}}$ during stress. The forward and reverse measurements are employed to analyze DIBL degradation and the associated evolution of lateral interface traps. Additionally, integrating the model into circuit-level analyses, such as those for inverter and SRAM, effectively reduces the risk of overestimating device performance. This comprehensive evaluation highlights the critical importance of precise DIBL modeling for ensuring circuit reliability in modern ultralow-power (ULP) system-on chip (SoC) designs.
{"title":"Universal Time-Dependent DIBL Model for HCD-Degraded FinFETs","authors":"Yi Gu;Wendi Wei;Kun Chen;Chen Wang;Qingqing Sun;David Wei Zhang","doi":"10.1109/TED.2025.3628365","DOIUrl":"https://doi.org/10.1109/TED.2025.3628365","url":null,"abstract":"A universal model for drain-induced barrier lowering (DIBL) that accounts for time-dependent hot carrier degradation (HCD) in fin field-effect transistor (FinFET) has been presented. The model demonstrates agreement with experimental data from advanced 14-nm ultralow threshold voltage (ULVT) FinFET devices, accurately predicting DIBL degradation under HCD stress, where DIBL values become independent of <inline-formula> <tex-math>$textit{V}_{text {ds}}$ </tex-math></inline-formula> during stress. The forward and reverse measurements are employed to analyze DIBL degradation and the associated evolution of lateral interface traps. Additionally, integrating the model into circuit-level analyses, such as those for inverter and SRAM, effectively reduces the risk of overestimating device performance. This comprehensive evaluation highlights the critical importance of precise DIBL modeling for ensuring circuit reliability in modern ultralow-power (ULP) system-on chip (SoC) designs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7182-7185"},"PeriodicalIF":3.2,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-13DOI: 10.1109/TED.2025.3629599
Yuan-Chun Su;Shu-Jui Chang;D. Mahaveer Sathaiya;Chen-Feng Hsu;Bo-Heng Liu;Chien-Ying Su;Chi-Chung Kei;Yen-Fa Liao;Shu-Chih Haw;Chih-Wei Hu;San-Lin Liew;Vincent Duen-Huei Hou;T.-Y. Lee;Chao-Ching Cheng;Tsung-En Lee;Iuliana P. Radu
To address the challenge of directly nucleating dielectrics on a dangling bond-free surface, we present an optimized atomic layer deposition (ALD) process to achieve uniform AlOx and HfOx dielectric layers on a monolayer MoS2 nanosheet within a gate-all-around (GAA) architecture. By introducing a trimethylaluminum (TMA) precursor soaking step in the ALD cycles, a thin and dense AlOx interfacial layer (IL) can be formed on the MoS2 surface. Depositing the AlOx IL at 90$~^{circ }$ C and the subsequent HfOx high-$kappa $ layer at 200$~^{circ }$ C minimizes defect formations and preserves the MoS2 channel’s integrity. A postdeposition anneal at 400$~^{circ }$ C further improves device performance, achieving an ON/OFF ratio of 108 and a improved subthreshold swing (SS). These improvements are attributed to a reduction of Al–OH bonds in the AlOx layer, which lowers the interface trap density and enhances carrier mobility. This study demonstrates the feasibility of integrating high-quality ALD gate dielectrics with 1L-MoS2 enabling scalable and high-performance nanosheet transistors and paving the way toward advanced device architectures.
{"title":"Conformal Atomic Layer Deposition of Gate Dielectrics on Monolayer MoS2 for Gate-All-Around Transistors","authors":"Yuan-Chun Su;Shu-Jui Chang;D. Mahaveer Sathaiya;Chen-Feng Hsu;Bo-Heng Liu;Chien-Ying Su;Chi-Chung Kei;Yen-Fa Liao;Shu-Chih Haw;Chih-Wei Hu;San-Lin Liew;Vincent Duen-Huei Hou;T.-Y. Lee;Chao-Ching Cheng;Tsung-En Lee;Iuliana P. Radu","doi":"10.1109/TED.2025.3629599","DOIUrl":"https://doi.org/10.1109/TED.2025.3629599","url":null,"abstract":"To address the challenge of directly nucleating dielectrics on a dangling bond-free surface, we present an optimized atomic layer deposition (ALD) process to achieve uniform AlO<sub>x</sub> and HfO<sub>x</sub> dielectric layers on a monolayer MoS<sub>2</sub> nanosheet within a gate-all-around (GAA) architecture. By introducing a trimethylaluminum (TMA) precursor soaking step in the ALD cycles, a thin and dense AlO<sub>x</sub> interfacial layer (IL) can be formed on the MoS<sub>2</sub> surface. Depositing the AlO<sub>x</sub> IL at 90<inline-formula> <tex-math>$~^{circ }$ </tex-math></inline-formula>C and the subsequent HfO<sub>x</sub> high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> layer at 200<inline-formula> <tex-math>$~^{circ }$ </tex-math></inline-formula>C minimizes defect formations and preserves the MoS<sub>2</sub> channel’s integrity. A postdeposition anneal at 400<inline-formula> <tex-math>$~^{circ }$ </tex-math></inline-formula>C further improves device performance, achieving an <sc>ON</small>/<sc>OFF</small> ratio of 10<sup>8</sup> and a improved subthreshold swing (SS). These improvements are attributed to a reduction of Al–OH bonds in the AlO<sub>x</sub> layer, which lowers the interface trap density and enhances carrier mobility. This study demonstrates the feasibility of integrating high-quality ALD gate dielectrics with 1L-MoS<sub>2</sub> enabling scalable and high-performance nanosheet transistors and paving the way toward advanced device architectures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7122-7127"},"PeriodicalIF":3.2,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The wake-up effect in ultrathin (sub-6-nm) hafnium-zirconium-oxide (HZO) ferroelectric films is a critical reliability challenge that slows down their implementation in nonvolatile memories. This article reports on the existence of optimal frequency that maximizes the efficiency of the wake-up process. To explain this phenomenon, a physical model based on the field-driven migration of oxygen ions and the interaction with oxygen vacancies is proposed. The optimal wake-up frequency is attributed to a temporal matching between the dynamics of oxygen ions across the film and the cycling field frequency. The model is validated by comprehensive experiments, including the field dependence of the optimal frequency and the thermally activated behavior with a thermal activation energy of 0.14--0.42 eV. This work provides a physical picture of the mechanism behind the wake-up effect and offers a guideline for an efficient wake-up process.
{"title":"Wake-Up Mechanism With De-Pinning Dynamics in Ultrathin Hf0.5Zr0.5O2: Understanding Frequency and Temperature Dependences","authors":"Kosuke Ito;Mitsuru Takenaka;Shinichi Takagi;Kasidit Toprasertpong","doi":"10.1109/TED.2025.3628364","DOIUrl":"https://doi.org/10.1109/TED.2025.3628364","url":null,"abstract":"The wake-up effect in ultrathin (sub-6-nm) hafnium-zirconium-oxide (HZO) ferroelectric films is a critical reliability challenge that slows down their implementation in nonvolatile memories. This article reports on the existence of optimal frequency that maximizes the efficiency of the wake-up process. To explain this phenomenon, a physical model based on the field-driven migration of oxygen ions and the interaction with oxygen vacancies is proposed. The optimal wake-up frequency is attributed to a temporal matching between the dynamics of oxygen ions across the film and the cycling field frequency. The model is validated by comprehensive experiments, including the field dependence of the optimal frequency and the thermally activated behavior with a thermal activation energy of 0.14--0.42 eV. This work provides a physical picture of the mechanism behind the wake-up effect and offers a guideline for an efficient wake-up process.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7145-7152"},"PeriodicalIF":3.2,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-10DOI: 10.1109/TED.2025.3606893
Chao Wang;Junfeng Hu;Ziyu Liu;Xiaojin Li;Yanling Shi;Yabin Sun
{"title":"Corrections to “TCAD Simulations of Reconfigurable Field-Effect Transistor With Embedded-Fin-Contact to Improve On-Current”","authors":"Chao Wang;Junfeng Hu;Ziyu Liu;Xiaojin Li;Yanling Shi;Yabin Sun","doi":"10.1109/TED.2025.3606893","DOIUrl":"https://doi.org/10.1109/TED.2025.3606893","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6396-6396"},"PeriodicalIF":3.2,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11236985","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-10DOI: 10.1109/TED.2025.3619313
{"title":"IEEE Transactions on Electron Devices Information for Authors","authors":"","doi":"10.1109/TED.2025.3619313","DOIUrl":"https://doi.org/10.1109/TED.2025.3619313","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"C3-C3"},"PeriodicalIF":3.2,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11237001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-10DOI: 10.1109/TED.2025.3619311
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/TED.2025.3619311","DOIUrl":"https://doi.org/10.1109/TED.2025.3619311","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6397-6398"},"PeriodicalIF":3.2,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11237003","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A comprehensive electrical characterization of a p-n diode constructed from a Te/n-Si heterostructure was presented in this work. Fabricated using CMOS-compatible RF sputtering, the device exhibited a typical diode behavior. Key electrical parameters including the ideality factor, series resistance, built-in potential, and interface state density were precisely extracted from temperature-dependent current–voltage measurements and capacitance–voltage analyses. The ideality factor decreased with increasing temperature, attributed to interface states and barrier inhomogeneities, while the decrease in series resistance with increasing temperature was a result of improved semiconductor conductivity due to increased intrinsic carrier concentration, reduced contact resistance at interfaces, and enhanced conduction through activated trap states. The reverse-bias current was dominated primarily by a thermal generation mechanism rather than by diffusion. Notably, the Te/n-Si diode demonstrated promising temperature sensing capabilities with a high sensitivity.
{"title":"In-Depth Electrical Characterization of Carrier Transport in Tellurium/Silicon Heterojunction-Based p-n Diode","authors":"Yohan Kim;Gyuri Lim;Byeongjin Park;Jongwon Yoon;Yonghun Kim;Dae-Young Jeon","doi":"10.1109/TED.2025.3626337","DOIUrl":"https://doi.org/10.1109/TED.2025.3626337","url":null,"abstract":"A comprehensive electrical characterization of a p-n diode constructed from a Te/n-Si heterostructure was presented in this work. Fabricated using CMOS-compatible RF sputtering, the device exhibited a typical diode behavior. Key electrical parameters including the ideality factor, series resistance, built-in potential, and interface state density were precisely extracted from temperature-dependent current–voltage measurements and capacitance–voltage analyses. The ideality factor decreased with increasing temperature, attributed to interface states and barrier inhomogeneities, while the decrease in series resistance with increasing temperature was a result of improved semiconductor conductivity due to increased intrinsic carrier concentration, reduced contact resistance at interfaces, and enhanced conduction through activated trap states. The reverse-bias current was dominated primarily by a thermal generation mechanism rather than by diffusion. Notably, the Te/n-Si diode demonstrated promising temperature sensing capabilities with a high sensitivity.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7108-7113"},"PeriodicalIF":3.2,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145729464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-03DOI: 10.1109/TED.2025.3623957
Xinkang Chen;Sumeet Kumar Gupta
In the article referenced below [1], the following errors and their corrections should be noted. The derivations, results, and analyses in [1] use the correct equations, and therefore, these errors do not impact the other content in [1]. 1)In (3), the term $(v_{z}/v)$ in the integrand should be replaced by $(v_{z}^{2}/v)$ .2)In (5), there should be no negative sign before $(2q^{2}m_{mathrm {eff}}^{2}/h^{3})$ .3) In (6), (7), (13), and (16), the prefactor on the right-hand side multiplied with $sigma _{0}$ should be $3/(4pi)$ (instead of $3/4)$ . Similarly, in the equation for $(sigma _{mathrm {SRFS}}(y_{n})/sigma _{0})$ in (18), the prefactor on the right-hand side multiplied by the integral with respect to $theta $ should be $3/(4pi)$ (instead of $3/4)$ .
{"title":"Erratum to “Spatially Resolved Conductivity of Rectangular Interconnects Considering Surface Scattering—Part I: Physical Modeling”","authors":"Xinkang Chen;Sumeet Kumar Gupta","doi":"10.1109/TED.2025.3623957","DOIUrl":"https://doi.org/10.1109/TED.2025.3623957","url":null,"abstract":"In the article referenced below [1], the following errors and their corrections should be noted. The derivations, results, and analyses in [1] use the correct equations, and therefore, these errors do not impact the other content in [1]. 1)In (3), the term $(v_{z}/v)$ in the integrand should be replaced by $(v_{z}^{2}/v)$ .2)In (5), there should be no negative sign before $(2q^{2}m_{mathrm {eff}}^{2}/h^{3})$ .3) In (6), (7), (13), and (16), the prefactor on the right-hand side multiplied with $sigma _{0}$ should be $3/(4pi)$ (instead of $3/4)$ . Similarly, in the equation for $(sigma _{mathrm {SRFS}}(y_{n})/sigma _{0})$ in (18), the prefactor on the right-hand side multiplied by the integral with respect to $theta $ should be $3/(4pi)$ (instead of $3/4)$ .","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7190-7190"},"PeriodicalIF":3.2,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11224734","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：