In this study, we explore the stability of third-quadrant characteristics in planar SiC power MOSFETs under high drain bias above the avalanche breakdown condition. By using experimental measurements and TCAD simulations, we analyze the mechanisms responsible for the positive shift of reverse turn-on voltage (${V}_{text {rev}, text {on}}$ ) during the third-quadrant operation. When the drain bias is increased from 1500 to 1620 V, obvious negative shifts in threshold voltage (${V}_{text {TH}}$ ) and positive shifts in ${V}_{text {rev}, text {on}}$ are observed. The TCAD simulations attribute these shifts to the impact ionization caused by the high electric field inside the p-well regions. Furthermore, with the inclusion of positive fixed charges as the hole traps in the gate oxide near the SiO2/SiC interface, the simulation results show positive shifts of ${V}_{text {rev}, text {on}}$ consistent with the experimental results. These findings suggest that hole trapping caused by high drain bias above the avalanche breakdown condition can affect the stability of third-quadrant operation in planar SiC power MOSFETs.
{"title":"Toward Understanding the Positive Shift of Reverse Turn-on Voltage in the Third Quadrant Operation in Planar SiC Power MOSFETs After Avalanche Breakdown","authors":"Wei-Cheng Lin;Yu-Sheng Hsiao;Chen Sung;Chu Thị Bích Ngọc;Rustam Kumar;Pei-Jie Chang;Surya Elangovan;Sheng-Shiuan Yeh;Chia-Lung Hung;Yi-Kai Hsiao;Hao-Chung Kuo;Chang-Ching Tu;Tian-Li Wu","doi":"10.1109/TED.2025.3536447","DOIUrl":"https://doi.org/10.1109/TED.2025.3536447","url":null,"abstract":"In this study, we explore the stability of third-quadrant characteristics in planar SiC power MOSFETs under high drain bias above the avalanche breakdown condition. By using experimental measurements and TCAD simulations, we analyze the mechanisms responsible for the positive shift of reverse turn-on voltage (<inline-formula> <tex-math>${V}_{text {rev}, text {on}}$ </tex-math></inline-formula>) during the third-quadrant operation. When the drain bias is increased from 1500 to 1620 V, obvious negative shifts in threshold voltage (<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>) and positive shifts in <inline-formula> <tex-math>${V}_{text {rev}, text {on}}$ </tex-math></inline-formula> are observed. The TCAD simulations attribute these shifts to the impact ionization caused by the high electric field inside the p-well regions. Furthermore, with the inclusion of positive fixed charges as the hole traps in the gate oxide near the SiO2/SiC interface, the simulation results show positive shifts of <inline-formula> <tex-math>${V}_{text {rev}, text {on}}$ </tex-math></inline-formula> consistent with the experimental results. These findings suggest that hole trapping caused by high drain bias above the avalanche breakdown condition can affect the stability of third-quadrant operation in planar SiC power MOSFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1270-1275"},"PeriodicalIF":2.9,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143519865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-11DOI: 10.1109/TED.2025.3535479
Leshan Qiu;Yun Bai;Yan Chen;Yiping Xiao;Jieqin Ding;Yidan Tang;Xiaoli Tian;Chaoming Liu;Xinyu Liu
This study designed a type of silicon carbide (SiC) split-gate MOSFETs (SG-MOSFETs) to evaluate the effect of SG structure on single-event gate oxide damage under heavy-ion irradiation. Comparisons with conventional MOSFETs (C-MOSFETs) by krypton (84Kr+18) ion irradiation experiments showed that SG-MOSFETs exhibited no significant improvement in single-event leakage current (SELC) degradation. However, following irradiation at a drain bias of 100 V, the gate bias at which the SG-MOSFET reached the current limit during postirradiation gate stress (PIGS) tests increased by approximately 60%, indicating SG-MOSFETs enhanced their irradiation reliability at low drain bias. In C-MOSFETs, the damage was located above the center of the JFET region within the active region. In contrast, in SG-MOSFETs, the damage was observed at the corner of the polysilicon gate in the main junction region. This shift in the damage location suggests that the SG structure moves the most sensitive point from the center of the JFET region to other areas. However, structure deviations during the manufacturing of the SG may introduce new sensitivities. Therefore, further design optimization is needed to improve irradiation survivability at higher drain biases.
{"title":"Effect of Split-Gate Structure in SiC MOSFET on Single-Event Gate Oxide Damage","authors":"Leshan Qiu;Yun Bai;Yan Chen;Yiping Xiao;Jieqin Ding;Yidan Tang;Xiaoli Tian;Chaoming Liu;Xinyu Liu","doi":"10.1109/TED.2025.3535479","DOIUrl":"https://doi.org/10.1109/TED.2025.3535479","url":null,"abstract":"This study designed a type of silicon carbide (SiC) split-gate MOSFETs (SG-MOSFETs) to evaluate the effect of SG structure on single-event gate oxide damage under heavy-ion irradiation. Comparisons with conventional MOSFETs (C-MOSFETs) by krypton (84Kr+18) ion irradiation experiments showed that SG-MOSFETs exhibited no significant improvement in single-event leakage current (SELC) degradation. However, following irradiation at a drain bias of 100 V, the gate bias at which the SG-MOSFET reached the current limit during postirradiation gate stress (PIGS) tests increased by approximately 60%, indicating SG-MOSFETs enhanced their irradiation reliability at low drain bias. In C-MOSFETs, the damage was located above the center of the JFET region within the active region. In contrast, in SG-MOSFETs, the damage was observed at the corner of the polysilicon gate in the main junction region. This shift in the damage location suggests that the SG structure moves the most sensitive point from the center of the JFET region to other areas. However, structure deviations during the manufacturing of the SG may introduce new sensitivities. Therefore, further design optimization is needed to improve irradiation survivability at higher drain biases.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1053-1059"},"PeriodicalIF":2.9,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A cost-effective yet efficient approach is proposed for suppressing the drain-bias-induced threshold voltage (${V} _{text {TH}}$ ) instability in Schottky-type p-gallium nitride (GaN) gate high electron mobility transistors (HEMTs). The proposed device consists of a source-connected metal layer on a dielectric layer in the gate-to-drain access region, which operates as a voltage seatbelt that restricts the voltage coupling to the p-GaN region from the drain within a defined range. By adjusting the dielectric thickness in the proposed structure, the voltage potential experienced by the p-GaN region is confined within a range of 3.1–22.3 V at a drain voltage (${V} _{text {DS}}$ ) of 400 V. In the scenario with a 3.1-V clamping voltage, the proposed configuration demonstrates a remarkable reduction of over 95% in ${V} _{text {TH}}$ shift caused by the floating nature of p-GaN, along with a reduction of 88% in ${V} _{text {TH}}$ shift induced by trapping effects. The proposed structure also enhances short-circuit robustness by reducing the saturation current density, while exerting only a minimal effect on the devices’ on-resistance (${R} _{text {ON}}$ ). The proposed structure offers room for balancing the tradeoff between the ${R} _{text {ON}}$ and the short-circuit robustness in practical applications.
{"title":"Suppression of Drain-Bias-Induced VTH Instability in Schottky-Type p-GaN Gate HEMTs With Voltage Seatbelt","authors":"Junting Chen;Haohao Chen;Yan Cheng;Jiongchong Fang;Zheng Wu;Junqiang Li;Jinjin Tang;Guosong Zeng;Kevin J. Chen;Mengyuan Hua","doi":"10.1109/TED.2025.3534168","DOIUrl":"https://doi.org/10.1109/TED.2025.3534168","url":null,"abstract":"A cost-effective yet efficient approach is proposed for suppressing the drain-bias-induced threshold voltage (<inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula>) instability in Schottky-type p-gallium nitride (GaN) gate high electron mobility transistors (HEMTs). The proposed device consists of a source-connected metal layer on a dielectric layer in the gate-to-drain access region, which operates as a voltage seatbelt that restricts the voltage coupling to the p-GaN region from the drain within a defined range. By adjusting the dielectric thickness in the proposed structure, the voltage potential experienced by the p-GaN region is confined within a range of 3.1–22.3 V at a drain voltage (<inline-formula> <tex-math>${V} _{text {DS}}$ </tex-math></inline-formula>) of 400 V. In the scenario with a 3.1-V clamping voltage, the proposed configuration demonstrates a remarkable reduction of over 95% in <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> shift caused by the floating nature of p-GaN, along with a reduction of 88% in <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> shift induced by trapping effects. The proposed structure also enhances short-circuit robustness by reducing the saturation current density, while exerting only a minimal effect on the devices’ on-resistance (<inline-formula> <tex-math>${R} _{text {ON}}$ </tex-math></inline-formula>). The proposed structure offers room for balancing the tradeoff between the <inline-formula> <tex-math>${R} _{text {ON}}$ </tex-math></inline-formula> and the short-circuit robustness in practical applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1041-1046"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-10DOI: 10.1109/TED.2024.3466112
Jung-Soo Ko;Alexander B. Shearer;Sol Lee;Kathryn Neilson;Marc Jaikissoon;Kwanpyo Kim;Stacey F. Bent;Eric Pop;Krishna C. Saraswat
Monolayer two-dimensional transition metal dichalcogenides (2-D TMDs) are promising semiconductors for future nanoscale transistors owing to their atomic thinness. However, atomic layer deposition (ALD) of gate dielectrics on 2-D TMDs has been difficult, and reducing the equivalent oxide thickness (EOT) with CMOS-compatible approaches remains a key challenge. Here, we report ultrathin top-gate dielectrics on monolayer TMDs using industry-friendly approaches, achieving 1-nm-scale top-gate EOT. We first show ALD of HfO2 on both monolayer WSe2 and MoS2 with a simple Si seed, enabling EOT $approx ~0.9$ nm with subthreshold swing SS $approx ~70$ mV/dec, low leakage, and negligible hysteresis on MoS2. We also demonstrate direct ALD of ultrathin alumina (AlOx) on monolayer MoS2 with good quality and uniformity using triethylaluminum (TEA) precursor, followed by ALD of HfO2. Combining our findings, we show that the threshold voltage (${V}_{text {T}}$ ) can be controlled by the interfacial dielectric layer on the 2-D transistor channel.
{"title":"Achieving 1-nm-Scale Equivalent Oxide Thickness Top-Gate Dielectric on Monolayer Transition Metal Dichalcogenide Transistors With CMOS-Friendly Approaches","authors":"Jung-Soo Ko;Alexander B. Shearer;Sol Lee;Kathryn Neilson;Marc Jaikissoon;Kwanpyo Kim;Stacey F. Bent;Eric Pop;Krishna C. Saraswat","doi":"10.1109/TED.2024.3466112","DOIUrl":"https://doi.org/10.1109/TED.2024.3466112","url":null,"abstract":"Monolayer two-dimensional transition metal dichalcogenides (2-D TMDs) are promising semiconductors for future nanoscale transistors owing to their atomic thinness. However, atomic layer deposition (ALD) of gate dielectrics on 2-D TMDs has been difficult, and reducing the equivalent oxide thickness (EOT) with CMOS-compatible approaches remains a key challenge. Here, we report ultrathin top-gate dielectrics on monolayer TMDs using industry-friendly approaches, achieving 1-nm-scale top-gate EOT. We first show ALD of HfO2 on both monolayer WSe2 and MoS2 with a simple Si seed, enabling EOT <inline-formula> <tex-math>$approx ~0.9$ </tex-math></inline-formula> nm with subthreshold swing SS <inline-formula> <tex-math>$approx ~70$ </tex-math></inline-formula> mV/dec, low leakage, and negligible hysteresis on MoS2. We also demonstrate direct ALD of ultrathin alumina (AlOx) on monolayer MoS2 with good quality and uniformity using triethylaluminum (TEA) precursor, followed by ALD of HfO2. Combining our findings, we show that the threshold voltage (<inline-formula> <tex-math>${V}_{text {T}}$ </tex-math></inline-formula>) can be controlled by the interfacial dielectric layer on the 2-D transistor channel.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1514-1519"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143580905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The carrier transport process in CdZnTe epitaxial films is significantly influenced by the substantial lattice mismatch between the CdZnTe films and GaAs substrates. To mitigate this issue, a uniform buffer layer was fabricated between the substrates and the CdZnTe films using the close-space sublimation (CSS). The impact of the buffer layers on surface roughness and crystalline quality of the films was investigated through optical microscopy, atomic force microscopy, and X-ray diffraction. The effects on the electrical performance were studied through I–V tests and alpha-particle energy spectra. The results demonstrate that a uniform buffer layer, grown at $400~^{circ }$ C for 5 min, significantly enhances the crystalline quality, resistivity, and carrier transport properties of the CdZnTe epitaxial films grown on low-resistance GaAs(001) substrates. After annealing at $400~^{circ }$ C in a Te2 atmosphere for 4 h, the energy resolution of the detector improved to 1.5% in vacuum and 11.23% in air conditions.
{"title":"Effects of Homogeneous Buffer Layer on the Crystalline Quality and Electrical Properties of CdZnTe Epitaxial Films","authors":"Xue Tian;Tingting Tan;Kun Cao;Xin Wan;Heming Wei;Ran Jiang;Yu Liu;Renying Cheng;Gangqiang Zha","doi":"10.1109/TED.2025.3531320","DOIUrl":"https://doi.org/10.1109/TED.2025.3531320","url":null,"abstract":"The carrier transport process in CdZnTe epitaxial films is significantly influenced by the substantial lattice mismatch between the CdZnTe films and GaAs substrates. To mitigate this issue, a uniform buffer layer was fabricated between the substrates and the CdZnTe films using the close-space sublimation (CSS). The impact of the buffer layers on surface roughness and crystalline quality of the films was investigated through optical microscopy, atomic force microscopy, and X-ray diffraction. The effects on the electrical performance were studied through I–V tests and alpha-particle energy spectra. The results demonstrate that a uniform buffer layer, grown at <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C for 5 min, significantly enhances the crystalline quality, resistivity, and carrier transport properties of the CdZnTe epitaxial films grown on low-resistance GaAs(001) substrates. After annealing at <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C in a Te2 atmosphere for 4 h, the energy resolution of the detector improved to 1.5% in vacuum and 11.23% in air conditions.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1235-1241"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To achieve superior electrical performance in vertical GaN-based devices on iron-doped semi-insulating gallium nitride (SI-GaN:Fe) substrates, a profound comprehension of the ohmic contact on the N-face of SI-GaN:Fe is imperative. The low carrier concentration and high bulk resistivity of SI-GaN:Fe, together with the complicated surface states of N-face, result in an excessively elevated specific contact resistance ($rho _{text {C}}$ ), posing a significant barrier to the realization of optimal ohmic contact. This study focuses on the surface treatments on the N-face of SI-GaN:Fe to reduce $rho _{text {C}}$ of ohmic contact on it. Surface band bending (BB), surface roughness, and oxidation are all considered to investigate the influence of surface treatments on the ohmic contact performance on the N-face of SI-GaN:Fe. Among various treatments, samples subjected to inductively coupled plasma (ICP) dry etching followed by a wet etching in hydrochloric acid solution (HCl:H2O =1:2) demonstrated the most pronounced reduction in $rho _{text {C}}$ . This is attributed to the surface BB after ICP etching, facilitating electron transition from the semiconductor to the metal. In addition, the N-face SI-GaN:Fe has a strong adsorption activity for oxygen, while the HCl solution effectively removes the surface GaOx layer and improves surface morphology, which is crucial for achieving ohmic contact. This study provides valuable insights into the fundamental physics of GaN ohmic contacts, thus enhancing the potential applicability of SI-GaN:Fe in vertical GaN-based devices.
{"title":"Influence of Surface Treatments on the Ohmic Contact Performance on the N-Face of Iron-Doped Semi-Insulating Freestanding GaN","authors":"Yuanhang Sun;Yumin Zhang;Xiao Wang;Hao Zhou;Songyuan Xia;Qizhi Zhu;Wei Liu;Jianfeng Wang;Ke Xu","doi":"10.1109/TED.2025.3534739","DOIUrl":"https://doi.org/10.1109/TED.2025.3534739","url":null,"abstract":"To achieve superior electrical performance in vertical GaN-based devices on iron-doped semi-insulating gallium nitride (SI-GaN:Fe) substrates, a profound comprehension of the ohmic contact on the N-face of SI-GaN:Fe is imperative. The low carrier concentration and high bulk resistivity of SI-GaN:Fe, together with the complicated surface states of N-face, result in an excessively elevated specific contact resistance (<inline-formula> <tex-math>$rho _{text {C}}$ </tex-math></inline-formula>), posing a significant barrier to the realization of optimal ohmic contact. This study focuses on the surface treatments on the N-face of SI-GaN:Fe to reduce <inline-formula> <tex-math>$rho _{text {C}}$ </tex-math></inline-formula> of ohmic contact on it. Surface band bending (BB), surface roughness, and oxidation are all considered to investigate the influence of surface treatments on the ohmic contact performance on the N-face of SI-GaN:Fe. Among various treatments, samples subjected to inductively coupled plasma (ICP) dry etching followed by a wet etching in hydrochloric acid solution (HCl:H2O =1:2) demonstrated the most pronounced reduction in <inline-formula> <tex-math>$rho _{text {C}}$ </tex-math></inline-formula>. This is attributed to the surface BB after ICP etching, facilitating electron transition from the semiconductor to the metal. In addition, the N-face SI-GaN:Fe has a strong adsorption activity for oxygen, while the HCl solution effectively removes the surface GaOx layer and improves surface morphology, which is crucial for achieving ohmic contact. This study provides valuable insights into the fundamental physics of GaN ohmic contacts, thus enhancing the potential applicability of SI-GaN:Fe in vertical GaN-based devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1027-1034"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-10DOI: 10.1109/TED.2025.3534172
Chan Heo;Jeongmin Son;M. Meyyappan;Kihyun Kim
Biosensors with label-free and rapid detection capabilities have a critical impact on healthcare and environmental monitoring. Biosensors based on field-effect transistor (FET) are one of the most common and successful forms. They can detect the charged biomolecules, but it is impossible to detect the neutral biomolecules. Dielectric-modulated (DM) FETs overcome these limitations. However, as biosensor dimensions shrink to nanoscale for integration into mobile devices, such miniaturization leads to severe leakage current increase followed by standby power consumption, thereby creating a need to mitigate these issues. Thyristor devices have been studied recently in the memory and logic semiconductor fields as a promising candidate due to their low leakage current, high density, and fast operating speed. Taking advantage of these attributes, a thyristor-based DM biosensor with a nanocavity in the gate region to host the analytes is designed in this study and its biosensing characteristics are analyzed using technology computer-aided design (TCAD) simulations. The thyristor-based sensor shows high-voltage sensitivity exceeding 1, indicating its potential in future biosensing.
{"title":"Design and Sensitivity Analysis of Double Gate Dielectric-Modulated Thyristor for Highly Sensitive Biosensing","authors":"Chan Heo;Jeongmin Son;M. Meyyappan;Kihyun Kim","doi":"10.1109/TED.2025.3534172","DOIUrl":"https://doi.org/10.1109/TED.2025.3534172","url":null,"abstract":"Biosensors with label-free and rapid detection capabilities have a critical impact on healthcare and environmental monitoring. Biosensors based on field-effect transistor (FET) are one of the most common and successful forms. They can detect the charged biomolecules, but it is impossible to detect the neutral biomolecules. Dielectric-modulated (DM) FETs overcome these limitations. However, as biosensor dimensions shrink to nanoscale for integration into mobile devices, such miniaturization leads to severe leakage current increase followed by standby power consumption, thereby creating a need to mitigate these issues. Thyristor devices have been studied recently in the memory and logic semiconductor fields as a promising candidate due to their low leakage current, high density, and fast operating speed. Taking advantage of these attributes, a thyristor-based DM biosensor with a nanocavity in the gate region to host the analytes is designed in this study and its biosensing characteristics are analyzed using technology computer-aided design (TCAD) simulations. The thyristor-based sensor shows high-voltage sensitivity exceeding 1, indicating its potential in future biosensing.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1377-1382"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-10DOI: 10.1109/TED.2025.3526127
Tom Jackson
The equations typically taught and used to estimate the threshold voltage for MOSFETs, based on the band bending in the MOSFET channel, are simple and easy to develop. However, they work well only for a subset of MOSFET types that do not include the MOSFETs of greatest interest today, including finFETs, nanosheet FETs, and most thin-film transistors (TFTs). This note provides an alternative, where threshold voltage is understood as moving the Fermi level to near the relevant band edge (conduction band minimum for n-channel MOSFETs or valence band maximum for p-channel MOSFETs).
{"title":"Thinking MOSFETs","authors":"Tom Jackson","doi":"10.1109/TED.2025.3526127","DOIUrl":"https://doi.org/10.1109/TED.2025.3526127","url":null,"abstract":"The equations typically taught and used to estimate the threshold voltage for MOSFETs, based on the band bending in the MOSFET channel, are simple and easy to develop. However, they work well only for a subset of MOSFET types that do not include the MOSFETs of greatest interest today, including finFETs, nanosheet FETs, and most thin-film transistors (TFTs). This note provides an alternative, where threshold voltage is understood as moving the Fermi level to near the relevant band edge (conduction band minimum for n-channel MOSFETs or valence band maximum for p-channel MOSFETs).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1520-1522"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143580902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-10DOI: 10.1109/TED.2025.3534152
Jibran Latif;Zhanliang Wang;Atif Jameel;Muhammad Khawar Nadeem;Bilawal Ali;Shaomeng Wang;Yubin Gong;Huarong Gong
A short double-grating rectangular waveguide (DGRW) slow wave structure (SWS) is designed and compared in detail with DGRW. Significant modifications are made to the corrugation geometry to optimize the dispersion characteristics, resulting in a broader frequency passband and enhanced frequency tunability. The high-frequency performance is analyzed in terms of dispersion and interaction impedance. The structure shows an interaction impedance of $1.5~Omega $ at 0.34 THz. To confirm the effectiveness of the proposed design, a 0.34-THz backward wave oscillator circuit is designed and fabricated comprising 160 periods. The circuit is assembled and cold-tested for scattering parameters. The results show ${S}_{{21}}$ values above −1.5 dB and ${S}_{{11}}$ below −20 dB for a broad frequency range. The beam-wave interaction simulations using a 30-kV, 30-mA electron beam, and 0.2-T focusing magnetic field show that the backward wave oscillator based on the proposed design achieves an average output power of 16 W at 0.34 THz, with a frequency tuning range of 95 GHz when compared with 57 GHz for the DGRW-based backward wave oscillator.
{"title":"Design and Cold Test of a Broadly Tunable Terahertz Short Double-Grating Rectangular Waveguide Slow Wave Structure","authors":"Jibran Latif;Zhanliang Wang;Atif Jameel;Muhammad Khawar Nadeem;Bilawal Ali;Shaomeng Wang;Yubin Gong;Huarong Gong","doi":"10.1109/TED.2025.3534152","DOIUrl":"https://doi.org/10.1109/TED.2025.3534152","url":null,"abstract":"A short double-grating rectangular waveguide (DGRW) slow wave structure (SWS) is designed and compared in detail with DGRW. Significant modifications are made to the corrugation geometry to optimize the dispersion characteristics, resulting in a broader frequency passband and enhanced frequency tunability. The high-frequency performance is analyzed in terms of dispersion and interaction impedance. The structure shows an interaction impedance of <inline-formula> <tex-math>$1.5~Omega $ </tex-math></inline-formula> at 0.34 THz. To confirm the effectiveness of the proposed design, a 0.34-THz backward wave oscillator circuit is designed and fabricated comprising 160 periods. The circuit is assembled and cold-tested for scattering parameters. The results show <inline-formula> <tex-math>${S}_{{21}}$ </tex-math></inline-formula> values above −1.5 dB and <inline-formula> <tex-math>${S}_{{11}}$ </tex-math></inline-formula> below −20 dB for a broad frequency range. The beam-wave interaction simulations using a 30-kV, 30-mA electron beam, and 0.2-T focusing magnetic field show that the backward wave oscillator based on the proposed design achieves an average output power of 16 W at 0.34 THz, with a frequency tuning range of 95 GHz when compared with 57 GHz for the DGRW-based backward wave oscillator.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1455-1461"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-06DOI: 10.1109/TED.2025.3532569
Zhiwei Chang;Zhong Cao;Wenli Shang;Guoxiang Shu;Yanyan Tian;Wenlong He
A newly proposed multimode circuit designed for extended interaction devices (EIDs) has demonstrated its ability to achieve multimode oscillation and multimode amplification in the millimeter-wave bands. Various distinctive features related to this multimode circuit, especially its discontinuous dispersion, have been observed. Herein, the dispersion characteristics of this multimode circuit are comprehensively studied. The dispersion is verified through theoretical analyses, simulation, and cold test; S-parameters, the “break” in the dispersion, and the high-order modes are analyzed. This study lays a scientific foundation for the multimode working mechanism and offers guidance for the optimal design of the multimode circuit. It can also be applied to the research of conventional extended interaction circuits and enlightens other potential multimode circuits designed for high-efficiency broadband electron beam-driven terahertz sources.
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