Pub Date : 2024-12-11DOI: 10.1109/TED.2024.3499935
Huihua Cheng;Jing Wang;James Kelly;Afesomeh Ofiare;Stephen Thoms;Chong Li
We present the design, fabrication, and characterization of InGaAs channel high electron mobility transistors (HEMTs) with ultralow contact resistance for millimeter-wave and subterahertz applications. The HEMT has a composite InGaAs channel and a 50-nm T-shaped gate, which was realized through a single-step electron beam lithography (EBL) process. A room temperature ohmic contact fabrication process achieving the lowest contact resistance of 15 m $Omega cdot $ mm has been developed with all room temperature process. The I–V measurements of the HEMTs at room temperature revealed a peak drain current of 0.75 A/mm and a transconductance of 1.4 S/mm. In standard 50- $Omega ~{S}$ -parameter measurements, the HEMTs exhibited a maximum gain of 10 dB at 170 GHz. However, utilizing an active load-pull measurement, the 50-nm HEMT shows a gain of 14.5 dB at 170 GHz and 2 dB at 270 GHz. The load-pull measurements also obtained power added efficiency (PAE) and 1-dB compression point of the HEMTs. The noise performance was characterized using a noise parameter system with source tuner between 2 and 50 GHz. A drift-diffusion model was used to benchmark the dc and RF performance of the devices, and good agreements have been achieved.
{"title":"HEMT With Ultralow Contact Resistance by Room Temperature Process With One-Step EBL T-Shape Gates for Subterahertz Applications: Design, Fabrication, and Characterization","authors":"Huihua Cheng;Jing Wang;James Kelly;Afesomeh Ofiare;Stephen Thoms;Chong Li","doi":"10.1109/TED.2024.3499935","DOIUrl":"https://doi.org/10.1109/TED.2024.3499935","url":null,"abstract":"We present the design, fabrication, and characterization of InGaAs channel high electron mobility transistors (HEMTs) with ultralow contact resistance for millimeter-wave and subterahertz applications. The HEMT has a composite InGaAs channel and a 50-nm T-shaped gate, which was realized through a single-step electron beam lithography (EBL) process. A room temperature ohmic contact fabrication process achieving the lowest contact resistance of 15 m\u0000<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>\u0000 mm has been developed with all room temperature process. The I–V measurements of the HEMTs at room temperature revealed a peak drain current of 0.75 A/mm and a transconductance of 1.4 S/mm. In standard 50-\u0000<inline-formula> <tex-math>$Omega ~{S}$ </tex-math></inline-formula>\u0000-parameter measurements, the HEMTs exhibited a maximum gain of 10 dB at 170 GHz. However, utilizing an active load-pull measurement, the 50-nm HEMT shows a gain of 14.5 dB at 170 GHz and 2 dB at 270 GHz. The load-pull measurements also obtained power added efficiency (PAE) and 1-dB compression point of the HEMTs. The noise performance was characterized using a noise parameter system with source tuner between 2 and 50 GHz. A drift-diffusion model was used to benchmark the dc and RF performance of the devices, and good agreements have been achieved.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"142-146"},"PeriodicalIF":2.9,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-11DOI: 10.1109/TED.2024.3510237
Jay Singh;Suman Gora;Mandeep Jangra;Arnab Datta
We report germanium (Ge) doping in tin oxide (SnO2), which led to achieving a record ON–OFF current ratio of ~109 and a subthreshold slope (SS) of 77 mV/decade in a bottom-gated n-type SnO2:Ge thin film transistor (TFT) with 40- $mu $ m channel length. Ge atomic percentage control to 12.2% during cosputtering of Ge and Sn in O2 plasma was shown to reduce oxygen vacancies (from 26.13% to 12.3%), which occurred due to Ge substitution in the Sn vacant sites of SnO2 lattice, leading to rearrangement of higher formation enthalpy Ge–O bonds. Low oxygen vacancies, therefore, impacted OFF current and SS of TFT with the Ge doped channel. Furthermore, for the same percent of atomic doping with Ge, field effect mobility was increased to 14.5 cm2/V-s, and barrier height of aluminum source–drain contacts with the SnO2:Ge channel was reduced from 0.69 to 0.47 eV, which were found suitable for enhancing drive current of SnO2:Ge TFT. Physical and electrical parameters of TFT fabricated with this exploratory channel material were characterized in detail.
{"title":"Germanium Doped SnO₂: An Exploratory Channel Material for High On–Off Current Ratio and Low Subthreshold Slope in n-Type SnO₂:Ge Thin Film Transistor","authors":"Jay Singh;Suman Gora;Mandeep Jangra;Arnab Datta","doi":"10.1109/TED.2024.3510237","DOIUrl":"https://doi.org/10.1109/TED.2024.3510237","url":null,"abstract":"We report germanium (Ge) doping in tin oxide (SnO2), which led to achieving a record ON–OFF current ratio of ~109 and a subthreshold slope (SS) of 77 mV/decade in a bottom-gated n-type SnO2:Ge thin film transistor (TFT) with 40-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m channel length. Ge atomic percentage control to 12.2% during cosputtering of Ge and Sn in O2 plasma was shown to reduce oxygen vacancies (from 26.13% to 12.3%), which occurred due to Ge substitution in the Sn vacant sites of SnO2 lattice, leading to rearrangement of higher formation enthalpy Ge–O bonds. Low oxygen vacancies, therefore, impacted OFF current and SS of TFT with the Ge doped channel. Furthermore, for the same percent of atomic doping with Ge, field effect mobility was increased to 14.5 cm2/V-s, and barrier height of aluminum source–drain contacts with the SnO2:Ge channel was reduced from 0.69 to 0.47 eV, which were found suitable for enhancing drive current of SnO2:Ge TFT. Physical and electrical parameters of TFT fabricated with this exploratory channel material were characterized in detail.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"282-288"},"PeriodicalIF":2.9,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-11DOI: 10.1109/TED.2024.3503540
Wei Wang;Qingmin Li;Daocheng Lu;Yujie Tang;Jian Wang;Hanwen Ren;Ruoqing Hong
Square voltage coupled high frequency and steep dv/dt is the main cause of interfacial discharge (ID) at the direct bond copper (DBC) substrate of power electronic devices. In this article, a high-frequency partial discharge test system at the junction of ceramic, metal layer, and silicone gel on DBC substrate is built. A partial discharge measurement method capable of shielding from strong electromagnetic interference (EMI) is proposed. The research results show that the rising time is shortened from 500 to 100 ns, and the ID inceptive voltage (IDIV) increases by 13.8%, but it is almost frequency independent. Second, the initial discharge phase is gradually advanced with the shortening of the rising time. The average and maximum discharge amplitude gradually increases and the number of discharges decreases. When the frequency rises from 10 to 50 kHz, the discharge phase percentage increases significantly. While the average discharge amplitude tends to increase and then decrease, the number of discharges increases substantially. Finally, it is found that the frequency is more harmful to the package insulation life than the voltage steepness. The above findings can provide a reference for the high-frequency discharges detection and the package insulation optimization for electronic devices.
{"title":"Interfacial Discharge Characteristics and Insulation Life Analysis of Package Insulation Under Square Voltage Coupled With High Frequency and Steep dv/dt","authors":"Wei Wang;Qingmin Li;Daocheng Lu;Yujie Tang;Jian Wang;Hanwen Ren;Ruoqing Hong","doi":"10.1109/TED.2024.3503540","DOIUrl":"https://doi.org/10.1109/TED.2024.3503540","url":null,"abstract":"Square voltage coupled high frequency and steep dv/dt is the main cause of interfacial discharge (ID) at the direct bond copper (DBC) substrate of power electronic devices. In this article, a high-frequency partial discharge test system at the junction of ceramic, metal layer, and silicone gel on DBC substrate is built. A partial discharge measurement method capable of shielding from strong electromagnetic interference (EMI) is proposed. The research results show that the rising time is shortened from 500 to 100 ns, and the ID inceptive voltage (IDIV) increases by 13.8%, but it is almost frequency independent. Second, the initial discharge phase is gradually advanced with the shortening of the rising time. The average and maximum discharge amplitude gradually increases and the number of discharges decreases. When the frequency rises from 10 to 50 kHz, the discharge phase percentage increases significantly. While the average discharge amplitude tends to increase and then decrease, the number of discharges increases substantially. Finally, it is found that the frequency is more harmful to the package insulation life than the voltage steepness. The above findings can provide a reference for the high-frequency discharges detection and the package insulation optimization for electronic devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"350-356"},"PeriodicalIF":2.9,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-11DOI: 10.1109/TED.2024.3506505
Marina Deng;Chhandak Mukherjee;Lucas Réveil;Akshay M. Arabhavi;Sara Hamzeloui;Colombo R. Bolognesi;Magali De Matos;Cristell Maneux
This article presents a new methodology to accurately characterize indium phosphide (InP) bipolar transistors up to 500 GHz. Following design optimization of RF test structures specifically developed for the on-wafer thru-reflect-line (TRL) calibration technique, InP/GaAsSb double heterojunction bipolar transistors have been successfully characterized up to 500 GHz. Moreover, the high current model (HICUM) compact model was validated against measurements for different operating conditions and various geometries for the first time up to 500 GHz. The physics-based compact model and the associated scalable parameter extraction flow allowed us to demonstrate the scalability of this terahertz (THz) InP double heterojunction transistor (DHBT) technology, offering possibilities for further design-level explorations. State-of-the-art cut-off frequencies of this THz transistor technology featuring ${f}_{text {MAX}}$ reaching 1 THz for transistor geometries with 0.15- $mu text {m}$ emitter widths were experimentally verified and confirmed by the compact model predictions.
本文提出了一种新的方法来精确表征高达500 GHz的磷化铟（InP）双极晶体管。在对专为晶圆上透反射线（TRL）校准技术开发的射频测试结构进行设计优化后，InP/GaAsSb双异质结双极晶体管已成功地进行了高达500 GHz的表征。此外，高电流模型（HICUM）紧凑型模型首次在高达500 GHz的不同工作条件和各种几何形状下进行了验证。基于物理的紧凑模型和相关的可扩展参数提取流程使我们能够展示这种太赫兹（THz） InP双异质结晶体管（DHBT）技术的可扩展性，为进一步的设计级探索提供了可能性。对于发射极宽度为0.15- $mu text {m}$的晶体管几何形状，最先进的太赫兹晶体管技术的截止频率${f}_{text {MAX}}$达到1太赫兹，实验验证并通过紧凑模型预测得到证实。
{"title":"InP/GaAsSb Double Heterojunction Bipolar Transistor Characterization and Compact Modeling up to 500 GHz","authors":"Marina Deng;Chhandak Mukherjee;Lucas Réveil;Akshay M. Arabhavi;Sara Hamzeloui;Colombo R. Bolognesi;Magali De Matos;Cristell Maneux","doi":"10.1109/TED.2024.3506505","DOIUrl":"https://doi.org/10.1109/TED.2024.3506505","url":null,"abstract":"This article presents a new methodology to accurately characterize indium phosphide (InP) bipolar transistors up to 500 GHz. Following design optimization of RF test structures specifically developed for the on-wafer thru-reflect-line (TRL) calibration technique, InP/GaAsSb double heterojunction bipolar transistors have been successfully characterized up to 500 GHz. Moreover, the high current model (HICUM) compact model was validated against measurements for different operating conditions and various geometries for the first time up to 500 GHz. The physics-based compact model and the associated scalable parameter extraction flow allowed us to demonstrate the scalability of this terahertz (THz) InP double heterojunction transistor (DHBT) technology, offering possibilities for further design-level explorations. State-of-the-art cut-off frequencies of this THz transistor technology featuring \u0000<inline-formula> <tex-math>${f}_{text {MAX}}$ </tex-math></inline-formula>\u0000 reaching 1 THz for transistor geometries with 0.15-\u0000<inline-formula> <tex-math>$mu text {m}$ </tex-math></inline-formula>\u0000 emitter widths were experimentally verified and confirmed by the compact model predictions.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"175-180"},"PeriodicalIF":2.9,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/TED.2024.3509385
Eslam Abubakr;Ashenafi Abadi;Masaaki Oshita;Shiro Saito;Hironori Suzuki;Tetsuo Kan
While Au is commonly utilized in semiconductor fabrication, its interaction with Si yields unstable contacts, posing potential reliability concerns. In this work, Cr interlayers were integrated to improve interface properties, enhance charge carrier transport within a plasmonic photodetector, and ensure long-term stability, demonstrated by consistent responses under zero bias and room-temperature conditions over the span of a year. The induced Fermi level shifts and Schottky barrier lowering to 0.59 eV, improving responsivity and extending the operation range beyond 1850 nm with increased sensitivity, allowing for precise reconstructive spectroscopy (RS). This is promising for reliable compound identification based on specific bond absorbance properties while scaling down IR spectroscopy to chip level, promoting applications like environmental monitoring and gas detection.
{"title":"Advanced Room-Temperature NIR Plasmonic Photodetection and Reconstructive Spectroscopy","authors":"Eslam Abubakr;Ashenafi Abadi;Masaaki Oshita;Shiro Saito;Hironori Suzuki;Tetsuo Kan","doi":"10.1109/TED.2024.3509385","DOIUrl":"https://doi.org/10.1109/TED.2024.3509385","url":null,"abstract":"While Au is commonly utilized in semiconductor fabrication, its interaction with Si yields unstable contacts, posing potential reliability concerns. In this work, Cr interlayers were integrated to improve interface properties, enhance charge carrier transport within a plasmonic photodetector, and ensure long-term stability, demonstrated by consistent responses under zero bias and room-temperature conditions over the span of a year. The induced Fermi level shifts and Schottky barrier lowering to 0.59 eV, improving responsivity and extending the operation range beyond 1850 nm with increased sensitivity, allowing for precise reconstructive spectroscopy (RS). This is promising for reliable compound identification based on specific bond absorbance properties while scaling down IR spectroscopy to chip level, promoting applications like environmental monitoring and gas detection.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"301-305"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/TED.2024.3509407
Keshari Nandan;Ateeb Naseer;Amit Agarwal;Somnath Bhowmick;Yogesh S. Chauhan
Making ultra-short gate-length transistors significantly contributes to scaling the contacted gate pitch. This, in turn, plays a vital role in achieving smaller standard logic cells for enhanced logic density scaling. As we push the boundaries of miniaturization, it is intriguing to consider that the ultimate limit of contacted gate pitch could be reached with remarkable 1 nm gate-length transistors. Here, we identify InSe, Bi2O2Se, and MoSi2N4 as potential 2-D semiconductors for 1 nm transistors with low contact resistance and outstanding interface properties. We employ a fully self-consistent ballistic quantum transport model starting from first-principle calculations. Our simulations show that the interplay between electrostatics and quantum tunneling influences the performance of these devices over the device design space. MoSi2N4 channels have the best immunity to quantum tunneling, and Bi2O2Se channel devices have the best electrostatics. We show that for a channel length of 12 nm, all the devices can deliver ${I}_{text {on}}/{I}_{text {off}} gt {10}^{{3}}$ , suitable for electronic applications, and Bi2O2Se is the best-performing channel material.
{"title":"Transistors Based on Novel 2-D Monolayer Semiconductors Bi₂O₂Se, InSe, and MoSi₂N₄ for Enhanced Logic Density Scaling","authors":"Keshari Nandan;Ateeb Naseer;Amit Agarwal;Somnath Bhowmick;Yogesh S. Chauhan","doi":"10.1109/TED.2024.3509407","DOIUrl":"https://doi.org/10.1109/TED.2024.3509407","url":null,"abstract":"Making ultra-short gate-length transistors significantly contributes to scaling the contacted gate pitch. This, in turn, plays a vital role in achieving smaller standard logic cells for enhanced logic density scaling. As we push the boundaries of miniaturization, it is intriguing to consider that the ultimate limit of contacted gate pitch could be reached with remarkable 1 nm gate-length transistors. Here, we identify InSe, Bi2O2Se, and MoSi2N4 as potential 2-D semiconductors for 1 nm transistors with low contact resistance and outstanding interface properties. We employ a fully self-consistent ballistic quantum transport model starting from first-principle calculations. Our simulations show that the interplay between electrostatics and quantum tunneling influences the performance of these devices over the device design space. MoSi2N4 channels have the best immunity to quantum tunneling, and Bi2O2Se channel devices have the best electrostatics. We show that for a channel length of 12 nm, all the devices can deliver \u0000<inline-formula> <tex-math>${I}_{text {on}}/{I}_{text {off}} gt {10}^{{3}}$ </tex-math></inline-formula>\u0000, suitable for electronic applications, and Bi2O2Se is the best-performing channel material.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"516-521"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/TED.2024.3508674
Limeng Shi;Hengyu Yu;Michael Jin;Jiashu Qian;Monikuntala Bhattacharya;Shiva Houshmand;Atsushi Shimbori;Marvin H. White;Anant K. Agarwal
The burn-in technique is a well-established screening method designed to eliminate early failures in the gate oxide of silicon carbide (SiC) MOSFETs. Despite its widespread application, optimizing the burn-in technique to improve both efficiency and feasibility remains a significant challenge. This study investigates the performance of commercial 1.2-kV SiC planar MOSFETs following the burn-in process, focusing on parameters, such as threshold voltage ( ${V}_{text {th}}text {)}$ , on -resistance ( ${R}_{text {on}}text {)}$ , and subthreshold hysteresis (Hy). The degradation characteristics of SiC MOSFETs during the burn-in and subsequent recovery processes are thoroughly analyzed. The results indicate that aggressive burn-in conditions, such as elevated oxide electric fields or prolonged stress durations, induce defect generation at or near the SiC/SiO2 interface. These new defects and pre-existing defects promote electron trapping, leading to an increase in ${V}_{text {th}}$ and ${R}_{text {on}}$ . Therefore, this study proposes two optimization strategies to refine the burn-in technique while maintaining the intrinsic performance of SiC MOSFETs under demanding conditions. The first approach involves identifying a critical stress duration to minimize defect generation during the burn-in process. The second approach utilizes pulse-mode burn-in technology, incorporating a negative gate bias to reduce the effects of electron trapping.
{"title":"Analysis and Optimization of Burn-In Techniques for Screening Commercial 1.2-kV SiC MOSFETs","authors":"Limeng Shi;Hengyu Yu;Michael Jin;Jiashu Qian;Monikuntala Bhattacharya;Shiva Houshmand;Atsushi Shimbori;Marvin H. White;Anant K. Agarwal","doi":"10.1109/TED.2024.3508674","DOIUrl":"https://doi.org/10.1109/TED.2024.3508674","url":null,"abstract":"The burn-in technique is a well-established screening method designed to eliminate early failures in the gate oxide of silicon carbide (SiC) MOSFETs. Despite its widespread application, optimizing the burn-in technique to improve both efficiency and feasibility remains a significant challenge. This study investigates the performance of commercial 1.2-kV SiC planar MOSFETs following the burn-in process, focusing on parameters, such as threshold voltage (\u0000<inline-formula> <tex-math>${V}_{text {th}}text {)}$ </tex-math></inline-formula>\u0000,\u0000<sc>on</small>\u0000-resistance (\u0000<inline-formula> <tex-math>${R}_{text {on}}text {)}$ </tex-math></inline-formula>\u0000, and subthreshold hysteresis (Hy). The degradation characteristics of SiC MOSFETs during the burn-in and subsequent recovery processes are thoroughly analyzed. The results indicate that aggressive burn-in conditions, such as elevated oxide electric fields or prolonged stress durations, induce defect generation at or near the SiC/SiO2 interface. These new defects and pre-existing defects promote electron trapping, leading to an increase in \u0000<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula>\u0000. Therefore, this study proposes two optimization strategies to refine the burn-in technique while maintaining the intrinsic performance of SiC MOSFETs under demanding conditions. The first approach involves identifying a critical stress duration to minimize defect generation during the burn-in process. The second approach utilizes pulse-mode burn-in technology, incorporating a negative gate bias to reduce the effects of electron trapping.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"331-337"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/TED.2024.3508653
Chao Wang;Xin Hao;Ding Lu;Chao Tan;Guoling Luo;Xiumin Xie;Qingmin Chen;Zungui Ke;Zegao Wang
Efficient p-type doping is at the top of the priority list for developing MoS2 electronics and optoelectronics devices due to MoS2 exhibiting the characteristics of an n-type semiconductor. However, implantation, a CMOS-compatible, controllable, and area-selective p-type doping process, is still unclear on MoS2. Here, it is reported that the phosphorus-implantation (P-implantation), a part of the CMOS process, can achieve p-type doping and extend cutoff wavelength from ~980 nm to a value over 1550 nm selectively by modulating implantation dose. By tuning the implantation dose, it was able to transform MoS2 from semiconductor to semimetal. Besides, we fabricate a gate-controlled MoS2 photodiode with spectral response from 450 to 1550 nm by P-implantation. The photodiode has 24 times more responsivity and 500 times the special detectivity than pristine transistor and achieves the responsivity of 6.1 A/W at 1550-nm illumination. In summary, this study opens a guideline for commercialization of MoS2 chips and enriches the application scenarios of MoS2 in NIR photodetection.
{"title":"Gate-Controlled MoS₂ Photodiode With Spectral Response From 450 to 1550 nm by Phosphorus-Implantation","authors":"Chao Wang;Xin Hao;Ding Lu;Chao Tan;Guoling Luo;Xiumin Xie;Qingmin Chen;Zungui Ke;Zegao Wang","doi":"10.1109/TED.2024.3508653","DOIUrl":"https://doi.org/10.1109/TED.2024.3508653","url":null,"abstract":"Efficient p-type doping is at the top of the priority list for developing MoS2 electronics and optoelectronics devices due to MoS2 exhibiting the characteristics of an n-type semiconductor. However, implantation, a CMOS-compatible, controllable, and area-selective p-type doping process, is still unclear on MoS2. Here, it is reported that the phosphorus-implantation (P-implantation), a part of the CMOS process, can achieve p-type doping and extend cutoff wavelength from ~980 nm to a value over 1550 nm selectively by modulating implantation dose. By tuning the implantation dose, it was able to transform MoS2 from semiconductor to semimetal. Besides, we fabricate a gate-controlled MoS2 photodiode with spectral response from 450 to 1550 nm by P-implantation. The photodiode has 24 times more responsivity and 500 times the special detectivity than pristine transistor and achieves the responsivity of 6.1 A/W at 1550-nm illumination. In summary, this study opens a guideline for commercialization of MoS2 chips and enriches the application scenarios of MoS2 in NIR photodetection.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"295-300"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micro-light emitting diode (micro-LED) is an essential component for the next-generation self-emissive display. However, existing studies often focus on specific parameters, such as chip size and current density, which restricts the overall understanding of micro-LEDs. This study presents a novel and extensive numerical analysis evaluating the impact of Mg-doped AlGaN electron blocking layers (EBLs) on InGaN-based micro-LED performance, covering current densities from 0.1 to 1000 A/cm2 and mesa sizes from 3 to $100~mu $ m for micro-LEDs to $gt 200~mu $ m for conventional LEDs. Unlike prior studies, our work uniquely investigates the interplay between EBL doping concentrations and micro-LED performance across multiple dimensions, providing new insights into carrier injection mechanisms. By varying the EBL doping levels ( $1times 10^{{19}}$ cm−3, $3times 10^{{18}}$ cm−3, and without EBL), we explored their impact on the band alignment at the last quantum barrier (LQB) and EBL interface, which is crucial for modulating carrier injections and increasing light output power density (LOPD). The results indicate that optimizing EBL properties improves electron blocking at low current densities and enhances hole injection at higher densities, effectively reducing the current leakage and enhancing the luminous efficiency of micro-LEDs across a broad range of current densities. This comprehensive analysis challenges conventional micro-LED design approaches by emphasizing the importance of EBL engineering to achieve balanced and efficient carrier injections under a variety of operating conditions, providing a pathway for future innovations in micro-LED technology.
{"title":"Impact of Mg-Doped AlGaN Electron Blocking Layer on Micro-LEDs: A Comparative Analysis of Carrier Transport Versus Chip Size and Current Density","authors":"Ying Jiang;Zhuoying Jiang;Mengyue Mo;Kai Huang;Zhaoxia Bi;Cheng Li;Jinchai Li;Junyong Kang;Rong Zhang","doi":"10.1109/TED.2024.3509822","DOIUrl":"https://doi.org/10.1109/TED.2024.3509822","url":null,"abstract":"Micro-light emitting diode (micro-LED) is an essential component for the next-generation self-emissive display. However, existing studies often focus on specific parameters, such as chip size and current density, which restricts the overall understanding of micro-LEDs. This study presents a novel and extensive numerical analysis evaluating the impact of Mg-doped AlGaN electron blocking layers (EBLs) on InGaN-based micro-LED performance, covering current densities from 0.1 to 1000 A/cm2 and mesa sizes from 3 to \u0000<inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>\u0000m for micro-LEDs to \u0000<inline-formula> <tex-math>$gt 200~mu $ </tex-math></inline-formula>\u0000m for conventional LEDs. Unlike prior studies, our work uniquely investigates the interplay between EBL doping concentrations and micro-LED performance across multiple dimensions, providing new insights into carrier injection mechanisms. By varying the EBL doping levels (\u0000<inline-formula> <tex-math>$1times 10^{{19}}$ </tex-math></inline-formula>\u0000 cm−3, \u0000<inline-formula> <tex-math>$3times 10^{{18}}$ </tex-math></inline-formula>\u0000 cm−3, and without EBL), we explored their impact on the band alignment at the last quantum barrier (LQB) and EBL interface, which is crucial for modulating carrier injections and increasing light output power density (LOPD). The results indicate that optimizing EBL properties improves electron blocking at low current densities and enhances hole injection at higher densities, effectively reducing the current leakage and enhancing the luminous efficiency of micro-LEDs across a broad range of current densities. This comprehensive analysis challenges conventional micro-LED design approaches by emphasizing the importance of EBL engineering to achieve balanced and efficient carrier injections under a variety of operating conditions, providing a pathway for future innovations in micro-LED technology.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"306-311"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/TED.2024.3508660
Yan Chen;Yun Bai;Antao Wang;Leshan Qiu;Jieqin Ding;Yidan Tang;Xiaoli Tian;Jilong Hao;Xuan Li;Xinyu Liu
In this article, the electron irradiation coupling short circuit (SC) characteristics of 4H-silicon carbide (SiC) MOSFET are studied. The SC influence mechanism of electron irradiation coupling is proposed, and the influence of minority carrier lifetime on the SC characteristics of the device after irradiation is further studied. The 4H-SiC MOSFET and 4H-SiC wafer are irradiated by 2-MeV electrons. The changes in static parameters of 4H-SiC MOSFET are analyzed, and the SC characteristics of 4H-SiC MOSFET under electron irradiation coupling are studied by the limit SC (LSC) test method. The results show that after irradiation, the SC peak current of 4H-SiC MOSFET increases by 9.6%, the critical SC failure time ( ${t}_{text {crit}}$ ) decreases by 10.85%, and the critical SC failure energy ( ${E}_{text {crit}}$ ) decreases by 5.29%. MOSFET’s LSC failure mechanism after electron irradiation is parasitic BJT conduction. Through TCAD simulation and theoretical derivation, it is proved that the increase of the base current is the main cause of parasitic BJT conduction, and the decrease of carrier lifetime will trigger parasitic BJT conduction earlier. The minority carrier lifetime can be reduced by 97% after electron irradiation. The influence mechanism of electron irradiation on SC characteristics is verified by TCAD simulation. The total ion dose effect will increase the SC peak current, and the displacement effect will significantly reduce the minority carrier lifetime, thus reducing the SC capacity of the device. The simulation results are consistent with the experimental results.
{"title":"A Study on Short Circuit Characteristics of 4H-SiC MOSFET Coupled With Electron Irradiation","authors":"Yan Chen;Yun Bai;Antao Wang;Leshan Qiu;Jieqin Ding;Yidan Tang;Xiaoli Tian;Jilong Hao;Xuan Li;Xinyu Liu","doi":"10.1109/TED.2024.3508660","DOIUrl":"https://doi.org/10.1109/TED.2024.3508660","url":null,"abstract":"In this article, the electron irradiation coupling short circuit (SC) characteristics of 4H-silicon carbide (SiC) MOSFET are studied. The SC influence mechanism of electron irradiation coupling is proposed, and the influence of minority carrier lifetime on the SC characteristics of the device after irradiation is further studied. The 4H-SiC MOSFET and 4H-SiC wafer are irradiated by 2-MeV electrons. The changes in static parameters of 4H-SiC MOSFET are analyzed, and the SC characteristics of 4H-SiC MOSFET under electron irradiation coupling are studied by the limit SC (LSC) test method. The results show that after irradiation, the SC peak current of 4H-SiC MOSFET increases by 9.6%, the critical SC failure time (\u0000<inline-formula> <tex-math>${t}_{text {crit}}$ </tex-math></inline-formula>\u0000) decreases by 10.85%, and the critical SC failure energy (\u0000<inline-formula> <tex-math>${E}_{text {crit}}$ </tex-math></inline-formula>\u0000) decreases by 5.29%. MOSFET’s LSC failure mechanism after electron irradiation is parasitic BJT conduction. Through TCAD simulation and theoretical derivation, it is proved that the increase of the base current is the main cause of parasitic BJT conduction, and the decrease of carrier lifetime will trigger parasitic BJT conduction earlier. The minority carrier lifetime can be reduced by 97% after electron irradiation. The influence mechanism of electron irradiation on SC characteristics is verified by TCAD simulation. The total ion dose effect will increase the SC peak current, and the displacement effect will significantly reduce the minority carrier lifetime, thus reducing the SC capacity of the device. The simulation results are consistent with the experimental results.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"323-330"},"PeriodicalIF":2.9,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：