Pub Date : 2024-10-08DOI: 10.1109/TED.2024.3469161
Seung Hyeop Han;Haesung Kim;Jong-Ho Bae;Sung-Jin Choi;Dae Hwan Kim;Dong Myong Kim
The subgap density of states [ ${g}_{text {DOS}}$ (E)] is a critical parameter governing the electrical characteristics and short-/long-term reliability of amorphous oxide semiconductor thin-film transistors (AOS TFTs). In this study, we propose an advanced technique for ${g}_{text {DOS}}$ (E) in AOS TFTs through the photonic capacitance-voltage (C–V) characterization. We focused on the gate voltage ( ${V}_{text {G}}$ ) dependence of the photovoltaic effect (PVE), which has not been considered in previous studies. The PVE strongly depends on the amount of ${g}_{text {DOS}}$ (E) reacting in each energy interval, requiring the consideration of ${V}_{text {G}}$ -dependency. Furthermore, we incorporated the ${V}_{text {G}}$ -dependency of the parasitic capacitance into the equivalent capacitance model, resulting in a more accurate extraction of ${g}_{text {DOS}}$ (E). For validation, the proposed method was applied to amorphous indium-gallium–zinc-oxide (a-IGZO) TFTs with an optical source with $lambda = 532$ nm and obtained ${N}_{text {T}} = 6times 10^{{15}}$ cm $^{-{3}} cdot $ eV $^{-{1}}$ , ${N}_{text {D}} = 7times 10^{{13}}$ cm $^{-{3}} cdot $ eV−1, ${kT}_{text {T}} = 0.28$ eV, and ${kT}_{text {D}} = 0.7$ eV of the exponential and gaussian superposed model of ${g}_{text {DOS}}$ (E). The proposed method is expected to be a useful tool in the characterization of AOS TFTs.
{"title":"Photovoltaic Effect De-Embedded Photonic C–V Characterization of Subgap Density of States in Amorphous Oxide Semiconductor Thin-Film Transistors","authors":"Seung Hyeop Han;Haesung Kim;Jong-Ho Bae;Sung-Jin Choi;Dae Hwan Kim;Dong Myong Kim","doi":"10.1109/TED.2024.3469161","DOIUrl":"https://doi.org/10.1109/TED.2024.3469161","url":null,"abstract":"The subgap density of states [\u0000<inline-formula> <tex-math>${g}_{text {DOS}}$ </tex-math></inline-formula>\u0000(E)] is a critical parameter governing the electrical characteristics and short-/long-term reliability of amorphous oxide semiconductor thin-film transistors (AOS TFTs). In this study, we propose an advanced technique for \u0000<inline-formula> <tex-math>${g}_{text {DOS}}$ </tex-math></inline-formula>\u0000(E) in AOS TFTs through the photonic capacitance-voltage (C–V) characterization. We focused on the gate voltage (\u0000<inline-formula> <tex-math>${V}_{text {G}}$ </tex-math></inline-formula>\u0000) dependence of the photovoltaic effect (PVE), which has not been considered in previous studies. The PVE strongly depends on the amount of \u0000<inline-formula> <tex-math>${g}_{text {DOS}}$ </tex-math></inline-formula>\u0000(E) reacting in each energy interval, requiring the consideration of \u0000<inline-formula> <tex-math>${V}_{text {G}}$ </tex-math></inline-formula>\u0000-dependency. Furthermore, we incorporated the \u0000<inline-formula> <tex-math>${V}_{text {G}}$ </tex-math></inline-formula>\u0000-dependency of the parasitic capacitance into the equivalent capacitance model, resulting in a more accurate extraction of \u0000<inline-formula> <tex-math>${g}_{text {DOS}}$ </tex-math></inline-formula>\u0000(E). For validation, the proposed method was applied to amorphous indium-gallium–zinc-oxide (a-IGZO) TFTs with an optical source with \u0000<inline-formula> <tex-math>$lambda = 532$ </tex-math></inline-formula>\u0000 nm and obtained \u0000<inline-formula> <tex-math>${N}_{text {T}} = 6times 10^{{15}}$ </tex-math></inline-formula>\u0000 cm\u0000<inline-formula> <tex-math>$^{-{3}} cdot $ </tex-math></inline-formula>\u0000eV\u0000<inline-formula> <tex-math>$^{-{1}}$ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>${N}_{text {D}} = 7times 10^{{13}}$ </tex-math></inline-formula>\u0000 cm\u0000<inline-formula> <tex-math>$^{-{3}} cdot $ </tex-math></inline-formula>\u0000eV−1, \u0000<inline-formula> <tex-math>${kT}_{text {T}} = 0.28$ </tex-math></inline-formula>\u0000 eV, and \u0000<inline-formula> <tex-math>${kT}_{text {D}} = 0.7$ </tex-math></inline-formula>\u0000 eV of the exponential and gaussian superposed model of \u0000<inline-formula> <tex-math>${g}_{text {DOS}}$ </tex-math></inline-formula>\u0000(E). The proposed method is expected to be a useful tool in the characterization of AOS TFTs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A single transistor latch (STL), driven by impact ionization (II) and band-to-band tunneling (BTBT), plays a crucial role in threshold switching in a thin-body MOSFET. The inherent challenge lies in the high latch-up voltage ( ${V}_{text {LU}}$ ) required to trigger the STL because the II and BTBT mechanisms rely on higher voltages. Moreover, thus far, strategies for adjusting the ${V}_{text {LU}}$ level have been limited to altering process parameters or materials that are difficult to change once decided. Therefore, these methods do not provide dynamic controllability of ${V}_{text {LU}}$ . The high ${V}_{text {LU}}$ and lack of tunability limit and hinder various applications utilizing STL. In this study, ${V}_{text {LU}}$ was experimentally reduced to near 1 V by asymmetric biasing, i.e., electrically separating the top of the body (ToB) and the bottom of the body (BoB) through front-gate (FG) biasing and back-gate (BG) biasing. The underlying physics of this reduction was elucidated by means of TCAD simulation through the analysis of energy band diagrams, II rates, and BTBT rates. A significant reduction in ${V}_{text {LU}}$ was achieved solely through electrical modulation.
{"title":"Single Transistor Latch Near 1 V With Asymmetric Biasing in a MOSFET","authors":"Sang-Won Lee;Seung-Il Kim;Seong-Yun Yun;Joon-Kyu Han;Ji-Man Yu;Joon-Ha Son;Yang-Kyu Choi","doi":"10.1109/TED.2024.3469181","DOIUrl":"https://doi.org/10.1109/TED.2024.3469181","url":null,"abstract":"A single transistor latch (STL), driven by impact ionization (II) and band-to-band tunneling (BTBT), plays a crucial role in threshold switching in a thin-body MOSFET. The inherent challenge lies in the high latch-up voltage (\u0000<inline-formula> <tex-math>${V}_{text {LU}}$ </tex-math></inline-formula>\u0000) required to trigger the STL because the II and BTBT mechanisms rely on higher voltages. Moreover, thus far, strategies for adjusting the \u0000<inline-formula> <tex-math>${V}_{text {LU}}$ </tex-math></inline-formula>\u0000 level have been limited to altering process parameters or materials that are difficult to change once decided. Therefore, these methods do not provide dynamic controllability of \u0000<inline-formula> <tex-math>${V}_{text {LU}}$ </tex-math></inline-formula>\u0000. The high \u0000<inline-formula> <tex-math>${V}_{text {LU}}$ </tex-math></inline-formula>\u0000 and lack of tunability limit and hinder various applications utilizing STL. In this study, \u0000<inline-formula> <tex-math>${V}_{text {LU}}$ </tex-math></inline-formula>\u0000 was experimentally reduced to near 1 V by asymmetric biasing, i.e., electrically separating the top of the body (ToB) and the bottom of the body (BoB) through front-gate (FG) biasing and back-gate (BG) biasing. The underlying physics of this reduction was elucidated by means of TCAD simulation through the analysis of energy band diagrams, II rates, and BTBT rates. A significant reduction in \u0000<inline-formula> <tex-math>${V}_{text {LU}}$ </tex-math></inline-formula>\u0000 was achieved solely through electrical modulation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, a 1.2-kV conventional MOSFET and a MOSFET integrated with a junction barrier Schottky diode (JBSFET) were fabricated with a consistent process flow. The electrical characteristics of MOSFET and JBSFET, including static performance, structural capacitance, and switching performance have been systematically analyzed in the temperature range of 80–300 K. Experimental results show that the third quadrant voltage drop of JBSFET is smaller than MOSFET and hardly changes with decreasing temperature. The gate-drain capacitance of MOSFET and JBSFET increases by more than 50% at 80 K, due to the cryogenic incomplete ionization of the P-Base. The switching performance of the two devices is affected by the temperature dependence of threshold voltage, structural capacitance, and interface state charges, manifesting in a reduction in turn-on speed and voltage tailing at cryogenic temperatures. According to the results, JBSFET has better potential for low-temperature applications due to its stable third-quadrant characteristics. The cryogenic incomplete ionization of the P-Base region has a significant impact on the output characteristics, structural capacitance, and switching performance.
{"title":"Investigation of Electrical Characteristics on SiC MOSFET and JBS-Integrated MOSFET at Cryogenic Temperatures","authors":"Zhaoyuan Gu;Mingchao Yang;Yi Yang;Weihua Liu;Chuanyu Han;Xin Li;Li Geng;Yue Hao","doi":"10.1109/TED.2024.3467211","DOIUrl":"https://doi.org/10.1109/TED.2024.3467211","url":null,"abstract":"In this article, a 1.2-kV conventional MOSFET and a MOSFET integrated with a junction barrier Schottky diode (JBSFET) were fabricated with a consistent process flow. The electrical characteristics of MOSFET and JBSFET, including static performance, structural capacitance, and switching performance have been systematically analyzed in the temperature range of 80–300 K. Experimental results show that the third quadrant voltage drop of JBSFET is smaller than MOSFET and hardly changes with decreasing temperature. The gate-drain capacitance of MOSFET and JBSFET increases by more than 50% at 80 K, due to the cryogenic incomplete ionization of the P-Base. The switching performance of the two devices is affected by the temperature dependence of threshold voltage, structural capacitance, and interface state charges, manifesting in a reduction in turn-on speed and voltage tailing at cryogenic temperatures. According to the results, JBSFET has better potential for low-temperature applications due to its stable third-quadrant characteristics. The cryogenic incomplete ionization of the P-Base region has a significant impact on the output characteristics, structural capacitance, and switching performance.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-08DOI: 10.1109/TED.2024.3469908
Kynghwan Lee;Jungpyo Hong;Bong Jin Kuh;Daewon Ha;Sangjin Hyun;Sujin Ahn;Jaihyuk Song
Multibridge channel-ferroelectric field-effect transistor (MBC-FeFET) with metal-ferroelectric-metal-insulator-silicon (MFMIS) gate-stack is an advanced noble memory device, which is compatible with a 3-nm node technology logic device. Thanks to the wide effective channel width of the device’s stacked nanosheet (NS), the capacitance ratio of the interfacial layer (IL) and ferroelectric layer ( ${C}_{text {IL}}$ / ${C}_{text {FE}}$ ) can be maximized without area penalty, significantly improving memory window (MW) and endurance characteristics. In this work, we developed analytical compact models of memory characteristics for MFMIS gate-stack-based MBC-FeFET. Also, using this model, the gate-stack design guidelines were presented. As a result, the MW becomes three times larger, and the electric field in the IL layer ( ${E}_{text {IL}}$ ) becomes 0.17 times smaller after optimization. This is 21 times larger MW compared to a planar FeFET with initial gate-stack parameters applied.
{"title":"Design Guidelines of Multibridge Channel-Ferroelectric FET for 3-nm Node and Beyond","authors":"Kynghwan Lee;Jungpyo Hong;Bong Jin Kuh;Daewon Ha;Sangjin Hyun;Sujin Ahn;Jaihyuk Song","doi":"10.1109/TED.2024.3469908","DOIUrl":"https://doi.org/10.1109/TED.2024.3469908","url":null,"abstract":"Multibridge channel-ferroelectric field-effect transistor (MBC-FeFET) with metal-ferroelectric-metal-insulator-silicon (MFMIS) gate-stack is an advanced noble memory device, which is compatible with a 3-nm node technology logic device. Thanks to the wide effective channel width of the device’s stacked nanosheet (NS), the capacitance ratio of the interfacial layer (IL) and ferroelectric layer (\u0000<inline-formula> <tex-math>${C}_{text {IL}}$ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>${C}_{text {FE}}$ </tex-math></inline-formula>\u0000) can be maximized without area penalty, significantly improving memory window (MW) and endurance characteristics. In this work, we developed analytical compact models of memory characteristics for MFMIS gate-stack-based MBC-FeFET. Also, using this model, the gate-stack design guidelines were presented. As a result, the MW becomes three times larger, and the electric field in the IL layer (\u0000<inline-formula> <tex-math>${E}_{text {IL}}$ </tex-math></inline-formula>\u0000) becomes 0.17 times smaller after optimization. This is 21 times larger MW compared to a planar FeFET with initial gate-stack parameters applied.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, the Gaussian density of states (DOSs) in organic semiconductors is taken into account in order to derive a charge-based compact model for high-speed organic transistors. This physics-based analytical solution provides a continues current equation from below to above threshold regions with considering the deep and shallow trap densities in the organic material, power-law mobility model, and contact resistances effects. The proposed model is verified with the experimental data of our fabricated organic permeable base transistor (OPBT) and shows good agreement with the measurements. OPBTs are of great interest as vertical organic transistors and stand out due to their excellent performance, such as low-voltage operation and high transit frequency.
{"title":"Gaussian DOS Charge-Based DC Compact Modeling of High-Speed Organic Transistors","authors":"Elahe Rastegar Pashaki;Jakob Leise;Benjamin Iniguez;Hans Kleemann;Alexander Kloes;Ghader Darbandy","doi":"10.1109/TED.2024.3462652","DOIUrl":"https://doi.org/10.1109/TED.2024.3462652","url":null,"abstract":"In this article, the Gaussian density of states (DOSs) in organic semiconductors is taken into account in order to derive a charge-based compact model for high-speed organic transistors. This physics-based analytical solution provides a continues current equation from below to above threshold regions with considering the deep and shallow trap densities in the organic material, power-law mobility model, and contact resistances effects. The proposed model is verified with the experimental data of our fabricated organic permeable base transistor (OPBT) and shows good agreement with the measurements. OPBTs are of great interest as vertical organic transistors and stand out due to their excellent performance, such as low-voltage operation and high transit frequency.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Silicon-based heterojunction phototransistors (HPTs) with their advantages of high internal gain, high responsivity, and compatibility with CMOS processes have attracted much attention in high-sensitivity light detection. In this article, the SiGe/Si HPT with an illuminated area of $50times 50~mu $ m2 for high responsivity and sensitivity was designed and fabricated. The optical responsivity of the fabricated SiGe/Si HPT reached 1.717 and 12.379 A/W for 405 and 650 nm, their specific detectivity values were $1.54times 10^{{10}}$ and $11.16times 10^{{10}}~text {cm}cdot text {Hz}^{{0.5}}cdot text {W}^{-{1}}$ , respectively. An analytic model was developed to discuss current amplification for different wavelengths when considering absorption efficiency and carrier transportation. The emitter thickness was optimized as 60 nm to significantly improve the current amplification under short wavelengths. The achieved optical responsivity of the optimized SiGe/Si HPT for 405 and 650 nm respectively were 13.756 and 13.904 A/W, and the specific detectivity were $12.41times 10^{{10}}$ and $12.54times 10^{{10}}~text {cm}cdot text {Hz}^{{0.5}} cdot text {W}^{-{1}}$ .
{"title":"A SiGe/Si Heterojunction Phototransistor for High Sensitivity Light Detection","authors":"Hongyun Xie;Xiaoting Shen;Yunpeng Ge;Zimai Xu;Ziming Liu;Yudong Ma;Weicong Na;Dongyue Jin;Wanrong Zhang","doi":"10.1109/TED.2024.3467218","DOIUrl":"https://doi.org/10.1109/TED.2024.3467218","url":null,"abstract":"Silicon-based heterojunction phototransistors (HPTs) with their advantages of high internal gain, high responsivity, and compatibility with CMOS processes have attracted much attention in high-sensitivity light detection. In this article, the SiGe/Si HPT with an illuminated area of \u0000<inline-formula> <tex-math>$50times 50~mu $ </tex-math></inline-formula>\u0000m2 for high responsivity and sensitivity was designed and fabricated. The optical responsivity of the fabricated SiGe/Si HPT reached 1.717 and 12.379 A/W for 405 and 650 nm, their specific detectivity values were \u0000<inline-formula> <tex-math>$1.54times 10^{{10}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$11.16times 10^{{10}}~text {cm}cdot text {Hz}^{{0.5}}cdot text {W}^{-{1}}$ </tex-math></inline-formula>\u0000, respectively. An analytic model was developed to discuss current amplification for different wavelengths when considering absorption efficiency and carrier transportation. The emitter thickness was optimized as 60 nm to significantly improve the current amplification under short wavelengths. The achieved optical responsivity of the optimized SiGe/Si HPT for 405 and 650 nm respectively were 13.756 and 13.904 A/W, and the specific detectivity were \u0000<inline-formula> <tex-math>$12.41times 10^{{10}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$12.54times 10^{{10}}~text {cm}cdot text {Hz}^{{0.5}} cdot text {W}^{-{1}}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-08DOI: 10.1109/TED.2024.3469187
L. Tondelli;R. Asanovski;A. J. Scholten;T. V. Dinh;S.-W. Tam;R. M. T. Pijper;L. Selmi
Accurate determination of thermal resistances having a clear physical interpretation is crucial for analyzing self-heating effects (SHEs) in bulk FinFETs and ensuring reliable circuit operation. In this article, we use extensive electrothermal simulations, calibrated against experiments, to validate a popular method to monitor SHEs based on the measured AC output conductance. The results confirm that nanoscale silicon fins exhibit degraded thermal conductivity compared with the bulk silicon case. Then, we explore the relationship between the temperature extracted by the output conductance method and the maximum temperature inside the fin (which is a useful parameter to study device reliability) as a function of device bias and dimensions, providing a few projections toward scaled technology nodes. Our results show that the following hold: 1) the overtemperature extracted with the AC output conductance method represents an average overtemperature across the device active area and 2) the AC conductance method largely underestimates the peak temperature of long-channel devices; less so for short-channel ones. In this latter case, however, the difference between the above temperatures changes appreciably as a function of gate voltage.
准确测定热阻并给出清晰的物理解释，对于分析块状 FinFET 的自热效应 (SHE) 和确保电路可靠运行至关重要。在本文中，我们使用了大量电热模拟，并根据实验进行了校准，以验证一种基于测量的交流输出电导监测 SHE 的常用方法。结果证实，与块状硅相比，纳米级硅翅片的热传导率有所下降。然后，我们探讨了输出电导法提取的温度与鳍片内部最高温度（这是研究器件可靠性的有用参数）之间的关系，并将其作为器件偏置和尺寸的函数，提供了一些对缩放技术节点的预测。我们的结果表明以下几点是成立的：1) 用交流输出电导法提取的超温代表了整个器件有效区域的平均超温；2) 交流电导法在很大程度上低估了长沟道器件的峰值温度，而对短沟道器件的低估则较少。不过，在后一种情况下，上述温度之间的差异会随着栅极电压的变化而发生明显变化。
{"title":"Understanding the Self-Heating Effects Measured With the AC Output Conductance Method in Advanced FinFET Nodes","authors":"L. Tondelli;R. Asanovski;A. J. Scholten;T. V. Dinh;S.-W. Tam;R. M. T. Pijper;L. Selmi","doi":"10.1109/TED.2024.3469187","DOIUrl":"https://doi.org/10.1109/TED.2024.3469187","url":null,"abstract":"Accurate determination of thermal resistances having a clear physical interpretation is crucial for analyzing self-heating effects (SHEs) in bulk FinFETs and ensuring reliable circuit operation. In this article, we use extensive electrothermal simulations, calibrated against experiments, to validate a popular method to monitor SHEs based on the measured AC output conductance. The results confirm that nanoscale silicon fins exhibit degraded thermal conductivity compared with the bulk silicon case. Then, we explore the relationship between the temperature extracted by the output conductance method and the maximum temperature inside the fin (which is a useful parameter to study device reliability) as a function of device bias and dimensions, providing a few projections toward scaled technology nodes. Our results show that the following hold: 1) the overtemperature extracted with the AC output conductance method represents an average overtemperature across the device active area and 2) the AC conductance method largely underestimates the peak temperature of long-channel devices; less so for short-channel ones. In this latter case, however, the difference between the above temperatures changes appreciably as a function of gate voltage.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-08DOI: 10.1109/TED.2024.3469165
Yuzhi Li;Guangshuo Cai;Biao Tang;Shenghan Zou;Linfeng Lan;Zheng Gong
In this work, we proposed and demonstrated etch-stopper-layer (ESL) structured indium-gallium-zinc oxide (IGZO) Schottky-barrier thin-film transistors (SBTFTs) with hybrid Ohmic/Schottky contacts utilizing single-layer Cu source/drain (S/D) electrodes. In this unique yet simple configuration, the AlOx layer deposited on the IGZO layer serves not only as a protection layer for the IGZO channel during S/D electrode etching but also as an interfacial layer for modulating the Schottky barrier of the Cu/IGZO contact. This, combined with quasi-Ohmic contact of Cu/IGZO, enables the formation of hybrid contacts based on a single-layer Cu electrode. The ESL-structured SBTFTs with hybrid contacts show a two-order magnitude increase in saturation current ( ${I}_{text {dsat}}$ ) compared to SBTFTs solely based on Schottky contacts, with high intrinsic gains exceeding 1500 at a gate voltage of 10 V, and good stability under gate bias and illumination stress. Utilizing technology computer-aided design (TCAD) simulation, the operation of ESL-structured IGZO SBTFTs was fully elucidated. Also, this study conducted a thorough investigation and analysis of the influence of source-drain gaps and Schottky contact lengths at the source on ${I}_{text {dsat}}$ and saturation voltage ( ${V}_{text {dsat}}$ ) for the devices. This work provides a promising route to fabricate low-cost metal oxide SBTFTs with significantly increased ${I}_{text {dsat}}$ .
{"title":"High-Performance Schottky-Barrier IGZO Thin-Film Transistors Based on Ohmic/Schottky Hybrid Contacts","authors":"Yuzhi Li;Guangshuo Cai;Biao Tang;Shenghan Zou;Linfeng Lan;Zheng Gong","doi":"10.1109/TED.2024.3469165","DOIUrl":"https://doi.org/10.1109/TED.2024.3469165","url":null,"abstract":"In this work, we proposed and demonstrated etch-stopper-layer (ESL) structured indium-gallium-zinc oxide (IGZO) Schottky-barrier thin-film transistors (SBTFTs) with hybrid Ohmic/Schottky contacts utilizing single-layer Cu source/drain (S/D) electrodes. In this unique yet simple configuration, the AlOx layer deposited on the IGZO layer serves not only as a protection layer for the IGZO channel during S/D electrode etching but also as an interfacial layer for modulating the Schottky barrier of the Cu/IGZO contact. This, combined with quasi-Ohmic contact of Cu/IGZO, enables the formation of hybrid contacts based on a single-layer Cu electrode. The ESL-structured SBTFTs with hybrid contacts show a two-order magnitude increase in saturation current (\u0000<inline-formula> <tex-math>${I}_{text {dsat}}$ </tex-math></inline-formula>\u0000) compared to SBTFTs solely based on Schottky contacts, with high intrinsic gains exceeding 1500 at a gate voltage of 10 V, and good stability under gate bias and illumination stress. Utilizing technology computer-aided design (TCAD) simulation, the operation of ESL-structured IGZO SBTFTs was fully elucidated. Also, this study conducted a thorough investigation and analysis of the influence of source-drain gaps and Schottky contact lengths at the source on \u0000<inline-formula> <tex-math>${I}_{text {dsat}}$ </tex-math></inline-formula>\u0000 and saturation voltage (\u0000<inline-formula> <tex-math>${V}_{text {dsat}}$ </tex-math></inline-formula>\u0000) for the devices. This work provides a promising route to fabricate low-cost metal oxide SBTFTs with significantly increased \u0000<inline-formula> <tex-math>${I}_{text {dsat}}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the rapid development of smart vehicles and unmanned driving, intelligent lighting control systems that can generate programmable illumination patterns are attracting great attention. In this work, an electrothermally actuated rolling shutter array is proposed to realize intelligent automobile headlights. A $2times 8$ array of electrothermal microshutters is designed and fabricated. The chip size is $26times 26times 0.5$ mm with an effective optical aperture of $20times 20$ mm. Resistive heaters on rolling shutters are designed with a new proposed method for a uniform temperature distribution. In order to improve power efficiency, polyimide (PI) filled trenches are implemented to increase thermal isolation, reducing both the operating voltage and the power consumption. Experimental results show that the opening ratio of a single microshutter pixel changes from 71% at 0 V (Open-state) to 2.6% at 2.8 V (Close-state). The open-to-close switching power efficiency is 9.1 mW/mm2, corresponding to a maximum power consumption of 3.65 W for the $2times 8$ microshutter array in Close-state. Furthermore, a mimicked traffic scene has been successfully demonstrated, where the microshutter array provides programmable illumination for a model car.
{"title":"An Electrothermally Actuated Microshutter Array With Enhanced Power Efficiency for Intelligent Lighting Control","authors":"Xinyu Ding;Wenlong Jiao;Zishan Xiong;Senlin Jiang;Yingchao Cao;Qiangxian Qi;Yue Tang;Huikai Xie","doi":"10.1109/TED.2024.3462911","DOIUrl":"https://doi.org/10.1109/TED.2024.3462911","url":null,"abstract":"With the rapid development of smart vehicles and unmanned driving, intelligent lighting control systems that can generate programmable illumination patterns are attracting great attention. In this work, an electrothermally actuated rolling shutter array is proposed to realize intelligent automobile headlights. A \u0000<inline-formula> <tex-math>$2times 8$ </tex-math></inline-formula>\u0000 array of electrothermal microshutters is designed and fabricated. The chip size is \u0000<inline-formula> <tex-math>$26times 26times 0.5$ </tex-math></inline-formula>\u0000 mm with an effective optical aperture of \u0000<inline-formula> <tex-math>$20times 20$ </tex-math></inline-formula>\u0000 mm. Resistive heaters on rolling shutters are designed with a new proposed method for a uniform temperature distribution. In order to improve power efficiency, polyimide (PI) filled trenches are implemented to increase thermal isolation, reducing both the operating voltage and the power consumption. Experimental results show that the opening ratio of a single microshutter pixel changes from 71% at 0 V (Open-state) to 2.6% at 2.8 V (Close-state). The open-to-close switching power efficiency is 9.1 mW/mm2, corresponding to a maximum power consumption of 3.65 W for the \u0000<inline-formula> <tex-math>$2times 8$ </tex-math></inline-formula>\u0000 microshutter array in Close-state. Furthermore, a mimicked traffic scene has been successfully demonstrated, where the microshutter array provides programmable illumination for a model car.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, a compact model of the dc characteristics of organic electrochemical transistors (OECTs) is proposed. Starting from the output characteristics, the transconductance in the saturation regime is modeled after the output conductance in the saturation regime is reduced to very low values. For this purpose, a previously justified integrable bell-shaped function is used, based on which the transfer characteristics in the saturation regime are determined. Since the drain current due to hopping diminishes in the linear regime, the model is based on the gradual channel approximation and constant hole mobility and gate capacitance at this regime. Six parameters are required for dc modeling, which can be obtained in a straightforward way from the transconductance and transfer characteristics in the saturation regime, and the output characteristics. A good agreement between the modeled and measured data is achieved. The proposed compact model stands out in terms of its simplicity and rapid determination of its parameters and can be easily incorporated into circuit simulators.
{"title":"A Compact DC Model for PEDOT-Based Organic Electrochemical Transistors (OECTs)","authors":"Benito González;Laia Masip;Marc Lázaro;Ramón Villarino;David Girbau;Antonio Lázaro","doi":"10.1109/TED.2024.3469170","DOIUrl":"https://doi.org/10.1109/TED.2024.3469170","url":null,"abstract":"In this article, a compact model of the dc characteristics of organic electrochemical transistors (OECTs) is proposed. Starting from the output characteristics, the transconductance in the saturation regime is modeled after the output conductance in the saturation regime is reduced to very low values. For this purpose, a previously justified integrable bell-shaped function is used, based on which the transfer characteristics in the saturation regime are determined. Since the drain current due to hopping diminishes in the linear regime, the model is based on the gradual channel approximation and constant hole mobility and gate capacitance at this regime. Six parameters are required for dc modeling, which can be obtained in a straightforward way from the transconductance and transfer characteristics in the saturation regime, and the output characteristics. A good agreement between the modeled and measured data is achieved. The proposed compact model stands out in terms of its simplicity and rapid determination of its parameters and can be easily incorporated into circuit simulators.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10706598","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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