Pub Date : 2025-10-06DOI: 10.1109/TED.2025.3613287
Ying-Jie Ma;Song Sun;Yue Huang;Shuai Zhang;Li-Ling Fu;Xin-Xin Wang;Jin-Yang Wei;Di Wu;Ai-Dong Li
Memristors are poised to drive the next wave of artificial intelligence advancements, owing to their exceptional potential for both storage and computation. However, their integration into flexible devices remains a tough challenge due to their inherent rigidity and high processing temperature, limiting their application in cutting-edge technologies such as soft robotics and wearable electronics. Motivated by human wrinkled skin, a PDMS/Au/Al2O3/HfO2/Ag stretchable memristor (C-HAP for short) fabricated via pre-stretch release and atomic layer deposition (ALD) is proposed in this study. The C-HAP memristor can withstand 10% of stretch strain and has a stable resistive switching (RS) behavior. The wrinkled structure allows stretching to be converted from the original in-plane stretching to out-of-plane localized bending, and the cushioning and stress relaxation effects of the wrinkles themselves contribute to the improvement of their mechanical properties. In addition, the C-HAP memristor can act as an artificial synapse and mimic synaptic behavior successfully under stretching. Furthermore, the triple spike time-dependent plasticity of C-HAP memristor is utilized to implement the Bienenstock–Cooper–Munro (BCM) learning rule, which enables orientation selectivity recognition in feedforward neural networks. A new methodology for designing stretchable memristors with stable storage and computational ability under dynamic conditions is provided by this research.
{"title":"Al2O3/HfO2-Based Stretchable Synaptic Memristor for Orientation Selectivity Recognition","authors":"Ying-Jie Ma;Song Sun;Yue Huang;Shuai Zhang;Li-Ling Fu;Xin-Xin Wang;Jin-Yang Wei;Di Wu;Ai-Dong Li","doi":"10.1109/TED.2025.3613287","DOIUrl":"https://doi.org/10.1109/TED.2025.3613287","url":null,"abstract":"Memristors are poised to drive the next wave of artificial intelligence advancements, owing to their exceptional potential for both storage and computation. However, their integration into flexible devices remains a tough challenge due to their inherent rigidity and high processing temperature, limiting their application in cutting-edge technologies such as soft robotics and wearable electronics. Motivated by human wrinkled skin, a PDMS/Au/Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>/Ag stretchable memristor (C-HAP for short) fabricated via pre-stretch release and atomic layer deposition (ALD) is proposed in this study. The C-HAP memristor can withstand 10% of stretch strain and has a stable resistive switching (RS) behavior. The wrinkled structure allows stretching to be converted from the original in-plane stretching to out-of-plane localized bending, and the cushioning and stress relaxation effects of the wrinkles themselves contribute to the improvement of their mechanical properties. In addition, the C-HAP memristor can act as an artificial synapse and mimic synaptic behavior successfully under stretching. Furthermore, the triple spike time-dependent plasticity of C-HAP memristor is utilized to implement the Bienenstock–Cooper–Munro (BCM) learning rule, which enables orientation selectivity recognition in feedforward neural networks. A new methodology for designing stretchable memristors with stable storage and computational ability under dynamic conditions is provided by this research.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6368-6374"},"PeriodicalIF":3.2,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-01DOI: 10.1109/TED.2025.3613286
Chunlin Liu;Xuesong Li;Ling-Xuan Qian
High-$k$ gate dielectrics have been widely studied in various transistors due to the unique properties, including but not limited to a stronger gate control capability. However, research on high-$k$ gate dielectrics in graphene field-effect transistors (GFETs) is quite limited so far, and the underlying mechanisms remain unclear. This study reports the first implementation of a binary-metal oxide of Hf1-xLaxOy as the gate dielectric in GFETs, and the effects of La incorporation into HfO2 gate dielectric were comprehensively investigated. It was found that La incorporation can effectively increase the dielectric constant, suppress the oxygen-vacancy defects, and increase the crystallization temperature of HfO2 through X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and X-ray diffraction (XRD) analyses. As a result, the electrical characteristics of GFETs can be significantly improved. In particular, the GFET with a Hf0.4La0.6Oy gate dielectric exhibits the best performance in the air within all the samples, including a small Dirac point Voltage (${V}_{text {Dirac}}text {)}$ of 4.9 V, negligible hysteresis ($Delta {V}_{text {Dirac}} =$ –0.2 V), and high hole/electron mobility of 1510/1250 cm2/V$cdot $ s, which is almost one and two orders of magnitude higher than those with pure HfO2 and SiO2 gate dielectrics under similar small gate voltages. Nevertheless, excessive La incorporation deteriorates the characteristics by generating hydroxyl defects, increasing surface roughness, and triggering recrystallization.
{"title":"Improved Performance of Graphene Field-Effect Transistors With HfO2 Gate Dielectric via La Incorporation","authors":"Chunlin Liu;Xuesong Li;Ling-Xuan Qian","doi":"10.1109/TED.2025.3613286","DOIUrl":"https://doi.org/10.1109/TED.2025.3613286","url":null,"abstract":"High-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> gate dielectrics have been widely studied in various transistors due to the unique properties, including but not limited to a stronger gate control capability. However, research on high-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> gate dielectrics in graphene field-effect transistors (GFETs) is quite limited so far, and the underlying mechanisms remain unclear. This study reports the first implementation of a binary-metal oxide of Hf<sub>1-<i>x</i></sub>La<italic><sub>x</sub></i>O<italic><sub>y</sub></i> as the gate dielectric in GFETs, and the effects of La incorporation into HfO<sub>2</sub> gate dielectric were comprehensively investigated. It was found that La incorporation can effectively increase the dielectric constant, suppress the oxygen-vacancy defects, and increase the crystallization temperature of HfO<sub>2</sub> through X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and X-ray diffraction (XRD) analyses. As a result, the electrical characteristics of GFETs can be significantly improved. In particular, the GFET with a Hf<sub>0.4</sub>La<sub>0.6</sub>O<italic><sub>y</sub></i> gate dielectric exhibits the best performance in the air within all the samples, including a small Dirac point Voltage (<inline-formula> <tex-math>${V}_{text {Dirac}}text {)}$ </tex-math></inline-formula> of 4.9 V, negligible hysteresis (<inline-formula> <tex-math>$Delta {V}_{text {Dirac}} =$ </tex-math></inline-formula> –0.2 V), and high hole/electron mobility of 1510/1250 cm<sup>2</sup>/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, which is almost one and two orders of magnitude higher than those with pure HfO<sub>2</sub> and SiO<sub>2</sub> gate dielectrics under similar small gate voltages. Nevertheless, excessive La incorporation deteriorates the characteristics by generating hydroxyl defects, increasing surface roughness, and triggering recrystallization.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6349-6354"},"PeriodicalIF":3.2,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study thoroughly investigates the on-current ($text {I}_{text {on}}text {)}$ and nonconductive stress (NCS) reliability of the contact field plate lateral double-diffused metal–oxide–semiconductor (CFP LDMOS) with bipolar–CMOS–DMOS (BCD) technology using different fluorine (F) implantation methodologies. Two devices with different oxide cap thicknesses during annealing after F implantation are compared to a standard (STD) device without F implantation. The thin oxide cap device demonstrates the poor Si quality and defect generation after annealing, resulting in decreased $text {I}_{text {on}}$ as the F-imp dose increases. In contrast, the F treatment can effectively passivate defects in the thick oxide cap device, leading to improved $text {I}_{text {on}}$ and NCS reliability. Finally, physical mechanisms based on defect analysis, scanning electron microscope (SEM) images, and secondary ion mass spectrometer (SIMS) profiles are proposed to clarify the phenomena.
{"title":"Analysis of Fluorine Implantation With Different Oxide Cap Thicknesses During Annealing in Contact Field Plate Lateral Double-Diffused MOS With 0.13-μm Bipolar–CMOS–DMOS Technology","authors":"Yu-Fa Tu;Ting-Chang Chang;Wei-Chieh Hung;Hung-Ming Kuo;Ya-Huan Lee;Yu-Hsiang Tsai","doi":"10.1109/TED.2025.3609743","DOIUrl":"https://doi.org/10.1109/TED.2025.3609743","url":null,"abstract":"This study thoroughly investigates the <sc>on</small>-current (<inline-formula> <tex-math>$text {I}_{text {on}}text {)}$ </tex-math></inline-formula> and nonconductive stress (NCS) reliability of the contact field plate lateral double-diffused metal–oxide–semiconductor (CFP LDMOS) with bipolar–CMOS–DMOS (BCD) technology using different fluorine (F) implantation methodologies. Two devices with different oxide cap thicknesses during annealing after F implantation are compared to a standard (STD) device without F implantation. The thin oxide cap device demonstrates the poor Si quality and defect generation after annealing, resulting in decreased <inline-formula> <tex-math>$text {I}_{text {on}}$ </tex-math></inline-formula> as the F-imp dose increases. In contrast, the F treatment can effectively passivate defects in the thick oxide cap device, leading to improved <inline-formula> <tex-math>$text {I}_{text {on}}$ </tex-math></inline-formula> and NCS reliability. Finally, physical mechanisms based on defect analysis, scanning electron microscope (SEM) images, and secondary ion mass spectrometer (SIMS) profiles are proposed to clarify the phenomena.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6383-6386"},"PeriodicalIF":3.2,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-29DOI: 10.1109/TED.2025.3611907
Andreu L. Glasmann;Wendy L. Sarney;Christine K. McGinn;Christina A. Hacker;Sina Najmaei
In this article, we present a simulation methodology for studying device-to-device variability in submicrometer planar hafnia-based ferroelectric field-effect transistors (FeFETs) with silicon channels. The simulation methodology is based on thin films of hafnium zirconium oxide (HZO) fabricated under CMOS-compatible conditions, which were characterized using piezoresponse force microscopy (PFM). The PFM images were analyzed using a combination of unsupervised learning with Gaussian mixture models (GMMs) and electrical measurements of polarization-field characteristics of metal–ferroelectric–metal capacitors. The results were directly integrated into an extensive Monte Carlo study based on 2-D device simulations of short-channel front-end FeFETs, where we simulate high- and low-threshold voltage states for 100 total device configurations. From this framework, we quantify how the granular and multiphase nature of ferroelectric HZO contribute to the transport within the semiconductor channel. The results indicate that threshold voltages for both high- and low-threshold states and the subthreshold swings can vary up to about 400 mV and 20 mV/dec, respectively.
{"title":"Analysis of Short-Channel Hafnia-Based FeFET Device Variability Guided by Piezoresponse Force Microscopy","authors":"Andreu L. Glasmann;Wendy L. Sarney;Christine K. McGinn;Christina A. Hacker;Sina Najmaei","doi":"10.1109/TED.2025.3611907","DOIUrl":"https://doi.org/10.1109/TED.2025.3611907","url":null,"abstract":"In this article, we present a simulation methodology for studying device-to-device variability in submicrometer planar hafnia-based ferroelectric field-effect transistors (FeFETs) with silicon channels. The simulation methodology is based on thin films of hafnium zirconium oxide (HZO) fabricated under CMOS-compatible conditions, which were characterized using piezoresponse force microscopy (PFM). The PFM images were analyzed using a combination of unsupervised learning with Gaussian mixture models (GMMs) and electrical measurements of polarization-field characteristics of metal–ferroelectric–metal capacitors. The results were directly integrated into an extensive Monte Carlo study based on 2-D device simulations of short-channel front-end FeFETs, where we simulate high- and low-threshold voltage states for 100 total device configurations. From this framework, we quantify how the granular and multiphase nature of ferroelectric HZO contribute to the transport within the semiconductor channel. The results indicate that threshold voltages for both high- and low-threshold states and the subthreshold swings can vary up to about 400 mV and 20 mV/dec, respectively.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6361-6367"},"PeriodicalIF":3.2,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-29DOI: 10.1109/TED.2025.3608778
Jimyoung Lee;Seung Kyu Kim;Kwang Young Lee;Jongwook Jeon
The complementary field-effect transistors (CFETs) are promising for next-generation logic devices, but tall vias (TVs) face challenges, including high resistance, parasitic capacitance, and metal void defects. This study evaluates three source-side to backside power delivery network (BSPDN) interconnect structures: conventional TV, line-type TV (LTV), and frontside connection (FSC). FSC utilizes frontside metal lines with power tap cells (PTCs) for front-to-back connectivity, offering a scalable solution. Through 3D-TCAD simulations, we analyze their cell-level and area-adjusted performance. FSC achieves a + 2.2% higher frequency at the same power (Freq. at $P$ ) and a −4.7% lower power at the same frequency (Power at F) compared to TV, while maintaining consistent performance across cell height (CH) scaling. In contrast, TV and LTV exhibit degradation due to increased resistance and capacitance at reduced CH. FSC’s sweet zone (12–71 CPPs) ensures sufficient margin for PTC insertion, delivering a 1.7% Freq. at $P$ gain at 31 CPPs and 12% area reduction at zero frequency offset. Notably, FSC’s compatibility with nonvertical via profiles (essential for void prevention) further enhances its advantages in real processes. These results demonstrate FSC’s superior power, performance, and area (PPA) characteristics, positioning it as a robust alternative to TV/LTV for CFET architectures. The study provides critical insights for advancing the next-generation logic devices.
{"title":"Area-Adjusted Comparison of BSPDN Interconnects in CFET: Superiority of Frontside Connection","authors":"Jimyoung Lee;Seung Kyu Kim;Kwang Young Lee;Jongwook Jeon","doi":"10.1109/TED.2025.3608778","DOIUrl":"https://doi.org/10.1109/TED.2025.3608778","url":null,"abstract":"The complementary field-effect transistors (CFETs) are promising for next-generation logic devices, but tall vias (TVs) face challenges, including high resistance, parasitic capacitance, and metal void defects. This study evaluates three source-side to backside power delivery network (BSPDN) interconnect structures: conventional TV, line-type TV (LTV), and frontside connection (FSC). FSC utilizes frontside metal lines with power tap cells (PTCs) for front-to-back connectivity, offering a scalable solution. Through 3D-TCAD simulations, we analyze their cell-level and area-adjusted performance. FSC achieves a + 2.2% higher frequency at the same power (Freq. at <inline-formula> <tex-math>$P$ </tex-math></inline-formula>) and a −4.7% lower power at the same frequency (Power at F) compared to TV, while maintaining consistent performance across cell height (CH) scaling. In contrast, TV and LTV exhibit degradation due to increased resistance and capacitance at reduced CH. FSC’s sweet zone (12–71 CPPs) ensures sufficient margin for PTC insertion, delivering a 1.7% Freq. at <inline-formula> <tex-math>$P$ </tex-math></inline-formula> gain at 31 CPPs and 12% area reduction at zero frequency offset. Notably, FSC’s compatibility with nonvertical via profiles (essential for void prevention) further enhances its advantages in real processes. These results demonstrate FSC’s superior power, performance, and area (PPA) characteristics, positioning it as a robust alternative to TV/LTV for CFET architectures. The study provides critical insights for advancing the next-generation logic devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6329-6335"},"PeriodicalIF":3.2,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-26DOI: 10.1109/TED.2025.3612316
Muhammad Asghar Khan;Yelim Kang;Muhammad Farooq Khan;Shania Rehman;Min Jong Lee;Sang Heon Lee;Seunghyun Oh;Tae Hyuk Kim;Seon Joong Kim;Hyungju Ahn;Jae Won Shim
Organic semiconductors exhibit significant potential for application in artificial neuromorphic computing because of their unique electrical and optoelectronic properties. In this study, we explore the potential of the nonfullerene Y6 (also known as BTP-4F) organic semiconductor material in optoelectronic neuromorphic computing, image recognition, reservoir computing (RC), and wireless encrypted communication. The organic field-effect transistor (OFET) constructed using the Y6 polymer exhibits n-type semiconductor behavior with a current on–off ($I_{mathrm{ON}} / I_{mathrm{OFF}}$ ) ratio of approximately $10^{{2}}$ as well as excellent synaptic functionalities under ultraviolet (UV) light. The synaptic plasticity of OFET is demonstrated to be optically controllable using incident light of 220-nm wavelength. Notably, the transition from short-term memory (STM) to long-term memory (LTM) could be modulated by manipulating pulse time, pulse number, and pulse interval. Furthermore, image recognition on the Modified National Institute of Standards and Technology (MNIST) dataset using the fabricated device in conjunction with a convolutional neural network (CNN) is observed to yield an excellent accuracy of 93.4%. Moreover, we demonstrate the application of Y6 OFET in a 4-bit RC for digit classification. Finally, optically encrypted communication is also achieved based on the international Morse code. These findings demonstrate the potential of Y6-based OFETs in neuromorphic computing, RC, and encrypted communication, paving the way for innovations in brain-inspired computing and artificial intelligence (AI) hardware.
{"title":"Ultraviolet Light-Driven Artificial Neuromorphic Properties in Organic Transistors for Reservoir Computing and Encrypted Communication","authors":"Muhammad Asghar Khan;Yelim Kang;Muhammad Farooq Khan;Shania Rehman;Min Jong Lee;Sang Heon Lee;Seunghyun Oh;Tae Hyuk Kim;Seon Joong Kim;Hyungju Ahn;Jae Won Shim","doi":"10.1109/TED.2025.3612316","DOIUrl":"https://doi.org/10.1109/TED.2025.3612316","url":null,"abstract":"Organic semiconductors exhibit significant potential for application in artificial neuromorphic computing because of their unique electrical and optoelectronic properties. In this study, we explore the potential of the nonfullerene Y6 (also known as BTP-4F) organic semiconductor material in optoelectronic neuromorphic computing, image recognition, reservoir computing (RC), and wireless encrypted communication. The organic field-effect transistor (OFET) constructed using the Y6 polymer exhibits n-type semiconductor behavior with a current <sc>on</small>–<sc>off</small> (<inline-formula> <tex-math>$I_{mathrm{ON}} / I_{mathrm{OFF}}$ </tex-math></inline-formula>) ratio of approximately <inline-formula> <tex-math>$10^{{2}}$ </tex-math></inline-formula> as well as excellent synaptic functionalities under ultraviolet (UV) light. The synaptic plasticity of OFET is demonstrated to be optically controllable using incident light of 220-nm wavelength. Notably, the transition from short-term memory (STM) to long-term memory (LTM) could be modulated by manipulating pulse time, pulse number, and pulse interval. Furthermore, image recognition on the Modified National Institute of Standards and Technology (MNIST) dataset using the fabricated device in conjunction with a convolutional neural network (CNN) is observed to yield an excellent accuracy of 93.4%. Moreover, we demonstrate the application of Y6 OFET in a 4-bit RC for digit classification. Finally, optically encrypted communication is also achieved based on the international Morse code. These findings demonstrate the potential of Y6-based OFETs in neuromorphic computing, RC, and encrypted communication, paving the way for innovations in brain-inspired computing and artificial intelligence (AI) hardware.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6341-6348"},"PeriodicalIF":3.2,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/TED.2025.3608842
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/TED.2025.3608842","DOIUrl":"https://doi.org/10.1109/TED.2025.3608842","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 10","pages":"5774-5775"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11176793","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145121311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/TED.2025.3608844
{"title":"IEEE Transactions on Electron Devices Information for Authors","authors":"","doi":"10.1109/TED.2025.3608844","DOIUrl":"https://doi.org/10.1109/TED.2025.3608844","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 10","pages":"C3-C3"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11176796","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145121312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gate oxide scaling is essential for enhancing the performance of amorphous oxide semiconductor (AOS) field-effect transistors, yet it remains limited by charge trapping and interface quality. In this work, we demonstrate tungsten-doped In2O3 indium–tungsten oxide (IWO) MOSFETs incorporating an amorphous HfO2/ZrO2/HfO2 (HZH) trilayer gate dielectric that achieves an equivalent oxide thickness (EOT) as low as $3~unicode{0x00C5}$ . The transistors exhibit near-ideal subthreshold swing (SS) (75 mV/decade), high on-state current ($gt 240~{mu }$ A/$mu $ m), and suppressed gate leakage even at this extreme limit of EOT scaling. Positive bias-stress (PBS) tests reveal improved reliability in HZH compared with conventional HfO2, with minimal threshold voltage shift. Through density-gradient-based numerical modeling and analytical stress-recovery simulations, we show that these improvements originate from spatial and energetic redistribution of oxygen vacancy induced traps into the ZrO2-rich region, away from the channel interface. The consequent reduction in the density of acceptor-like subgap states collectively improves carrier mobility and mitigates trap-limited conduction (TLC). These results highlight the potential of targeted gate-stack engineering in extending conventional EOT scaling benefits to AOS transistors.
{"title":"Extreme EOT Scaling in Tungsten-Doped In2O3 MOSFETs for Enhanced Stability and Drive Current","authors":"Hyeonwoo Park;Sharadindu Gopal Kirtania;Eknath Sarkar;Dyutimoy Chakraborty;Chengyang Zhang;Hyun Jae Lee;Jaewon Shin;Shimeng Yu;Asif Khan;H. Kim;C. Im;M. J. Hong;Daewon Ha;Suman Datta","doi":"10.1109/TED.2025.3612345","DOIUrl":"https://doi.org/10.1109/TED.2025.3612345","url":null,"abstract":"Gate oxide scaling is essential for enhancing the performance of amorphous oxide semiconductor (AOS) field-effect transistors, yet it remains limited by charge trapping and interface quality. In this work, we demonstrate tungsten-doped In<sub>2</sub>O<sub>3</sub> indium–tungsten oxide (IWO) MOSFETs incorporating an amorphous HfO<sub>2</sub>/ZrO<sub>2</sub>/HfO<sub>2</sub> (HZH) trilayer gate dielectric that achieves an equivalent oxide thickness (EOT) as low as <inline-formula> <tex-math>$3~unicode{0x00C5}$ </tex-math></inline-formula>. The transistors exhibit near-ideal subthreshold swing (SS) (75 mV/decade), high <sc>on</small>-state current (<inline-formula> <tex-math>$gt 240~{mu }$ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m), and suppressed gate leakage even at this extreme limit of EOT scaling. Positive bias-stress (PBS) tests reveal improved reliability in HZH compared with conventional HfO<sub>2</sub>, with minimal threshold voltage shift. Through density-gradient-based numerical modeling and analytical stress-recovery simulations, we show that these improvements originate from spatial and energetic redistribution of oxygen vacancy induced traps into the ZrO<sub>2</sub>-rich region, away from the channel interface. The consequent reduction in the density of acceptor-like subgap states collectively improves carrier mobility and mitigates trap-limited conduction (TLC). These results highlight the potential of targeted gate-stack engineering in extending conventional EOT scaling benefits to AOS transistors.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7136-7144"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/TED.2025.3609307
Xiaolei Zhang;Jiahao Lin;Chuandu Zhang;Wei Xu
The accurate monitoring of low-range pressure variations is crucial in many biomedical and wearable sensing applications, where abnormal pressure levels can indicate potential health risks. This brief presents a passive wireless inductor–capacitor (LC) pressure sensor, developed using MEMS and flexible printed circuit board (FPCB) technologies for low-range pressure monitoring. The sensor comprises a 16.2-$mu $ m-thick MEMS layer with a 2-mm circular electrode, a bottom electrode with an integrated spiral inductor on the FPCB, and a 50-$mu $ m laser-cut polyimide (PI) intermediate layer forming the capacitive structure. Simulations and experimental evaluations in a controlled low-pressure water environment confirmed stable performance and close agreement between theoretical and measured responses over the 100–5000-Pa range. By accounting for parasitic capacitance effects from water environments and interlayer interactions, the sensor still achieves a high average sensitivity of 5.15 MHz/kPa, a fine resolution of 25 Pa, and a low-temperature coefficient of frequency (TCF) of 173 ppm/°C. With its compact, flexible, and wireless design, the proposed sensor holds strong potential for continuous physiological pressure monitoring.
{"title":"A Compact Wireless Passive Pressure Sensor With High Sensitivity and Resolution Based on MEMS–FPCB Integration","authors":"Xiaolei Zhang;Jiahao Lin;Chuandu Zhang;Wei Xu","doi":"10.1109/TED.2025.3609307","DOIUrl":"https://doi.org/10.1109/TED.2025.3609307","url":null,"abstract":"The accurate monitoring of low-range pressure variations is crucial in many biomedical and wearable sensing applications, where abnormal pressure levels can indicate potential health risks. This brief presents a passive wireless inductor–capacitor (<italic>LC</i>) pressure sensor, developed using MEMS and flexible printed circuit board (FPCB) technologies for low-range pressure monitoring. The sensor comprises a 16.2-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick MEMS layer with a 2-mm circular electrode, a bottom electrode with an integrated spiral inductor on the FPCB, and a 50-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m laser-cut polyimide (PI) intermediate layer forming the capacitive structure. Simulations and experimental evaluations in a controlled low-pressure water environment confirmed stable performance and close agreement between theoretical and measured responses over the 100–5000-Pa range. By accounting for parasitic capacitance effects from water environments and interlayer interactions, the sensor still achieves a high average sensitivity of 5.15 MHz/kPa, a fine resolution of 25 Pa, and a low-temperature coefficient of frequency (TCF) of 173 ppm/°C. With its compact, flexible, and wireless design, the proposed sensor holds strong potential for continuous physiological pressure monitoring.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6391-6395"},"PeriodicalIF":3.2,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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