Pub Date : 2025-12-30DOI: 10.1109/TED.2025.3646145
Minjae Jeong;Min Seong Kim;Ki Taeg Shin;Wongyun Youn;Hoon Jeong;Hyun Jae Kim
A structural improvement is introduced to the direct current (dc)-type scan driver to address the electrical limitations and long-term bias stress characteristics of oxide thin-film transistors (TFTs). This modification improves output falling speed and reliability. In conventional oxide TFT-based scan drivers, prolonged positive gate bias can cause threshold voltage shifts. By functionally separating the pull-down (PD) and low-level holding (LLH) paths in the conventional dc-type scan driver, the proposed circuit enhances driving capability and reduces the stress duty cycle under continuous positive bias from over 99% to below 1%. The experimental measurements confirm that the falling time is reduced from 2.1 to 1.4 μs. Furthermore, the SmartSPICE simulations incorporating threshold voltage shifts predict that after one year of operation, the falling time of a conventional scan driver increases to 9.9 μs, whereas the proposed driver shows a modest increase to 1.9 μs.
{"title":"Highly Reliable Oxide TFT-Based DC-Type Scan Driver With Separated Pull-Down and Holding Functions in Displays","authors":"Minjae Jeong;Min Seong Kim;Ki Taeg Shin;Wongyun Youn;Hoon Jeong;Hyun Jae Kim","doi":"10.1109/TED.2025.3646145","DOIUrl":"https://doi.org/10.1109/TED.2025.3646145","url":null,"abstract":"A structural improvement is introduced to the direct current (dc)-type scan driver to address the electrical limitations and long-term bias stress characteristics of oxide thin-film transistors (TFTs). This modification improves output falling speed and reliability. In conventional oxide TFT-based scan drivers, prolonged positive gate bias can cause threshold voltage shifts. By functionally separating the pull-down (PD) and low-level holding (LLH) paths in the conventional dc-type scan driver, the proposed circuit enhances driving capability and reduces the stress duty cycle under continuous positive bias from over 99% to below 1%. The experimental measurements confirm that the falling time is reduced from 2.1 to 1.4 μs. Furthermore, the SmartSPICE simulations incorporating threshold voltage shifts predict that after one year of operation, the falling time of a conventional scan driver increases to 9.9 μs, whereas the proposed driver shows a modest increase to 1.9 μs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 2","pages":"1074-1078"},"PeriodicalIF":3.2,"publicationDate":"2025-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a system for high-efficiency S-band magnetron microwave power combining based on the mutual synchronization mechanism (peer-to-peer locking mechanism) between magnetrons, which effectively addresses the issues of low efficiency and complex architecture in the existing magnetron microwave combining systems. The system is simplified through a modification of the H–T waveguide tee by introducing multiple tuning pins to control the coupling coefficient precisely. This modification achieves tunable coupling strength and mutual frequency pulling and locking. It leverages the intrinsic coupling characteristics of microwave signals between magnetrons and ensures stable interlocking. Moreover, it significantly simplifies the combining system and eliminates the need for circulators or phase shifters. Additionally, a fixed-length (or tunable) straight waveguide is added to fine-tune the phase difference between the two magnetrons, thereby maximizing the combining efficiency to approximately 99% in experiments. The high combining efficiency is maintained once the combining system is established. The combining efficiency remains above 95% even when different magnetrons are alternated. These results highlight its potential as a high-efficiency solution for magnetron microwave combining applications and industrial-scale use.
{"title":"A High-Efficiency Microwave Power Combining System Based on a Tuned H–T Waveguide Tee","authors":"Dayang Wang;Jianlong Liu;Kongyi Hu;Zhijianmucuo Dong;Zheng Yang;Feifan Ma;Zhong Wang;Baoqing Zeng","doi":"10.1109/TED.2025.3643405","DOIUrl":"https://doi.org/10.1109/TED.2025.3643405","url":null,"abstract":"This brief presents a system for high-efficiency S-band magnetron microwave power combining based on the mutual synchronization mechanism (peer-to-peer locking mechanism) between magnetrons, which effectively addresses the issues of low efficiency and complex architecture in the existing magnetron microwave combining systems. The system is simplified through a modification of the H–T waveguide tee by introducing multiple tuning pins to control the coupling coefficient precisely. This modification achieves tunable coupling strength and mutual frequency pulling and locking. It leverages the intrinsic coupling characteristics of microwave signals between magnetrons and ensures stable interlocking. Moreover, it significantly simplifies the combining system and eliminates the need for circulators or phase shifters. Additionally, a fixed-length (or tunable) straight waveguide is added to fine-tune the phase difference between the two magnetrons, thereby maximizing the combining efficiency to approximately 99% in experiments. The high combining efficiency is maintained once the combining system is established. The combining efficiency remains above 95% even when different magnetrons are alternated. These results highlight its potential as a high-efficiency solution for magnetron microwave combining applications and industrial-scale use.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 2","pages":"1079-1082"},"PeriodicalIF":3.2,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-11DOI: 10.1109/TED.2025.3637350
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/TED.2025.3637350","DOIUrl":"https://doi.org/10.1109/TED.2025.3637350","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7192-7193"},"PeriodicalIF":3.2,"publicationDate":"2025-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11298382","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-11DOI: 10.1109/TED.2025.3637352
{"title":"IEEE Transactions on Electron Devices Information for Authors","authors":"","doi":"10.1109/TED.2025.3637352","DOIUrl":"https://doi.org/10.1109/TED.2025.3637352","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"C3-C3"},"PeriodicalIF":3.2,"publicationDate":"2025-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11298381","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1109/TED.2025.3630613
Alberto Ferraris;Eunjung Cha;Antonis Olziersky;Marilyne Sousa;Hung-Chi Han;Edoardo Charbon;Kirsten Moselund;Cezar Zota
This work investigates the impact of size scaling on the performance of cryogenic InxGa1_xAs/InP high electron mobility transistors (HEMTs) for low-noise and high-frequency applications. Two quantum-well heterostructures, with 75% and 80% indium content, are examined from 300 to 4 K, including devices with gate lengths down to 40 nm and gate widths down to 380 nm. At cryogenic temperatures, the 80% indium channel achieves a record combination of high-frequency metrics ${textit{f}}_{textit{T}} ={text{622}}$ GHz, ${textit{f}}_{text {MAX}} ={text{733}}$ GHz, and low-noise indication factor $({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {text{0}}.{text{17}}~({text{V}}cdot text {mm}/text {S})^{textsf{1/2}}$ on the same device. This performance is enabled by heterostructure engineering, resulting in ultralow ${textit{R}}_{text {ON}} = ~Omega cdot $ $mu $ m. The 75% indium heterostructure instead demonstrates superior low-noise operation, with a minimum subthreshold swing SS = 8.5 mV/decade and a noise indication factor as low as $({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {textsf{0.15}}~({text{V}}cdot text {mm}/text {S})^{1/2}$ at optimal device dimensions. These results highlight the potential of InGaAs/InP HEMTs in cryogenic low-noise amplifiers (LNAs), for qubit readout in future high-density quantum computing architectures.
这项工作研究了尺寸缩放对低温InxGa1＿xAs/InP高电子迁移率晶体管（hemt）性能的影响，用于低噪声和高频应用。两个量子阱异质结构，有75% and 80% indium content, are examined from 300 to 4 K, including devices with gate lengths down to 40 nm and gate widths down to 380 nm. At cryogenic temperatures, the 80% indium channel achieves a record combination of high-frequency metrics ${textit{f}}_{textit{T}} ={text{622}}$ GHz, ${textit{f}}_{text {MAX}} ={text{733}}$ GHz, and low-noise indication factor $({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {text{0}}.{text{17}}~({text{V}}cdot text {mm}/text {S})^{textsf{1/2}}$ on the same device. This performance is enabled by heterostructure engineering, resulting in ultralow ${textit{R}}_{text {ON}} = ~Omega cdot $ $mu $ m. The 75% indium heterostructure instead demonstrates superior low-noise operation, with a minimum subthreshold swing SS = 8.5 mV/decade and a noise indication factor as low as $({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {textsf{0.15}}~({text{V}}cdot text {mm}/text {S})^{1/2}$ at optimal device dimensions. These results highlight the potential of InGaAs/InP HEMTs in cryogenic low-noise amplifiers (LNAs), for qubit readout in future high-density quantum computing architectures.
{"title":"Impact of Size Scaling in Cryogenic InGaAs/InP HEMTs for Low-Noise and High-Frequency Performance","authors":"Alberto Ferraris;Eunjung Cha;Antonis Olziersky;Marilyne Sousa;Hung-Chi Han;Edoardo Charbon;Kirsten Moselund;Cezar Zota","doi":"10.1109/TED.2025.3630613","DOIUrl":"https://doi.org/10.1109/TED.2025.3630613","url":null,"abstract":"This work investigates the impact of size scaling on the performance of cryogenic In<italic><sub>x</sub></i>Ga<sub>1</sub>_<sub>x</sub>As/InP high electron mobility transistors (HEMTs) for low-noise and high-frequency applications. Two quantum-well heterostructures, with 75% and 80% indium content, are examined from 300 to 4 K, including devices with gate lengths down to 40 nm and gate widths down to 380 nm. At cryogenic temperatures, the 80% indium channel achieves a record combination of high-frequency metrics <inline-formula> <tex-math>${textit{f}}_{textit{T}} ={text{622}}$ </tex-math></inline-formula> GHz, <inline-formula> <tex-math>${textit{f}}_{text {MAX}} ={text{733}}$ </tex-math></inline-formula> GHz, and low-noise indication factor <inline-formula> <tex-math>$({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {text{0}}.{text{17}}~({text{V}}cdot text {mm}/text {S})^{textsf{1/2}}$ </tex-math></inline-formula> on the same device. This performance is enabled by heterostructure engineering, resulting in ultralow <inline-formula> <tex-math>${textit{R}}_{text {ON}} = ~Omega cdot $ </tex-math></inline-formula><inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m. The 75% indium heterostructure instead demonstrates superior low-noise operation, with a minimum subthreshold swing SS = 8.5 mV/decade and a noise indication factor as low as <inline-formula> <tex-math>$({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {textsf{0.15}}~({text{V}}cdot text {mm}/text {S})^{1/2}$ </tex-math></inline-formula> at optimal device dimensions. These results highlight the potential of InGaAs/InP HEMTs in cryogenic low-noise amplifiers (LNAs), for qubit readout in future high-density quantum computing architectures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7175-7181"},"PeriodicalIF":3.2,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-24DOI: 10.1109/TED.2025.3627189
D. K. Nguyen;A. Pilotto;D. Lizzit;M. Pala;P. Dollfus;D. Esseni
This article investigates the operation and design of Dirac-source FETs (DSFETs), by using ab initio transport simulations based on the NEGF formalism, which seems appropriate given the novelty of the physics and of the device architecture introduced by DSFETs. In particular, we first discuss the limitations in terms of drive current of DSFETs based on a graphene-MoS2 van der Waals heterojunction. Then, we propose a novel p-type DSFET based on hydrogenated graphene (HGr). Our simulation results suggest that the HGr-DSFET has a robust sub-60 mV/dec operation and an ${textsc{on}}$ -current between $text{2}times $ and $text{4}times $ larger than the graphene-MoS2 DSFET counterpart. Our study investigates the influence on the device operation of several material and design parameters, using either ballistic simulations or simulations accounting for electron–phonon scattering.
{"title":"Operation and Design of Dirac-Source FETs Using Ab Initio Transport Simulations: Subthreshold Swing and Drive Current","authors":"D. K. Nguyen;A. Pilotto;D. Lizzit;M. Pala;P. Dollfus;D. Esseni","doi":"10.1109/TED.2025.3627189","DOIUrl":"https://doi.org/10.1109/TED.2025.3627189","url":null,"abstract":"This article investigates the operation and design of Dirac-source FETs (DSFETs), by using ab initio transport simulations based on the NEGF formalism, which seems appropriate given the novelty of the physics and of the device architecture introduced by DSFETs. In particular, we first discuss the limitations in terms of drive current of DSFETs based on a graphene-MoS<sub>2</sub> van der Waals heterojunction. Then, we propose a novel p-type DSFET based on hydrogenated graphene (HGr). Our simulation results suggest that the HGr-DSFET has a robust sub-60 mV/dec operation and an <inline-formula> <tex-math>${textsc{on}}$ </tex-math></inline-formula>-current between <inline-formula> <tex-math>$text{2}times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$text{4}times $ </tex-math></inline-formula> larger than the graphene-MoS<sub>2</sub> DSFET counterpart. Our study investigates the influence on the device operation of several material and design parameters, using either ballistic simulations or simulations accounting for electron–phonon scattering.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7114-7121"},"PeriodicalIF":3.2,"publicationDate":"2025-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-20DOI: 10.1109/TED.2025.3629592
Yong-Ci Zhang;Kai-Chun Chang;Po-Hsun Chen;Ting-Chang Chang;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Hung-Ming Kuo
This research presents a new method for detecting GaN buffer traps in GaN high electron mobility transistors with p-type gates (p-GaN HEMTs). It is demonstrated that the hysteresis window during the transfer curve sweeping can be used to analyze the GaN buffer quality. The hysteresis behavior of p-GaN HEMTs is experimentally investigated in this research. Transfer curve sweeping with the varied $textit{V}_{text {g}}$ range and gate bias stress is tested on the device to clarify the physical model of the hysteresis window in p-GaN HEMTs. A hysteresis behavioral model in p-GaN HEMTs can correlate the hysteresis window with the buffer quality, providing an effective technique for the instantaneous detection of GaN buffer quality. The method is also verified by a dynamic $textit{R}_{text {on}}$ test on two devices with different buffer processes. The dynamic $textit{R}_{text {on}}$ degradation has a good correlation with the hysteresis window, which indicates that this new method is effective for detecting p-GaN HEMT buffer quality. The method proposed in this study has the potential to accelerate the detection of buffer traps in p-GaN HEMT devices. Through the technology developed in this research, we can identify and address these defects more quickly, and it is expected to achieve better performance for p-GaN HEMT in the field of high-power components.
{"title":"A Method to Detect Buffer Traps by the Hysteresis Window of p-GaN HEMTs","authors":"Yong-Ci Zhang;Kai-Chun Chang;Po-Hsun Chen;Ting-Chang Chang;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Hung-Ming Kuo","doi":"10.1109/TED.2025.3629592","DOIUrl":"https://doi.org/10.1109/TED.2025.3629592","url":null,"abstract":"This research presents a new method for detecting GaN buffer traps in GaN high electron mobility transistors with p-type gates (p-GaN HEMTs). It is demonstrated that the hysteresis window during the transfer curve sweeping can be used to analyze the GaN buffer quality. The hysteresis behavior of p-GaN HEMTs is experimentally investigated in this research. Transfer curve sweeping with the varied <inline-formula> <tex-math>$textit{V}_{text {g}}$ </tex-math></inline-formula> range and gate bias stress is tested on the device to clarify the physical model of the hysteresis window in p-GaN HEMTs. A hysteresis behavioral model in p-GaN HEMTs can correlate the hysteresis window with the buffer quality, providing an effective technique for the instantaneous detection of GaN buffer quality. The method is also verified by a dynamic <inline-formula> <tex-math>$textit{R}_{text {on}}$ </tex-math></inline-formula> test on two devices with different buffer processes. The dynamic <inline-formula> <tex-math>$textit{R}_{text {on}}$ </tex-math></inline-formula> degradation has a good correlation with the hysteresis window, which indicates that this new method is effective for detecting p-GaN HEMT buffer quality. The method proposed in this study has the potential to accelerate the detection of buffer traps in p-GaN HEMT devices. Through the technology developed in this research, we can identify and address these defects more quickly, and it is expected to achieve better performance for p-GaN HEMT in the field of high-power components.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7186-7189"},"PeriodicalIF":3.2,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1109/TED.2025.3628365
Yi Gu;Wendi Wei;Kun Chen;Chen Wang;Qingqing Sun;David Wei Zhang
A universal model for drain-induced barrier lowering (DIBL) that accounts for time-dependent hot carrier degradation (HCD) in fin field-effect transistor (FinFET) has been presented. The model demonstrates agreement with experimental data from advanced 14-nm ultralow threshold voltage (ULVT) FinFET devices, accurately predicting DIBL degradation under HCD stress, where DIBL values become independent of $textit{V}_{text {ds}}$ during stress. The forward and reverse measurements are employed to analyze DIBL degradation and the associated evolution of lateral interface traps. Additionally, integrating the model into circuit-level analyses, such as those for inverter and SRAM, effectively reduces the risk of overestimating device performance. This comprehensive evaluation highlights the critical importance of precise DIBL modeling for ensuring circuit reliability in modern ultralow-power (ULP) system-on chip (SoC) designs.
{"title":"Universal Time-Dependent DIBL Model for HCD-Degraded FinFETs","authors":"Yi Gu;Wendi Wei;Kun Chen;Chen Wang;Qingqing Sun;David Wei Zhang","doi":"10.1109/TED.2025.3628365","DOIUrl":"https://doi.org/10.1109/TED.2025.3628365","url":null,"abstract":"A universal model for drain-induced barrier lowering (DIBL) that accounts for time-dependent hot carrier degradation (HCD) in fin field-effect transistor (FinFET) has been presented. The model demonstrates agreement with experimental data from advanced 14-nm ultralow threshold voltage (ULVT) FinFET devices, accurately predicting DIBL degradation under HCD stress, where DIBL values become independent of <inline-formula> <tex-math>$textit{V}_{text {ds}}$ </tex-math></inline-formula> during stress. The forward and reverse measurements are employed to analyze DIBL degradation and the associated evolution of lateral interface traps. Additionally, integrating the model into circuit-level analyses, such as those for inverter and SRAM, effectively reduces the risk of overestimating device performance. This comprehensive evaluation highlights the critical importance of precise DIBL modeling for ensuring circuit reliability in modern ultralow-power (ULP) system-on chip (SoC) designs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7182-7185"},"PeriodicalIF":3.2,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-13DOI: 10.1109/TED.2025.3629599
Yuan-Chun Su;Shu-Jui Chang;D. Mahaveer Sathaiya;Chen-Feng Hsu;Bo-Heng Liu;Chien-Ying Su;Chi-Chung Kei;Yen-Fa Liao;Shu-Chih Haw;Chih-Wei Hu;San-Lin Liew;Vincent Duen-Huei Hou;T.-Y. Lee;Chao-Ching Cheng;Tsung-En Lee;Iuliana P. Radu
To address the challenge of directly nucleating dielectrics on a dangling bond-free surface, we present an optimized atomic layer deposition (ALD) process to achieve uniform AlOx and HfOx dielectric layers on a monolayer MoS2 nanosheet within a gate-all-around (GAA) architecture. By introducing a trimethylaluminum (TMA) precursor soaking step in the ALD cycles, a thin and dense AlOx interfacial layer (IL) can be formed on the MoS2 surface. Depositing the AlOx IL at 90$~^{circ }$ C and the subsequent HfOx high-$kappa $ layer at 200$~^{circ }$ C minimizes defect formations and preserves the MoS2 channel’s integrity. A postdeposition anneal at 400$~^{circ }$ C further improves device performance, achieving an ON/OFF ratio of 108 and a improved subthreshold swing (SS). These improvements are attributed to a reduction of Al–OH bonds in the AlOx layer, which lowers the interface trap density and enhances carrier mobility. This study demonstrates the feasibility of integrating high-quality ALD gate dielectrics with 1L-MoS2 enabling scalable and high-performance nanosheet transistors and paving the way toward advanced device architectures.
{"title":"Conformal Atomic Layer Deposition of Gate Dielectrics on Monolayer MoS2 for Gate-All-Around Transistors","authors":"Yuan-Chun Su;Shu-Jui Chang;D. Mahaveer Sathaiya;Chen-Feng Hsu;Bo-Heng Liu;Chien-Ying Su;Chi-Chung Kei;Yen-Fa Liao;Shu-Chih Haw;Chih-Wei Hu;San-Lin Liew;Vincent Duen-Huei Hou;T.-Y. Lee;Chao-Ching Cheng;Tsung-En Lee;Iuliana P. Radu","doi":"10.1109/TED.2025.3629599","DOIUrl":"https://doi.org/10.1109/TED.2025.3629599","url":null,"abstract":"To address the challenge of directly nucleating dielectrics on a dangling bond-free surface, we present an optimized atomic layer deposition (ALD) process to achieve uniform AlO<sub>x</sub> and HfO<sub>x</sub> dielectric layers on a monolayer MoS<sub>2</sub> nanosheet within a gate-all-around (GAA) architecture. By introducing a trimethylaluminum (TMA) precursor soaking step in the ALD cycles, a thin and dense AlO<sub>x</sub> interfacial layer (IL) can be formed on the MoS<sub>2</sub> surface. Depositing the AlO<sub>x</sub> IL at 90<inline-formula> <tex-math>$~^{circ }$ </tex-math></inline-formula>C and the subsequent HfO<sub>x</sub> high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> layer at 200<inline-formula> <tex-math>$~^{circ }$ </tex-math></inline-formula>C minimizes defect formations and preserves the MoS<sub>2</sub> channel’s integrity. A postdeposition anneal at 400<inline-formula> <tex-math>$~^{circ }$ </tex-math></inline-formula>C further improves device performance, achieving an <sc>ON</small>/<sc>OFF</small> ratio of 10<sup>8</sup> and a improved subthreshold swing (SS). These improvements are attributed to a reduction of Al–OH bonds in the AlO<sub>x</sub> layer, which lowers the interface trap density and enhances carrier mobility. This study demonstrates the feasibility of integrating high-quality ALD gate dielectrics with 1L-MoS<sub>2</sub> enabling scalable and high-performance nanosheet transistors and paving the way toward advanced device architectures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7122-7127"},"PeriodicalIF":3.2,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The wake-up effect in ultrathin (sub-6-nm) hafnium-zirconium-oxide (HZO) ferroelectric films is a critical reliability challenge that slows down their implementation in nonvolatile memories. This article reports on the existence of optimal frequency that maximizes the efficiency of the wake-up process. To explain this phenomenon, a physical model based on the field-driven migration of oxygen ions and the interaction with oxygen vacancies is proposed. The optimal wake-up frequency is attributed to a temporal matching between the dynamics of oxygen ions across the film and the cycling field frequency. The model is validated by comprehensive experiments, including the field dependence of the optimal frequency and the thermally activated behavior with a thermal activation energy of 0.14--0.42 eV. This work provides a physical picture of the mechanism behind the wake-up effect and offers a guideline for an efficient wake-up process.
{"title":"Wake-Up Mechanism With De-Pinning Dynamics in Ultrathin Hf0.5Zr0.5O2: Understanding Frequency and Temperature Dependences","authors":"Kosuke Ito;Mitsuru Takenaka;Shinichi Takagi;Kasidit Toprasertpong","doi":"10.1109/TED.2025.3628364","DOIUrl":"https://doi.org/10.1109/TED.2025.3628364","url":null,"abstract":"The wake-up effect in ultrathin (sub-6-nm) hafnium-zirconium-oxide (HZO) ferroelectric films is a critical reliability challenge that slows down their implementation in nonvolatile memories. This article reports on the existence of optimal frequency that maximizes the efficiency of the wake-up process. To explain this phenomenon, a physical model based on the field-driven migration of oxygen ions and the interaction with oxygen vacancies is proposed. The optimal wake-up frequency is attributed to a temporal matching between the dynamics of oxygen ions across the film and the cycling field frequency. The model is validated by comprehensive experiments, including the field dependence of the optimal frequency and the thermally activated behavior with a thermal activation energy of 0.14--0.42 eV. This work provides a physical picture of the mechanism behind the wake-up effect and offers a guideline for an efficient wake-up process.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7145-7152"},"PeriodicalIF":3.2,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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