Pub Date : 2025-11-03DOI: 10.1109/TED.2025.3623949
Xinkang Chen;Sumeet Kumar Gupta
In [1], the following error and its correction should be noted. The derivations, results, and analyses in [1] use the correct equations, and thus, this error does not impact the other content in [1].
{"title":"Erratum to “Spatially Resolved Conductivity of Rectangular Interconnects Considering Surface Scattering—Part II: Circuit-Compatible Modeling”","authors":"Xinkang Chen;Sumeet Kumar Gupta","doi":"10.1109/TED.2025.3623949","DOIUrl":"https://doi.org/10.1109/TED.2025.3623949","url":null,"abstract":"In [1], the following error and its correction should be noted. The derivations, results, and analyses in [1] use the correct equations, and thus, this error does not impact the other content in [1].","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7191-7191"},"PeriodicalIF":3.2,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11224364","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cryogenic CMOS technology is crucial for high-performance and quantum computing, but faces significant reliability challenges from exacerbated hot carrier degradation (HCD) at ultralow temperatures. In addition, cryogenic HCD (cryo-HCD) is further complicated by the coupling of cryogenic-specific phenomena, such as band tail states. In this work, a change temperature measure-stress-measure (MSM) method is established based on FinFET, which can separate the cryo-HCD from the effects of band tail states. It is found that additional Vth shifts under cryo-HCD in pFinFET at 10 K. The physical mechanism is revealed by advanced atomic-scale characterization [transmission electron microscope (TEM)/energy-dispersive X-ray spectroscopy (EDS)/electron energy-loss spectroscopy (EELS)], which identifies directional Ge migration from Si${}_{{1}-{x}}$ Gex (SiGe) drain regions into the channel as the origin. Combined with ab initio calculations, we establish that this Ge migration suppresses band tail states, directly inducing the anomalous ${V} _{text {th}}$ shift. These findings offer fundamental insights into cryogenic degradation mechanisms, underscoring the crucial role of atomic-scale material transport, which is essential for cryogenic reliability.
{"title":"Investigation on Cryogenic Reliability in FinFETs Under Hot Carrier Stress","authors":"Zuoyuan Dong;Zirui Wang;Hongbo Wang;Xiaomei Li;Chen Luo;Jialu Huang;Lan Li;Zepeng Huang;Zixuan Sun;Yue-Yang Liu;Xing Wu;Runsheng Wang","doi":"10.1109/TED.2025.3623950","DOIUrl":"https://doi.org/10.1109/TED.2025.3623950","url":null,"abstract":"Cryogenic CMOS technology is crucial for high-performance and quantum computing, but faces significant reliability challenges from exacerbated hot carrier degradation (HCD) at ultralow temperatures. In addition, cryogenic HCD (cryo-HCD) is further complicated by the coupling of cryogenic-specific phenomena, such as band tail states. In this work, a change temperature measure-stress-measure (MSM) method is established based on FinFET, which can separate the cryo-HCD from the effects of band tail states. It is found that additional <italic>V</i><sub>th</sub> shifts under cryo-HCD in pFinFET at 10 K. The physical mechanism is revealed by advanced atomic-scale characterization [transmission electron microscope (TEM)/energy-dispersive X-ray spectroscopy (EDS)/electron energy-loss spectroscopy (EELS)], which identifies directional Ge migration from Si<inline-formula> <tex-math>${}_{{1}-{x}}$ </tex-math></inline-formula>Ge<italic><sub>x</sub></i> (SiGe) drain regions into the channel as the origin. Combined with <italic>ab initio</i> calculations, we establish that this Ge migration suppresses band tail states, directly inducing the anomalous <inline-formula> <tex-math>${V} _{text {th}}$ </tex-math></inline-formula> shift. These findings offer fundamental insights into cryogenic degradation mechanisms, underscoring the crucial role of atomic-scale material transport, which is essential for cryogenic reliability.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7153-7160"},"PeriodicalIF":3.2,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-24DOI: 10.1109/TED.2025.3616087
Fabia Farlin Athena;Jimin Kang;Matthias Passlack;Nathaniel Safron;Didem Dede;Koustav Jana;Balreen Saini;Xinxin Wang;Shuhan Liu;Jonathan Hartanto;Ethan Boneh;Hugo J.-Y. Chen;Chi-Hsin Huang;Qing Lin;Donglai Zhong;Kaitlyn Leitherer;Paul C. McIntyre;Gregory Pitner;Iuliana P. Radu;H.-S. Philip Wong
We demonstrate that inserting an ultrathin (<1> $mathrm {Al_{2}O_{3}}$ layer between an oxide–semiconductor (OS) channel and a high-$kappa $ gate dielectric creates an interface dipole (ID) that shifts the threshold voltage ($textit {V} {_{text {T}}}$ ) of OS transistors. The ID engineering process by $mathrm {Al_{2}O_{3}}$ layer integration raises $textit {V} {_{text {T}}}$ of 2% W-doped indium tungsten oxide (IWO) FETs by ~450 mV relative to a reference $mathrm {HfO_{2}}$ stack, enabling normally-OFF operation with negligible degradation in mobility or subthreshold swing (SS). The $textit {V} {_{text {T}}}$ shift remains stable from 85 °C down to cryogenic temperatures. Under a worst case + 2-V positive bias stress at 85 °C, ID-engineered oxide–semiconductor field-effect transistors (OSFETs) exhibit a ~60-mV shift versus ~300 mV for the baseline device. The technique is effective across multiple OS channels [$mathrm {In_{2}O_{3}}$ , indium–tin oxide (ITO) and indium–gallium–zinc oxide (IGZO)] and gate lengths down to ~50 nm. Simulations calibrated to the measured devices show that the leakage reduction afforded by ID engineering decreases refresh energy of two transistor gain cell (2T-GC) arrays by $sim {5}times {10} ^{{4}} times $ , establishing ID engineering as a low thermal budget knob for energy-efficient, high-density GC memories.
我们证明了在氧化物半导体（OS）通道和高$kappa $栅极电介质之间插入超薄（$mathrm {Al_{2}O_{3}}$层）可以产生界面偶极子（ID），从而移动OS晶体管的阈值电压（$textit {V} {_{text {T}}}$）。ID工程过程由$mathrm {Al_{2}O_{3}}$层集成提出$textit {V} {_{text {T}}}$的2个% W-doped indium tungsten oxide (IWO) FETs by ~450 mV relative to a reference $mathrm {HfO_{2}}$ stack, enabling normally-OFF operation with negligible degradation in mobility or subthreshold swing (SS). The $textit {V} {_{text {T}}}$ shift remains stable from 85 °C down to cryogenic temperatures. Under a worst case + 2-V positive bias stress at 85 °C, ID-engineered oxide–semiconductor field-effect transistors (OSFETs) exhibit a ~60-mV shift versus ~300 mV for the baseline device. The technique is effective across multiple OS channels [ $mathrm {In_{2}O_{3}}$ , indium–tin oxide (ITO) and indium–gallium–zinc oxide (IGZO)] and gate lengths down to ~50 nm. Simulations calibrated to the measured devices show that the leakage reduction afforded by ID engineering decreases refresh energy of two transistor gain cell (2T-GC) arrays by $sim {5}times {10} ^{{4}} times $ , establishing ID engineering as a low thermal budget knob for energy-efficient, high-density GC memories.
{"title":"Multi-VT in Oxide--Semiconductor Transistors Leveraging Sub-1-nm Dipoles for Low-Refresh Energy Gain Cell Memory","authors":"Fabia Farlin Athena;Jimin Kang;Matthias Passlack;Nathaniel Safron;Didem Dede;Koustav Jana;Balreen Saini;Xinxin Wang;Shuhan Liu;Jonathan Hartanto;Ethan Boneh;Hugo J.-Y. Chen;Chi-Hsin Huang;Qing Lin;Donglai Zhong;Kaitlyn Leitherer;Paul C. McIntyre;Gregory Pitner;Iuliana P. Radu;H.-S. Philip Wong","doi":"10.1109/TED.2025.3616087","DOIUrl":"https://doi.org/10.1109/TED.2025.3616087","url":null,"abstract":"We demonstrate that inserting an ultrathin (<1> <tex-math>$mathrm {Al_{2}O_{3}}$ </tex-math></inline-formula> layer between an oxide–semiconductor (OS) channel and a high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula> gate dielectric creates an interface dipole (ID) that shifts the threshold voltage (<inline-formula> <tex-math>$textit {V} {_{text {T}}}$ </tex-math></inline-formula>) of OS transistors. The ID engineering process by <inline-formula> <tex-math>$mathrm {Al_{2}O_{3}}$ </tex-math></inline-formula> layer integration raises <inline-formula> <tex-math>$textit {V} {_{text {T}}}$ </tex-math></inline-formula> of 2% W-doped indium tungsten oxide (IWO) FETs by ~450 mV relative to a reference <inline-formula> <tex-math>$mathrm {HfO_{2}}$ </tex-math></inline-formula> stack, enabling normally-OFF operation with negligible degradation in mobility or subthreshold swing (SS). The <inline-formula> <tex-math>$textit {V} {_{text {T}}}$ </tex-math></inline-formula> shift remains stable from 85 °C down to cryogenic temperatures. Under a worst case + 2-V positive bias stress at 85 °C, ID-engineered oxide–semiconductor field-effect transistors (OSFETs) exhibit a ~60-mV shift versus ~300 mV for the baseline device. The technique is effective across multiple OS channels [<inline-formula> <tex-math>$mathrm {In_{2}O_{3}}$ </tex-math></inline-formula>, indium–tin oxide (ITO) and indium–gallium–zinc oxide (IGZO)] and gate lengths down to ~50 nm. Simulations calibrated to the measured devices show that the leakage reduction afforded by ID engineering decreases refresh energy of two transistor gain cell (2T-GC) arrays by <inline-formula> <tex-math>$sim {5}times {10} ^{{4}} times $ </tex-math></inline-formula>, establishing ID engineering as a low thermal budget knob for energy-efficient, high-density GC memories.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7161-7166"},"PeriodicalIF":3.2,"publicationDate":"2025-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-14DOI: 10.1109/TED.2025.3613466
Dasom Lee;Tsu-Jae King Liu
Relevant to the cryogenic operation of CMOS integrated circuits, random telegraph noise (RTN) temperature dependence was investigated using FinFET devices fabricated using Samsung’s 14-nm process technology. Transistor drive current degradation due to trapped charge in the gate oxide is experimentally observed to worsen with decreasing temperature. A newfound dependence of trap capture and emission rates on drain voltage is observed and explained. Technology computer-aided design (TCAD) simulations using models calibrated to the measured data are then performed to investigate trends in RTN temperature dependence with transistor scaling (3-nm FinFET) and evolution [2-nm gate-all-around field-effect transistor (GAAFET)].
{"title":"Study of Defect-Induced Noise in Advanced MOSFETs for Cryogenic Operation","authors":"Dasom Lee;Tsu-Jae King Liu","doi":"10.1109/TED.2025.3613466","DOIUrl":"https://doi.org/10.1109/TED.2025.3613466","url":null,"abstract":"Relevant to the cryogenic operation of CMOS integrated circuits, random telegraph noise (RTN) temperature dependence was investigated using FinFET devices fabricated using Samsung’s 14-nm process technology. Transistor drive current degradation due to trapped charge in the gate oxide is experimentally observed to worsen with decreasing temperature. A newfound dependence of trap capture and emission rates on drain voltage is observed and explained. Technology computer-aided design (TCAD) simulations using models calibrated to the measured data are then performed to investigate trends in RTN temperature dependence with transistor scaling (3-nm FinFET) and evolution [2-nm gate-all-around field-effect transistor (GAAFET)].","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6379-6382"},"PeriodicalIF":3.2,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The switching efficiency of conventional silicon-based field-effect transistors (FETs) is fundamentally constrained by their 60-mV/dec subthreshold swing (SS) lower bound. Recently, we proposed an Al-drain FET to overcome this limitation. In this work, we further design and experimentally demonstrate dual types of (p/n) silicon transistors featuring various metal-drain (MD) structure MD field effect transistor (MDFET). Particularly, Al and Ti are selected for n-type MDFET, while Pt is adapted for p-type MDFET based on their work function. Measurement results show that both n-type and p-type MDFETs achieve ultrasteep average SS ($ll$ 10 mV/dec) over multiple decades of current. In addition, TCAD simulations have been performed, and the simulation results agree well with experimental data qualitatively. Detailed analysis reveals that the Schottky junction at the metal–silicon drain interface induces a localized electric field amplification ($gt 1.66times $ compared to conventional doped silicon drain) and extends the depletion region, synergistically enhancing impact ionization (II) of carriers. This mechanism establishes a regenerative feedback loop, enabling ultrasteep switching behavior. Finally, a compact model of MDFET is created for circuit simulation, and an inverter circuit composed of pMOS and n-type MDFET is constructed experimentally. Both measured data and model simulation agree well, illustrating the potential of MDFET for CMOS-compatible low-power logic applications.
{"title":"Ultrasteep Subthreshold Slope Metal-Drain Dual-Type (p/n) Silicon Transistors: Characterization, Analysis, and Application","authors":"Zhibo Chen;Baowei Yuan;Haobo Huang;Weiao Chen;Biyu Guo;Chengjie Tang;Yingxin Chen;Weizhuo Gan;Chunsong Zhao;Zhaozhao Hou;Qiang Zhang;Jiachen Gao;Jiale Wang;Jeffrey Xu;Guangxi Hu;Jing Wan;Ye Lu","doi":"10.1109/TED.2025.3612318","DOIUrl":"https://doi.org/10.1109/TED.2025.3612318","url":null,"abstract":"The switching efficiency of conventional silicon-based field-effect transistors (FETs) is fundamentally constrained by their 60-mV/dec subthreshold swing (SS) lower bound. Recently, we proposed an Al-drain FET to overcome this limitation. In this work, we further design and experimentally demonstrate dual types of (p/n) silicon transistors featuring various metal-drain (MD) structure MD field effect transistor (MDFET). Particularly, Al and Ti are selected for n-type MDFET, while Pt is adapted for p-type MDFET based on their work function. Measurement results show that both n-type and p-type MDFETs achieve ultrasteep average SS (<inline-formula> <tex-math>$ll$ </tex-math></inline-formula> 10 mV/dec) over multiple decades of current. In addition, TCAD simulations have been performed, and the simulation results agree well with experimental data qualitatively. Detailed analysis reveals that the Schottky junction at the metal–silicon drain interface induces a localized electric field amplification (<inline-formula> <tex-math>$gt 1.66times $ </tex-math></inline-formula> compared to conventional doped silicon drain) and extends the depletion region, synergistically enhancing impact ionization (II) of carriers. This mechanism establishes a regenerative feedback loop, enabling ultrasteep switching behavior. Finally, a compact model of MDFET is created for circuit simulation, and an inverter circuit composed of pMOS and n-type MDFET is constructed experimentally. Both measured data and model simulation agree well, illustrating the potential of MDFET for CMOS-compatible low-power logic applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6355-6360"},"PeriodicalIF":3.2,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We report back-end-of-line (BEOL) compatible p-type $text{tellurium}_{1-x}text{selenium}_{x}$ ($text{Te}_{1-textit{x}}text{Se}_{textit{x}}$ ) field-effect transistors (FETs) with aggressively scaled channel length down to 50 nm, fabricated via a novel Te–Se co-sputtering method. Se incorporation effectively widens the bandgap, as confirmed by density functional theory (DFT) calculations, resulting in suppressed off-state current and enhanced device performance. Comprehensive experimental characterizations—including contact barrier height extraction, temperature-dependent transport measurements from 295 K down to 77 K, and bias temperature instability (BTI) analysis—demonstrate that Te${}_{{0}.{8}}$ Se${}_{{0}.{2}}$ FETs achieve a mobility of 24 cm2/V$cdot $ s, $textit {I}_{text {on}}$ /$textit {I}_{text {off}}$ ratio exceeding $10^{{4}}$ , and subthreshold swing (SS) near 300 mV/Dec. By integrating with indium–gallium–zinc-oxide (IGZO) n-FETs through monolithic 3-D stacking, we realize vertically stacked circuits: an n–p dynamic random-access-memory (DRAM) cell with retention exceeding 1000 s, a short-channel complementary FET (CFET) inverter showing a voltage gain of 38 at $textit {V}_{text {DD}} = 2.5$ V, and a compact CFET-structured static random-access-memory (SRAM) cell with a 33% area reduction compared to conventional 6 T SRAM. This work demonstrates co-sputtered $text{Te}_{1-textit{x}}text{Se}_{x}$ as a promising p-type channel for high-density, energy-efficient monolithic 3-D (M3D) integration.
我们报告了后端线（BEOL）兼容的p型$text{tellurium}_{1-x}text{selenium}_{x}$ （$text{Te}_{1-textit{x}}text{Se}_{textit{x}}$）场效应晶体管（fet），其通道长度可缩小至50 nm，通过新型Te-Se共溅射方法制造。正如密度泛函理论（DFT）计算所证实的那样，Se的掺入有效地扩大了带隙，从而抑制了断开状态电流并增强了器件性能。综合实验表征——包括接触势垒高度提取、295 K至77 K温度相关输运测量和偏置温度不稳定性（BTI）分析——表明，${}_{{0}.{8}}$ Se ${}_{{0}.{2}}$ fet的迁移率达到24 cm2/V $cdot $ s, $textit {I}_{text {on}}$ / $textit {I}_{text {off}}$比超过$10^{{4}}$，亚阈值摆幅（SS）接近300 mV/Dec。通过单片3d堆叠与铟镓锌氧化物（IGZO） n-FET集成，我们实现了垂直堆叠电路：n-p动态随机存取存储器（DRAM）单元保持时间超过1000 s，短通道互补FET （cet）逆变器在$textit {V}_{text {DD}} = 2.5$ V下显示38电压增益，紧凑的CFET结构静态随机存取存储器（SRAM）单元具有33% area reduction compared to conventional 6 T SRAM. This work demonstrates co-sputtered $text{Te}_{1-textit{x}}text{Se}_{x}$ as a promising p-type channel for high-density, energy-efficient monolithic 3-D (M3D) integration.
{"title":"BEOL-Compatible Co-Sputtered $text{Te}_{text{1}-x}text{Se}_{x}$ p-FETs With Bandgap Engineering Enabling Monolithic 3-D CMOS Logic and Memory","authors":"Ying Xu;Yiyuan Sun;Zuopu Zhou;Zijie Zheng;Sheng Luo;Gan Liu;Chen Sun;Yuye Kang;Kai Ni;Gengchiau Liang;Xiao Gong","doi":"10.1109/TED.2025.3612914","DOIUrl":"https://doi.org/10.1109/TED.2025.3612914","url":null,"abstract":"We report back-end-of-line (BEOL) compatible p-type <inline-formula> <tex-math>$text{tellurium}_{1-x}text{selenium}_{x}$ </tex-math></inline-formula> (<inline-formula> <tex-math>$text{Te}_{1-textit{x}}text{Se}_{textit{x}}$ </tex-math></inline-formula>) field-effect transistors (FETs) with aggressively scaled channel length down to 50 nm, fabricated via a novel Te–Se co-sputtering method. Se incorporation effectively widens the bandgap, as confirmed by density functional theory (DFT) calculations, resulting in suppressed <sc>off</small>-state current and enhanced device performance. Comprehensive experimental characterizations—including contact barrier height extraction, temperature-dependent transport measurements from 295 K down to 77 K, and bias temperature instability (BTI) analysis—demonstrate that Te<inline-formula> <tex-math>${}_{{0}.{8}}$ </tex-math></inline-formula>Se<inline-formula> <tex-math>${}_{{0}.{2}}$ </tex-math></inline-formula> FETs achieve a mobility of 24 cm<sup>2</sup>/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, <inline-formula> <tex-math>$textit {I}_{text {on}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$textit {I}_{text {off}}$ </tex-math></inline-formula> ratio exceeding <inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula>, and subthreshold swing (SS) near 300 mV/Dec. By integrating with indium–gallium–zinc-oxide (IGZO) n-FETs through monolithic 3-D stacking, we realize vertically stacked circuits: an n–p dynamic random-access-memory (DRAM) cell with retention exceeding 1000 s, a short-channel complementary FET (CFET) inverter showing a voltage gain of 38 at <inline-formula> <tex-math>$textit {V}_{text {DD}} = 2.5$ </tex-math></inline-formula> V, and a compact CFET-structured static random-access-memory (SRAM) cell with a 33% area reduction compared to conventional 6 T SRAM. This work demonstrates co-sputtered <inline-formula> <tex-math>$text{Te}_{1-textit{x}}text{Se}_{x}$ </tex-math></inline-formula> as a promising p-type channel for high-density, energy-efficient monolithic 3-D (M3D) integration.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7167-7174"},"PeriodicalIF":3.2,"publicationDate":"2025-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-06DOI: 10.1109/TED.2025.3613287
Ying-Jie Ma;Song Sun;Yue Huang;Shuai Zhang;Li-Ling Fu;Xin-Xin Wang;Jin-Yang Wei;Di Wu;Ai-Dong Li
Memristors are poised to drive the next wave of artificial intelligence advancements, owing to their exceptional potential for both storage and computation. However, their integration into flexible devices remains a tough challenge due to their inherent rigidity and high processing temperature, limiting their application in cutting-edge technologies such as soft robotics and wearable electronics. Motivated by human wrinkled skin, a PDMS/Au/Al2O3/HfO2/Ag stretchable memristor (C-HAP for short) fabricated via pre-stretch release and atomic layer deposition (ALD) is proposed in this study. The C-HAP memristor can withstand 10% of stretch strain and has a stable resistive switching (RS) behavior. The wrinkled structure allows stretching to be converted from the original in-plane stretching to out-of-plane localized bending, and the cushioning and stress relaxation effects of the wrinkles themselves contribute to the improvement of their mechanical properties. In addition, the C-HAP memristor can act as an artificial synapse and mimic synaptic behavior successfully under stretching. Furthermore, the triple spike time-dependent plasticity of C-HAP memristor is utilized to implement the Bienenstock–Cooper–Munro (BCM) learning rule, which enables orientation selectivity recognition in feedforward neural networks. A new methodology for designing stretchable memristors with stable storage and computational ability under dynamic conditions is provided by this research.
{"title":"Al2O3/HfO2-Based Stretchable Synaptic Memristor for Orientation Selectivity Recognition","authors":"Ying-Jie Ma;Song Sun;Yue Huang;Shuai Zhang;Li-Ling Fu;Xin-Xin Wang;Jin-Yang Wei;Di Wu;Ai-Dong Li","doi":"10.1109/TED.2025.3613287","DOIUrl":"https://doi.org/10.1109/TED.2025.3613287","url":null,"abstract":"Memristors are poised to drive the next wave of artificial intelligence advancements, owing to their exceptional potential for both storage and computation. However, their integration into flexible devices remains a tough challenge due to their inherent rigidity and high processing temperature, limiting their application in cutting-edge technologies such as soft robotics and wearable electronics. Motivated by human wrinkled skin, a PDMS/Au/Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>/Ag stretchable memristor (C-HAP for short) fabricated via pre-stretch release and atomic layer deposition (ALD) is proposed in this study. The C-HAP memristor can withstand 10% of stretch strain and has a stable resistive switching (RS) behavior. The wrinkled structure allows stretching to be converted from the original in-plane stretching to out-of-plane localized bending, and the cushioning and stress relaxation effects of the wrinkles themselves contribute to the improvement of their mechanical properties. In addition, the C-HAP memristor can act as an artificial synapse and mimic synaptic behavior successfully under stretching. Furthermore, the triple spike time-dependent plasticity of C-HAP memristor is utilized to implement the Bienenstock–Cooper–Munro (BCM) learning rule, which enables orientation selectivity recognition in feedforward neural networks. A new methodology for designing stretchable memristors with stable storage and computational ability under dynamic conditions is provided by this research.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6368-6374"},"PeriodicalIF":3.2,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-01DOI: 10.1109/TED.2025.3613286
Chunlin Liu;Xuesong Li;Ling-Xuan Qian
High-$k$ gate dielectrics have been widely studied in various transistors due to the unique properties, including but not limited to a stronger gate control capability. However, research on high-$k$ gate dielectrics in graphene field-effect transistors (GFETs) is quite limited so far, and the underlying mechanisms remain unclear. This study reports the first implementation of a binary-metal oxide of Hf1-xLaxOy as the gate dielectric in GFETs, and the effects of La incorporation into HfO2 gate dielectric were comprehensively investigated. It was found that La incorporation can effectively increase the dielectric constant, suppress the oxygen-vacancy defects, and increase the crystallization temperature of HfO2 through X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and X-ray diffraction (XRD) analyses. As a result, the electrical characteristics of GFETs can be significantly improved. In particular, the GFET with a Hf0.4La0.6Oy gate dielectric exhibits the best performance in the air within all the samples, including a small Dirac point Voltage (${V}_{text {Dirac}}text {)}$ of 4.9 V, negligible hysteresis ($Delta {V}_{text {Dirac}} =$ –0.2 V), and high hole/electron mobility of 1510/1250 cm2/V$cdot $ s, which is almost one and two orders of magnitude higher than those with pure HfO2 and SiO2 gate dielectrics under similar small gate voltages. Nevertheless, excessive La incorporation deteriorates the characteristics by generating hydroxyl defects, increasing surface roughness, and triggering recrystallization.
{"title":"Improved Performance of Graphene Field-Effect Transistors With HfO2 Gate Dielectric via La Incorporation","authors":"Chunlin Liu;Xuesong Li;Ling-Xuan Qian","doi":"10.1109/TED.2025.3613286","DOIUrl":"https://doi.org/10.1109/TED.2025.3613286","url":null,"abstract":"High-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> gate dielectrics have been widely studied in various transistors due to the unique properties, including but not limited to a stronger gate control capability. However, research on high-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> gate dielectrics in graphene field-effect transistors (GFETs) is quite limited so far, and the underlying mechanisms remain unclear. This study reports the first implementation of a binary-metal oxide of Hf<sub>1-<i>x</i></sub>La<italic><sub>x</sub></i>O<italic><sub>y</sub></i> as the gate dielectric in GFETs, and the effects of La incorporation into HfO<sub>2</sub> gate dielectric were comprehensively investigated. It was found that La incorporation can effectively increase the dielectric constant, suppress the oxygen-vacancy defects, and increase the crystallization temperature of HfO<sub>2</sub> through X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and X-ray diffraction (XRD) analyses. As a result, the electrical characteristics of GFETs can be significantly improved. In particular, the GFET with a Hf<sub>0.4</sub>La<sub>0.6</sub>O<italic><sub>y</sub></i> gate dielectric exhibits the best performance in the air within all the samples, including a small Dirac point Voltage (<inline-formula> <tex-math>${V}_{text {Dirac}}text {)}$ </tex-math></inline-formula> of 4.9 V, negligible hysteresis (<inline-formula> <tex-math>$Delta {V}_{text {Dirac}} =$ </tex-math></inline-formula> –0.2 V), and high hole/electron mobility of 1510/1250 cm<sup>2</sup>/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, which is almost one and two orders of magnitude higher than those with pure HfO<sub>2</sub> and SiO<sub>2</sub> gate dielectrics under similar small gate voltages. Nevertheless, excessive La incorporation deteriorates the characteristics by generating hydroxyl defects, increasing surface roughness, and triggering recrystallization.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6349-6354"},"PeriodicalIF":3.2,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study thoroughly investigates the on-current ($text {I}_{text {on}}text {)}$ and nonconductive stress (NCS) reliability of the contact field plate lateral double-diffused metal–oxide–semiconductor (CFP LDMOS) with bipolar–CMOS–DMOS (BCD) technology using different fluorine (F) implantation methodologies. Two devices with different oxide cap thicknesses during annealing after F implantation are compared to a standard (STD) device without F implantation. The thin oxide cap device demonstrates the poor Si quality and defect generation after annealing, resulting in decreased $text {I}_{text {on}}$ as the F-imp dose increases. In contrast, the F treatment can effectively passivate defects in the thick oxide cap device, leading to improved $text {I}_{text {on}}$ and NCS reliability. Finally, physical mechanisms based on defect analysis, scanning electron microscope (SEM) images, and secondary ion mass spectrometer (SIMS) profiles are proposed to clarify the phenomena.
{"title":"Analysis of Fluorine Implantation With Different Oxide Cap Thicknesses During Annealing in Contact Field Plate Lateral Double-Diffused MOS With 0.13-μm Bipolar–CMOS–DMOS Technology","authors":"Yu-Fa Tu;Ting-Chang Chang;Wei-Chieh Hung;Hung-Ming Kuo;Ya-Huan Lee;Yu-Hsiang Tsai","doi":"10.1109/TED.2025.3609743","DOIUrl":"https://doi.org/10.1109/TED.2025.3609743","url":null,"abstract":"This study thoroughly investigates the <sc>on</small>-current (<inline-formula> <tex-math>$text {I}_{text {on}}text {)}$ </tex-math></inline-formula> and nonconductive stress (NCS) reliability of the contact field plate lateral double-diffused metal–oxide–semiconductor (CFP LDMOS) with bipolar–CMOS–DMOS (BCD) technology using different fluorine (F) implantation methodologies. Two devices with different oxide cap thicknesses during annealing after F implantation are compared to a standard (STD) device without F implantation. The thin oxide cap device demonstrates the poor Si quality and defect generation after annealing, resulting in decreased <inline-formula> <tex-math>$text {I}_{text {on}}$ </tex-math></inline-formula> as the F-imp dose increases. In contrast, the F treatment can effectively passivate defects in the thick oxide cap device, leading to improved <inline-formula> <tex-math>$text {I}_{text {on}}$ </tex-math></inline-formula> and NCS reliability. Finally, physical mechanisms based on defect analysis, scanning electron microscope (SEM) images, and secondary ion mass spectrometer (SIMS) profiles are proposed to clarify the phenomena.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6383-6386"},"PeriodicalIF":3.2,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-29DOI: 10.1109/TED.2025.3611907
Andreu L. Glasmann;Wendy L. Sarney;Christine K. McGinn;Christina A. Hacker;Sina Najmaei
In this article, we present a simulation methodology for studying device-to-device variability in submicrometer planar hafnia-based ferroelectric field-effect transistors (FeFETs) with silicon channels. The simulation methodology is based on thin films of hafnium zirconium oxide (HZO) fabricated under CMOS-compatible conditions, which were characterized using piezoresponse force microscopy (PFM). The PFM images were analyzed using a combination of unsupervised learning with Gaussian mixture models (GMMs) and electrical measurements of polarization-field characteristics of metal–ferroelectric–metal capacitors. The results were directly integrated into an extensive Monte Carlo study based on 2-D device simulations of short-channel front-end FeFETs, where we simulate high- and low-threshold voltage states for 100 total device configurations. From this framework, we quantify how the granular and multiphase nature of ferroelectric HZO contribute to the transport within the semiconductor channel. The results indicate that threshold voltages for both high- and low-threshold states and the subthreshold swings can vary up to about 400 mV and 20 mV/dec, respectively.
{"title":"Analysis of Short-Channel Hafnia-Based FeFET Device Variability Guided by Piezoresponse Force Microscopy","authors":"Andreu L. Glasmann;Wendy L. Sarney;Christine K. McGinn;Christina A. Hacker;Sina Najmaei","doi":"10.1109/TED.2025.3611907","DOIUrl":"https://doi.org/10.1109/TED.2025.3611907","url":null,"abstract":"In this article, we present a simulation methodology for studying device-to-device variability in submicrometer planar hafnia-based ferroelectric field-effect transistors (FeFETs) with silicon channels. The simulation methodology is based on thin films of hafnium zirconium oxide (HZO) fabricated under CMOS-compatible conditions, which were characterized using piezoresponse force microscopy (PFM). The PFM images were analyzed using a combination of unsupervised learning with Gaussian mixture models (GMMs) and electrical measurements of polarization-field characteristics of metal–ferroelectric–metal capacitors. The results were directly integrated into an extensive Monte Carlo study based on 2-D device simulations of short-channel front-end FeFETs, where we simulate high- and low-threshold voltage states for 100 total device configurations. From this framework, we quantify how the granular and multiphase nature of ferroelectric HZO contribute to the transport within the semiconductor channel. The results indicate that threshold voltages for both high- and low-threshold states and the subthreshold swings can vary up to about 400 mV and 20 mV/dec, respectively.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 11","pages":"6361-6367"},"PeriodicalIF":3.2,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145479368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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