Pub Date : 2024-12-05DOI: 10.1109/TED.2024.3508656
Seokjun Kim;Daniel C. Shoemaker;Anwarul Karim;Husam Walwil;Matthew T. DeJarld;Maher B. Tahhan;Jarrod Vaillancourt;Eduardo M. Chumbes;Jeffrey R. Laroche;Georges Pavlidis;Samuel Graham;Sukwon Choi
Gallium nitride (GaN)-based radio frequency (RF) power amplifiers are spearheading the deployment of next-generation wireless systems owing to the large power handling capability at high frequencies and high-power-added efficiency. Unfortunately, this high power density operation leads to severe overheating, which reduces its lifetime and efficiency. Thus, correctly characterizing the temperature rise is of crucial importance to properly design GaN devices and cooling solutions. Optical-based thermometry techniques such as Raman thermometry and infrared (IR) thermography are commonly used to estimate the peak temperature rise, but they are limited by optical access, topside metallization, and depth averaging. Gate resistance thermometry (GRT) offers an alternative method to measure the temperature without needing optical access to the channel. Therefore, in this work, Raman thermometry is used in conjunction with GRT and electrothermal modeling to determine the accuracy of each method for a field-plated GaN high electron mobility transistor (HEMT) under various bias conditions. While both Raman thermometry and GRT measured a similar temperature rise under fully open (FO) channel conditions, it was found that GRT was better at estimating the peak temperature under a partially pinched-off (PPO) bias condition due to the source-connected field plate (SCFP) restricting optical access to the drain side of the gate edge.
{"title":"A Comparative Analysis of Electrical and Optical Thermometry Techniques for AlGaN/GaN HEMTs","authors":"Seokjun Kim;Daniel C. Shoemaker;Anwarul Karim;Husam Walwil;Matthew T. DeJarld;Maher B. Tahhan;Jarrod Vaillancourt;Eduardo M. Chumbes;Jeffrey R. Laroche;Georges Pavlidis;Samuel Graham;Sukwon Choi","doi":"10.1109/TED.2024.3508656","DOIUrl":"https://doi.org/10.1109/TED.2024.3508656","url":null,"abstract":"Gallium nitride (GaN)-based radio frequency (RF) power amplifiers are spearheading the deployment of next-generation wireless systems owing to the large power handling capability at high frequencies and high-power-added efficiency. Unfortunately, this high power density operation leads to severe overheating, which reduces its lifetime and efficiency. Thus, correctly characterizing the temperature rise is of crucial importance to properly design GaN devices and cooling solutions. Optical-based thermometry techniques such as Raman thermometry and infrared (IR) thermography are commonly used to estimate the peak temperature rise, but they are limited by optical access, topside metallization, and depth averaging. Gate resistance thermometry (GRT) offers an alternative method to measure the temperature without needing optical access to the channel. Therefore, in this work, Raman thermometry is used in conjunction with GRT and electrothermal modeling to determine the accuracy of each method for a field-plated GaN high electron mobility transistor (HEMT) under various bias conditions. While both Raman thermometry and GRT measured a similar temperature rise under fully open (FO) channel conditions, it was found that GRT was better at estimating the peak temperature under a partially pinched-off (PPO) bias condition due to the source-connected field plate (SCFP) restricting optical access to the drain side of the gate edge.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"162-168"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/TED.2024.3508670
Ao Zhang;Jianjun Gao
This article presented a novel approach for the modeling of noise behavior for GaAs and InP high-electron-mobility transistors (HEMTs). Closed-form expressions for minimum noise figure ${F}_{min } $ , noise resistance ${R}_{n} $ , optimum source conductance ${G}_{text {opt}} $ , and optimum source susceptance ${B}_{text {opt}} $ based on the noise equivalent circuit model are derived. The model is verified by measurements of the four noise parameters of a GaAs HEMT up to 26 GHz and an InP HEMT up to 40 GHz. The W-band low noise amplifier (LNA) is designed to validate the noise model for HEMT.
{"title":"Comparison of Two Noise Equivalent Circuit Models for GaAs and InP High-Electron-Mobility Transistors","authors":"Ao Zhang;Jianjun Gao","doi":"10.1109/TED.2024.3508670","DOIUrl":"https://doi.org/10.1109/TED.2024.3508670","url":null,"abstract":"This article presented a novel approach for the modeling of noise behavior for GaAs and InP high-electron-mobility transistors (HEMTs). Closed-form expressions for minimum noise figure \u0000<inline-formula> <tex-math>${F}_{min } $ </tex-math></inline-formula>\u0000, noise resistance \u0000<inline-formula> <tex-math>${R}_{n} $ </tex-math></inline-formula>\u0000, optimum source conductance \u0000<inline-formula> <tex-math>${G}_{text {opt}} $ </tex-math></inline-formula>\u0000, and optimum source susceptance \u0000<inline-formula> <tex-math>${B}_{text {opt}} $ </tex-math></inline-formula>\u0000 based on the noise equivalent circuit model are derived. The model is verified by measurements of the four noise parameters of a GaAs HEMT up to 26 GHz and an InP HEMT up to 40 GHz. The W-band low noise amplifier (LNA) is designed to validate the noise model for HEMT.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"154-161"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/TED.2024.3506500
Rajashree Bhattacharya
The insulator-to-metal phase transition oxides offer an opportunity to overcome the current constraints in RF limiter technology. In this article, we present shunt power limiters based on sputtered lanthanum cobalt oxide (LaCoO3, LCO) on silicon carbide substrate. The LCO limiters presented in this article achieve limiting behavior over the broadest temperature range ever reported for an insulator to metal transition (IMT) material-based RF switch, from 10 °C to 225 °C. At 2 GHz, the power limiter provides <1-dB insertion loss up to 75 °C, resilience up to 40 dBm, and leakage power of 20 dBm. S-parameter testing was conducted from 0.1 to 50 GHz, verifying the broadband viability of LCO microwave devices. We present low small signal losses at high temperature and frequency, with a maximum insertion loss of 1.15 dB at 125 °C and 50 GHz. Finally, we report on a 3-D multiphysics model that accurately predicts the LCO RF device behavior and can be used for further device optimization.
{"title":"Wide Bandwidth, High Power Radio Frequency Limiter Based on Lanthanum Cobalt Oxide on SiC","authors":"Rajashree Bhattacharya","doi":"10.1109/TED.2024.3506500","DOIUrl":"https://doi.org/10.1109/TED.2024.3506500","url":null,"abstract":"The insulator-to-metal phase transition oxides offer an opportunity to overcome the current constraints in RF limiter technology. In this article, we present shunt power limiters based on sputtered lanthanum cobalt oxide (LaCoO3, LCO) on silicon carbide substrate. The LCO limiters presented in this article achieve limiting behavior over the broadest temperature range ever reported for an insulator to metal transition (IMT) material-based RF switch, from 10 °C to 225 °C. At 2 GHz, the power limiter provides <1-dB insertion loss up to 75 °C, resilience up to 40 dBm, and leakage power of 20 dBm. S-parameter testing was conducted from 0.1 to 50 GHz, verifying the broadband viability of LCO microwave devices. We present low small signal losses at high temperature and frequency, with a maximum insertion loss of 1.15 dB at 125 °C and 50 GHz. Finally, we report on a 3-D multiphysics model that accurately predicts the LCO RF device behavior and can be used for further device optimization.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"522-528"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/TED.2024.3503533
Yefan Zhang;Shihao Yu;Peng Yang;Xiaopeng Luo;Hui Xu;Xi Wang;Haijun Liu;Sen Liu;Qingjiang Li
In this article, we have designed an optimized ferroelectric tunnel junction (FTJ) device structure that inserts 3-nm Al2O3 between Hf0.5Zr0.5O2 (HZO) films. The Al2O3 interlayer can block the longitudinal growth of HZO grains and increase the number of ferroelectric domains. Therefore, the FTJ devices with Al2O3 interlayer demonstrate amazing multilevel states (256) and ultralow computational power consumption (76.1 pW/bit). In addition, the proposed FTJ device shows high linearity ( $alpha _{text {p}} = -1.262$ ), wide modulation capability, and good reproducibility. The results indicate that the device has high potential in energy-efficient brain-like computing application.
{"title":"Multistates and Ultralow-Power Ferroelectric Tunnel Junction by Inserting Al₂O₃ Interlayer","authors":"Yefan Zhang;Shihao Yu;Peng Yang;Xiaopeng Luo;Hui Xu;Xi Wang;Haijun Liu;Sen Liu;Qingjiang Li","doi":"10.1109/TED.2024.3503533","DOIUrl":"https://doi.org/10.1109/TED.2024.3503533","url":null,"abstract":"In this article, we have designed an optimized ferroelectric tunnel junction (FTJ) device structure that inserts 3-nm Al2O3 between Hf0.5Zr0.5O2 (HZO) films. The Al2O3 interlayer can block the longitudinal growth of HZO grains and increase the number of ferroelectric domains. Therefore, the FTJ devices with Al2O3 interlayer demonstrate amazing multilevel states (256) and ultralow computational power consumption (76.1 pW/bit). In addition, the proposed FTJ device shows high linearity (\u0000<inline-formula> <tex-math>$alpha _{text {p}} = -1.262$ </tex-math></inline-formula>\u0000), wide modulation capability, and good reproducibility. The results indicate that the device has high potential in energy-efficient brain-like computing application.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"228-233"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/TED.2024.3507759
Dmitrii A. Nozhkin;Andrei V. Starodubov;Roman A. Torgashov;Viktor V. Galushka;Ilya O. Kozhevnikov;Alexey A. Serdobintsev;Alexey D. Lebedev;Anton A. Kozyrev;Nikita M. Ryskin
Vacuum electron devices operating at sub-THz frequencies require miniaturized high-frequency electromagnetic interaction structures manufactured using high-precision micromachining technologies. In this article, we present the results of microfabrication of 2-D planar microstrip periodic slow wave structures (SWSs) on dielectric substrate using magnetron sputtering and laser micromachining. A multistage optimized process that allows a substantial improvement of the fabrication accuracy is presented and discussed in detail. A batch of V-band meander-line SWS circuits is fabricated. Characterization of the fabricated structures by optical microscopy and scanning electron microscopy (SEM) demonstrates dimensional deviation less than $5~mu $ m. Experimental investigation of cold-test electromagnetic parameters shows good transmission and reflection characteristics.
{"title":"Laser Micromachining of 2-D Microstrip V-Band Meander-Line Slow Wave Structures","authors":"Dmitrii A. Nozhkin;Andrei V. Starodubov;Roman A. Torgashov;Viktor V. Galushka;Ilya O. Kozhevnikov;Alexey A. Serdobintsev;Alexey D. Lebedev;Anton A. Kozyrev;Nikita M. Ryskin","doi":"10.1109/TED.2024.3507759","DOIUrl":"https://doi.org/10.1109/TED.2024.3507759","url":null,"abstract":"Vacuum electron devices operating at sub-THz frequencies require miniaturized high-frequency electromagnetic interaction structures manufactured using high-precision micromachining technologies. In this article, we present the results of microfabrication of 2-D planar microstrip periodic slow wave structures (SWSs) on dielectric substrate using magnetron sputtering and laser micromachining. A multistage optimized process that allows a substantial improvement of the fabrication accuracy is presented and discussed in detail. A batch of V-band meander-line SWS circuits is fabricated. Characterization of the fabricated structures by optical microscopy and scanning electron microscopy (SEM) demonstrates dimensional deviation less than \u0000<inline-formula> <tex-math>$5~mu $ </tex-math></inline-formula>\u0000m. Experimental investigation of cold-test electromagnetic parameters shows good transmission and reflection characteristics.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"453-458"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/TED.2024.3506504
Jin Chen;Qiang Liu;Yuxin Liu;Zhiqiang Mu;Xing Wei;Wenjie Yu
The excellent tolerance against total ionizing dose (TID) effect and high compatibility with conventional technology nodes has been demonstrated in our previous work with void-embedded-silicon-on-insulator (VESOI) device. However, the presence of embedded void structures within the VESOI devices also introduces additional thermal performance challenges. To address this issue while maintaining the exceptional TID tolerance, we conducted a comprehensive study on the role played by embedded void in blocking both thermal conduction and radiation induced leakage path. Through both pulse I–V tests and systematic simulations, we have revealed the close relationship between the heat sinking capability of VESOI devices and the embedded voids with different structures and dimensions. By applying a nanoscale-embedded chamber extending into the middle channel of VESOI MOSFET, the increase of temperature in the channel is suppressed to a rather low level of 0.3 K. Furthermore, the nano void chamber is also found effective in cutting off radiation-induced leakage paths lying near the bottom channel, resulting in a reduction of the leakage current to $10^{-{11}}~mu $ A/ $mu $ m. This study paves the way for developing more robust and efficient devices based on VESOI technology that can maintain better thermal performance along with TID robustness.
在我们之前的研究中，我们已经证明了该器件对总电离剂量（TID）效应的良好耐受性和与传统技术节点的高兼容性。然而，VESOI器件中嵌入空隙结构的存在也带来了额外的热性能挑战。为了解决这一问题，同时保持特殊的TID容限，我们对嵌入空隙在阻断热传导和辐射诱导泄漏路径中的作用进行了全面的研究。通过脉冲I-V测试和系统模拟，揭示了不同结构和尺寸的嵌入孔洞与VESOI器件的散热能力密切相关。通过在VESOI MOSFET的中间通道中加入纳米级嵌入腔，将通道内的温度升高抑制在0.3 K的较低水平。此外，纳米空腔还被发现可以有效地切断位于底部通道附近的辐射引起的泄漏路径，从而将泄漏电流降低到$10^{-{11}}~mu $ a / $mu $ m。该研究为开发基于VESOI技术的更坚固高效的器件铺平了道路，该器件可以保持更好的热性能和TID鲁棒性。
{"title":"A Novel Approach to Integrating Thermal Performance and Total Ionizing Dose Hardening in Void-Embedded Silicon-on-Insulator MOSFET","authors":"Jin Chen;Qiang Liu;Yuxin Liu;Zhiqiang Mu;Xing Wei;Wenjie Yu","doi":"10.1109/TED.2024.3506504","DOIUrl":"https://doi.org/10.1109/TED.2024.3506504","url":null,"abstract":"The excellent tolerance against total ionizing dose (TID) effect and high compatibility with conventional technology nodes has been demonstrated in our previous work with void-embedded-silicon-on-insulator (VESOI) device. However, the presence of embedded void structures within the VESOI devices also introduces additional thermal performance challenges. To address this issue while maintaining the exceptional TID tolerance, we conducted a comprehensive study on the role played by embedded void in blocking both thermal conduction and radiation induced leakage path. Through both pulse I–V tests and systematic simulations, we have revealed the close relationship between the heat sinking capability of VESOI devices and the embedded voids with different structures and dimensions. By applying a nanoscale-embedded chamber extending into the middle channel of VESOI MOSFET, the increase of temperature in the channel is suppressed to a rather low level of 0.3 K. Furthermore, the nano void chamber is also found effective in cutting off radiation-induced leakage paths lying near the bottom channel, resulting in a reduction of the leakage current to \u0000<inline-formula> <tex-math>$10^{-{11}}~mu $ </tex-math></inline-formula>\u0000A/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m. This study paves the way for developing more robust and efficient devices based on VESOI technology that can maintain better thermal performance along with TID robustness.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"51-56"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/TED.2024.3507758
Jay Sonawane;Shubham Patil;Abhishek Kadam;Ajay Kumar Singh;Sandip Lashkare;Veeresh Deshpande;Udayan Ganguly
Large spiking neural networks (SNNs) require ultralow power and low variability hardware for neuromorphic computing applications. Recently, a band-to-band tunneling (BTBT)-based integrator was proposed, enabling the sub-kHz operation of neurons with area and energy efficiency. For an ultralow-power implementation of such neurons, a very low BTBT current is needed, so minimizing current without degrading neuronal properties is essential. Low variability is needed in the ultralow current integrator to avoid network performance degradation in a large BTBT neuron-based SNN. This work addresses device optimization to achieve low BTBT current. We conducted design space and variability analysis in technology computer-aided design (TCAD), utilizing a well-calibrated TCAD deck with experimental data from GlobalFoundries (GFs) 32 nm partially depleted silicon-on-insulator (PD-SOI) MOSFET. First, we discuss the physics-based explanation of the tunneling mechanism. Second, we explore the impact of device design parameters on SOI MOSFET performance, highlighting parameter sensitivities to tunneling current. With device parameters’ optimization, we demonstrate a $sim 20times $ reduction in BTBT current compared to the experimental data. Finally, a variability analysis that includes the effects of random dopant fluctuations (RDFs), oxide thickness variation (OTV), and channel-oxide interface traps ( ${D} _{text {IT}}$ ) in the BTBT, subthreshold (SS), and ON regimes of operation is shown. The BTBT regime shows the highest sensitivity to OTV, with variability increasing by up to $25times $ compared to the SS regime. In contrast, RDF and ${D} _{text {IT}}$ variability resulted in a $1.25times $ to $sim 10times $ lower coefficient of variation (CV) in the BTBT regime than in the SS regime, indicating better resilience to these sources of variability. The study provides essential design guidelines to enable energy-efficient neuromorphic computing, achieving biologically plausible sub-kHz spiking frequencies.
{"title":"Design Space and Variability Analysis of SOI MOSFET for Ultralow-Power Band-to-Band Tunneling Neurons","authors":"Jay Sonawane;Shubham Patil;Abhishek Kadam;Ajay Kumar Singh;Sandip Lashkare;Veeresh Deshpande;Udayan Ganguly","doi":"10.1109/TED.2024.3507758","DOIUrl":"https://doi.org/10.1109/TED.2024.3507758","url":null,"abstract":"Large spiking neural networks (SNNs) require ultralow power and low variability hardware for neuromorphic computing applications. Recently, a band-to-band tunneling (BTBT)-based integrator was proposed, enabling the sub-kHz operation of neurons with area and energy efficiency. For an ultralow-power implementation of such neurons, a very low BTBT current is needed, so minimizing current without degrading neuronal properties is essential. Low variability is needed in the ultralow current integrator to avoid network performance degradation in a large BTBT neuron-based SNN. This work addresses device optimization to achieve low BTBT current. We conducted design space and variability analysis in technology computer-aided design (TCAD), utilizing a well-calibrated TCAD deck with experimental data from GlobalFoundries (GFs) 32 nm partially depleted silicon-on-insulator (PD-SOI) MOSFET. First, we discuss the physics-based explanation of the tunneling mechanism. Second, we explore the impact of device design parameters on SOI MOSFET performance, highlighting parameter sensitivities to tunneling current. With device parameters’ optimization, we demonstrate a \u0000<inline-formula> <tex-math>$sim 20times $ </tex-math></inline-formula>\u0000 reduction in BTBT current compared to the experimental data. Finally, a variability analysis that includes the effects of random dopant fluctuations (RDFs), oxide thickness variation (OTV), and channel-oxide interface traps (\u0000<inline-formula> <tex-math>${D} _{text {IT}}$ </tex-math></inline-formula>\u0000) in the BTBT, subthreshold (SS), and ON regimes of operation is shown. The BTBT regime shows the highest sensitivity to OTV, with variability increasing by up to \u0000<inline-formula> <tex-math>$25times $ </tex-math></inline-formula>\u0000 compared to the SS regime. In contrast, RDF and \u0000<inline-formula> <tex-math>${D} _{text {IT}}$ </tex-math></inline-formula>\u0000 variability resulted in a \u0000<inline-formula> <tex-math>$1.25times $ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$sim 10times $ </tex-math></inline-formula>\u0000 lower coefficient of variation (CV) in the BTBT regime than in the SS regime, indicating better resilience to these sources of variability. The study provides essential design guidelines to enable energy-efficient neuromorphic computing, achieving biologically plausible sub-kHz spiking frequencies.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"500-506"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an experimental study optimizing a band-engineered gate-stack by incorporating both a tunnel dielectric layer (TDL) and a gate blocking layer (GBL) for ferroelectric (FE) nand flash applications, with a total thickness budget of 18 nm. Using Hf $_{{0}.{5}}$ Zr $_{{0}.{5}}$ O2 (HZO) as the FE material, we explore Al2O3, SiO2, Si3N4, and HfO2 as TDL and GBL materials. By systematically varying the location and thickness of each layer, we investigate their impact on memory window (MW) performance. Our results show that material choice and positioning within the gate-stack are critical, even with constant overall thickness. A hybrid stack using 2-nm Al2O3 and 4-nm SiO2 as TDL and GBL, respectively, results in a maximum MW of 11 V. When Al2O3 and SiO2 are positioned as GBL above the HZO layer, the MW is slightly reduced (>7.5 V), with an increased tetragonal phase. Conversely, MW is significantly reduced when Al2O3 and SiO2 are used as GBL and TDL, respectively, or when both are used as TDL. Further exploration using SiO2, Si3N4, and HfO2 as TDL materials with an SiO2 GBL shows that HfO2 and SiO2 as TDL lead to quad-level cell (QLC)-compatible MW, whereas Si3N4 as TDL leads to very low MW. HfO2 as TDL material leads to most optimized gate-stack with QLC compatibility and lowest operating voltage of all materials. This study underscores the importance of dielectric (DE) material selection and layer positioning within the gate-stack in optimizing the MW of hybrid gate-stacks.
{"title":"Optimizing Memory Window for Ferroelectric Nand Applications: An Experimental Study on Dielectric Material Selection and Layer Positioning","authors":"Lance Fernandes;Prasanna Venkatesan Ravindran;Jiayi Chen;Mengkun Tian;Dipjyoti Das;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan","doi":"10.1109/TED.2024.3504475","DOIUrl":"https://doi.org/10.1109/TED.2024.3504475","url":null,"abstract":"We present an experimental study optimizing a band-engineered gate-stack by incorporating both a tunnel dielectric layer (TDL) and a gate blocking layer (GBL) for ferroelectric (FE) nand flash applications, with a total thickness budget of 18 nm. Using Hf\u0000<inline-formula> <tex-math>$_{{0}.{5}}$ </tex-math></inline-formula>\u0000Zr\u0000<inline-formula> <tex-math>$_{{0}.{5}}$ </tex-math></inline-formula>\u0000O2 (HZO) as the FE material, we explore Al2O3, SiO2, Si3N4, and HfO2 as TDL and GBL materials. By systematically varying the location and thickness of each layer, we investigate their impact on memory window (MW) performance. Our results show that material choice and positioning within the gate-stack are critical, even with constant overall thickness. A hybrid stack using 2-nm Al2O3 and 4-nm SiO2 as TDL and GBL, respectively, results in a maximum MW of 11 V. When Al2O3 and SiO2 are positioned as GBL above the HZO layer, the MW is slightly reduced (>7.5 V), with an increased tetragonal phase. Conversely, MW is significantly reduced when Al2O3 and SiO2 are used as GBL and TDL, respectively, or when both are used as TDL. Further exploration using SiO2, Si3N4, and HfO2 as TDL materials with an SiO2 GBL shows that HfO2 and SiO2 as TDL lead to quad-level cell (QLC)-compatible MW, whereas Si3N4 as TDL leads to very low MW. HfO2 as TDL material leads to most optimized gate-stack with QLC compatibility and lowest operating voltage of all materials. This study underscores the importance of dielectric (DE) material selection and layer positioning within the gate-stack in optimizing the MW of hybrid gate-stacks.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"234-239"},"PeriodicalIF":2.9,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/TED.2024.3508666
Yang Shen;Zhoujie Pan;Mengge Jin;Jintian Gao;Yabin Sun;He Tian;Tian-Ling Ren
Considering that Von Neumann architecture has bottlenecks in both speed and power consumption, in-memory computation is a promising solution. The in-memory computation needs to be carried out in an array composed of storage units, which can be resistive random access memory (RRAM). When using RRAMs, the data storage density can be increased by taking advantage of their multiresistive state characteristics. However, the lack of reliability is a common problem of RRAM, and it is difficult to realize high long range cyclic characteristics purely from the principle. In this work, a new 3-D device based on RRAM is proposed, which is able to realize 2-bit vector multiplication and multibit storage. Analysis and SPICE simulation are conducted to validate the feasibility. The proposed device does not need to join the write-checking process and can greatly promote the improvement of area, storage density, and operation speed, providing a new route for the future in-memory computing. Compared to traditional CMOS circuits used for vector multiplication, our proposed device can achieve 93.75% reduction in terms of number of devices.
{"title":"RRAM-Based Single Device for Vector Multiplication and Multibit Storage With Ultrahigh Area Efficiency","authors":"Yang Shen;Zhoujie Pan;Mengge Jin;Jintian Gao;Yabin Sun;He Tian;Tian-Ling Ren","doi":"10.1109/TED.2024.3508666","DOIUrl":"https://doi.org/10.1109/TED.2024.3508666","url":null,"abstract":"Considering that Von Neumann architecture has bottlenecks in both speed and power consumption, in-memory computation is a promising solution. The in-memory computation needs to be carried out in an array composed of storage units, which can be resistive random access memory (RRAM). When using RRAMs, the data storage density can be increased by taking advantage of their multiresistive state characteristics. However, the lack of reliability is a common problem of RRAM, and it is difficult to realize high long range cyclic characteristics purely from the principle. In this work, a new 3-D device based on RRAM is proposed, which is able to realize 2-bit vector multiplication and multibit storage. Analysis and SPICE simulation are conducted to validate the feasibility. The proposed device does not need to join the write-checking process and can greatly promote the improvement of area, storage density, and operation speed, providing a new route for the future in-memory computing. Compared to traditional CMOS circuits used for vector multiplication, our proposed device can achieve 93.75% reduction in terms of number of devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"266-270"},"PeriodicalIF":2.9,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/TED.2024.3499192
Patrick Fay
{"title":"Thank You to our Reviewers and Editors!","authors":"Patrick Fay","doi":"10.1109/TED.2024.3499192","DOIUrl":"https://doi.org/10.1109/TED.2024.3499192","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7226-7229"},"PeriodicalIF":2.9,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778117","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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