Pub Date : 2022-09-02DOI: 10.1109/lmwc.2022.3198206
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
这些说明提供了为本出版物准备论文的指导方针。为在本期刊上发表文章的作者提供信息。
{"title":"IEEE Microwave and Wireless Components Letters Information for Authors","authors":"","doi":"10.1109/lmwc.2022.3198206","DOIUrl":"https://doi.org/10.1109/lmwc.2022.3198206","url":null,"abstract":"These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"47 1","pages":""},"PeriodicalIF":3.0,"publicationDate":"2022-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138538760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-01DOI: 10.1109/LMWC.2022.3165118
Guixiang Jin, N. Yan, Yue Lin, Hongtao Xu
A 29.5-GHz power amplifier (PA) with a codesigned transformer-based matching network and a second harmonic control network is presented here. The efficiency of the transformer is well studied, and an accurate analytical solution to a high-efficiency transformer has been proposed. Guiding by it, a high-efficiency 1:2 transformer has been designed. A series LC network has been added between the drain and the source as a second harmonic control network. Due to the codesign, the cost of the harmonic control network is negligible. The PA achieves a 3-dB gain bandwidth from 26.9 to 33.2 GHz (21%). The $P_{mathrm {1, dB}}$ exceeds 16.5 dBm with power added efficiency (PAE) beyond 27% from 27.5 to 30 GHz. At 29.5 GHz, the proposed PA achieves a $P_{mathrm {1 ,dB}}$ of 17.4 dBm with 30% PAE1dB and a $P_{mathrm {sat}}$ of 17.8 dBm with the peak PAE of 30.7%.
{"title":"A Linear CMOS Power Amplifier With Efficiency-Optimized Transformer Matching","authors":"Guixiang Jin, N. Yan, Yue Lin, Hongtao Xu","doi":"10.1109/LMWC.2022.3165118","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3165118","url":null,"abstract":"A 29.5-GHz power amplifier (PA) with a codesigned transformer-based matching network and a second harmonic control network is presented here. The efficiency of the transformer is well studied, and an accurate analytical solution to a high-efficiency transformer has been proposed. Guiding by it, a high-efficiency 1:2 transformer has been designed. A series <italic>LC</italic> network has been added between the drain and the source as a second harmonic control network. Due to the codesign, the cost of the harmonic control network is negligible. The PA achieves a 3-dB gain bandwidth from 26.9 to 33.2 GHz (21%). The <inline-formula> <tex-math notation=\"LaTeX\">$P_{mathrm {1, dB}}$ </tex-math></inline-formula> exceeds 16.5 dBm with power added efficiency (PAE) beyond 27% from 27.5 to 30 GHz. At 29.5 GHz, the proposed PA achieves a <inline-formula> <tex-math notation=\"LaTeX\">$P_{mathrm {1 ,dB}}$ </tex-math></inline-formula> of 17.4 dBm with 30% PAE<sub>1dB</sub> and a <inline-formula> <tex-math notation=\"LaTeX\">$P_{mathrm {sat}}$ </tex-math></inline-formula> of 17.8 dBm with the peak PAE of 30.7%.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1059-1062"},"PeriodicalIF":3.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44117368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-01DOI: 10.1109/LMWC.2022.3153326
Yuan Liang, C. Boon, Qian Chen
This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer- $N$ phase-locked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.
{"title":"A 23.4 mW −72-dBc Reference Spur 40 GHz CMOS PLL Featuring a Spur-Compensation Phase Detector","authors":"Yuan Liang, C. Boon, Qian Chen","doi":"10.1109/LMWC.2022.3153326","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3153326","url":null,"abstract":"This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer- $N$ phase-locked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1091-1094"},"PeriodicalIF":3.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43337275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-01DOI: 10.1109/LMWC.2022.3166259
Jingyun Lu, Lina Ma, Changzhan Gu, Junfa Mao
A novel 2.4 GHz passive duplexer with mismatched load impedance and high isolation between transmitting (TX) and receiving (RX) is proposed for integrated sensing and communication (ISAC) applications. By adjusting the impedance of a canceling tuner located between the quadrature coupler and the antenna, the load impedance of the coupler is tactfully mismatched, which reflects a portion of the TX power with the desired amplitude and phase to cancel out the TX/RX leakage to achieve a high TX/RX isolation of >56 dB. In the meantime, by leveraging the quadrature nature of the quadrature coupler, the proposed duplexer makes it possible for the transceiver to operate at dual circularly polarized (CP) mode, which is beneficial for the polarization requirement of ISAC. The proposed duplexer is fully characterized and evaluated in the custom-designed communication and radar sensing systems, and the simulation and experimental results demonstrate the feasibility for ISAC applications.
{"title":"A High-Isolation Duplexer With Mismatched Load Impedance for Integrated Sensing and Communication","authors":"Jingyun Lu, Lina Ma, Changzhan Gu, Junfa Mao","doi":"10.1109/LMWC.2022.3166259","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3166259","url":null,"abstract":"A novel 2.4 GHz passive duplexer with mismatched load impedance and high isolation between transmitting (TX) and receiving (RX) is proposed for integrated sensing and communication (ISAC) applications. By adjusting the impedance of a canceling tuner located between the quadrature coupler and the antenna, the load impedance of the coupler is tactfully mismatched, which reflects a portion of the TX power with the desired amplitude and phase to cancel out the TX/RX leakage to achieve a high TX/RX isolation of >56 dB. In the meantime, by leveraging the quadrature nature of the quadrature coupler, the proposed duplexer makes it possible for the transceiver to operate at dual circularly polarized (CP) mode, which is beneficial for the polarization requirement of ISAC. The proposed duplexer is fully characterized and evaluated in the custom-designed communication and radar sensing systems, and the simulation and experimental results demonstrate the feasibility for ISAC applications.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1127-1130"},"PeriodicalIF":3.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47975149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-01DOI: 10.1109/LMWC.2022.3169066
Joo-Yeol Lee, Songcheol Hong
A wideband common-gate (CG) cascode low-noise amplifier (LNA) is demonstrated with a 28-nm fully depleted silicon on insulator (FDSOI) CMOS process. Wide bandwidth is achieved with a CG structure in the first stage and tightly coupled ( $k=0.86$ ) transmission line transformer (TLT) matching networks. A gm-boosting technique with cross-coupled capacitors improves the gain and noise figure (NF) of the CG amplifier. A high-input 1-dB gain compression point (IP1 dB) can be achieved by introducing an inter-stage inductor at the second-stage cascode amplifier. The LNA shows 19.3 dB gain, 3.1 dB NF, 19.8 GHz (63%) of 3 dB bandwidth, and −15.7 dBm IP1 dB at 28 GHz.
{"title":"A 21–41-GHz Common-Gate LNA With TLT Matching Networks in 28-nm FDSOI CMOS","authors":"Joo-Yeol Lee, Songcheol Hong","doi":"10.1109/LMWC.2022.3169066","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3169066","url":null,"abstract":"A wideband common-gate (CG) cascode low-noise amplifier (LNA) is demonstrated with a 28-nm fully depleted silicon on insulator (FDSOI) CMOS process. Wide bandwidth is achieved with a CG structure in the first stage and tightly coupled ( $k=0.86$ ) transmission line transformer (TLT) matching networks. A gm-boosting technique with cross-coupled capacitors improves the gain and noise figure (NF) of the CG amplifier. A high-input 1-dB gain compression point (IP1 dB) can be achieved by introducing an inter-stage inductor at the second-stage cascode amplifier. The LNA shows 19.3 dB gain, 3.1 dB NF, 19.8 GHz (63%) of 3 dB bandwidth, and −15.7 dBm IP1 dB at 28 GHz.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1051-1054"},"PeriodicalIF":3.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47346884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-01DOI: 10.1109/LMWC.2022.3163788
Kejie Hu, Kaixue Ma, Zonglin Ma
This letter presents an ultra-wideband 20–42 GHz image-reject up-conversion mixer with low dc-power consumption implemented in 55 nm CMOS technology for multiband mm-Wave 5G systems. A sandwich-coupled transformer (SCT) is adopted to expand the operation bandwidth. The proposed SCT demonstrates good performance in enhancing the coupling coefficient and quality factor, which enables wideband impedance matching. Moreover, a quadrature signal generator composed of a transformer and a polyphase filter (PPF) is utilized to generate wideband high-precision I/Q signals without any calibration. With only 24 mW dc-power consumption, the mixer exhibits excellent conversion gain flatness of 1.2±1.5 dB from 20 to 42 GHz. The measured image reject ratio (IRR) is better than −30 dBc within the entire operation band. The measured output 1-dB compression point (OP1 dB) is −2.57 dBm at 28 GHz and −3.96 dBm at 38 GHz. The proposed mixer exhibits good broadband characteristics, which can sustain multiband operation.
{"title":"An Ultra-Wideband Image-Reject Up-Conversion Mixer With a Sandwich-Coupled Transformer for 5G mm-Wave Communication","authors":"Kejie Hu, Kaixue Ma, Zonglin Ma","doi":"10.1109/LMWC.2022.3163788","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3163788","url":null,"abstract":"This letter presents an ultra-wideband 20–42 GHz image-reject up-conversion mixer with low dc-power consumption implemented in 55 nm CMOS technology for multiband mm-Wave 5G systems. A sandwich-coupled transformer (SCT) is adopted to expand the operation bandwidth. The proposed SCT demonstrates good performance in enhancing the coupling coefficient and quality factor, which enables wideband impedance matching. Moreover, a quadrature signal generator composed of a transformer and a polyphase filter (PPF) is utilized to generate wideband high-precision I/Q signals without any calibration. With only 24 mW dc-power consumption, the mixer exhibits excellent conversion gain flatness of 1.2±1.5 dB from 20 to 42 GHz. The measured image reject ratio (IRR) is better than −30 dBc within the entire operation band. The measured output 1-dB compression point (OP1 dB) is −2.57 dBm at 28 GHz and −3.96 dBm at 38 GHz. The proposed mixer exhibits good broadband characteristics, which can sustain multiband operation.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1099-1102"},"PeriodicalIF":3.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43221272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-01DOI: 10.1109/LMWC.2022.3169628
Bo Zhang, Yong Zhang, Chengkai Wu, Tianhao Cao
In this letter, a novel waveguide-to-microstrip vertical transition using a bifurcated probe is presented. The bifurcated probe consists of a pair of thin parallel $E$ -plane probes and bend branches, which forms a strong current crowding effect for electromagnetic energy coupling from rectangular waveguide and broadband impendence matching. Therefore, the bifurcated probe can effectively reduce the sensitivity of probe dimensions to transition performance and design difficulty. To demonstrate this concept, a back-to-back bifurcated probe transition operating at WR-4.3 band (170–260 GHz) was fabricated and measured. Measured results show the double transition covers the entire WR-4.3 band with a minimum return loss (RL) of 16 dB and an average insertion loss (IL) of 0.84 dB, respectively.
{"title":"Millimeter-Wave Broadband Waveguide-to- Microstrip Transition Using a Bifurcated Probe","authors":"Bo Zhang, Yong Zhang, Chengkai Wu, Tianhao Cao","doi":"10.1109/LMWC.2022.3169628","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3169628","url":null,"abstract":"In this letter, a novel waveguide-to-microstrip vertical transition using a bifurcated probe is presented. The bifurcated probe consists of a pair of thin parallel $E$ -plane probes and bend branches, which forms a strong current crowding effect for electromagnetic energy coupling from rectangular waveguide and broadband impendence matching. Therefore, the bifurcated probe can effectively reduce the sensitivity of probe dimensions to transition performance and design difficulty. To demonstrate this concept, a back-to-back bifurcated probe transition operating at WR-4.3 band (170–260 GHz) was fabricated and measured. Measured results show the double transition covers the entire WR-4.3 band with a minimum return loss (RL) of 16 dB and an average insertion loss (IL) of 0.84 dB, respectively.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1031-1034"},"PeriodicalIF":3.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42628961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-01DOI: 10.1109/LMWC.2022.3163462
Ruitao Wang, Chenguang Li, Jian Zhang, S.-D. Yin, Weixing Zhu, Yan Wang
This letter presents a low noise amplifier (LNA) with a 3-dB gain bandwidth (3-dB BW) of 18–44 GHz in 65-nm CMOS technology. By deriving an analytical equation of input impedance, a co-design methodology for the first two stages of LNA that can simultaneously achieve broadband input matching and low noise figure (NF) is implemented. Weakly coupled asymmetric transformers that introduce a section of reverse parallel winding in the primary coil are designed to realize broadband interstage matching, optimize the gain flatness and boost the transconductance. The proposed LNA achieves a measured peak gain of 19.5 dB with a fractional 3-dB gain bandwidth (FBW) of 83.8%, covering the whole $K$ -band and $Ka$ -band. The measured NF is 2.6–3.5 dB from 20 to 43 GHz. To the best of our knowledge, the proposed LNA achieves the highest 3-dB BW and FBW with competitive NF. The measured input 1-dB gain compression point ($text {IP}_{mathrm {1,dB}}$ ) ranges from −23 to −18.5 dBm over the entire 3-dB gain bandwidth.
{"title":"A 18–44 GHz Low Noise Amplifier With Input Matching and Bandwidth Extension Techniques","authors":"Ruitao Wang, Chenguang Li, Jian Zhang, S.-D. Yin, Weixing Zhu, Yan Wang","doi":"10.1109/LMWC.2022.3163462","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3163462","url":null,"abstract":"This letter presents a low noise amplifier (LNA) with a 3-dB gain bandwidth (3-dB BW) of 18–44 GHz in 65-nm CMOS technology. By deriving an analytical equation of input impedance, a co-design methodology for the first two stages of LNA that can simultaneously achieve broadband input matching and low noise figure (NF) is implemented. Weakly coupled asymmetric transformers that introduce a section of reverse parallel winding in the primary coil are designed to realize broadband interstage matching, optimize the gain flatness and boost the transconductance. The proposed LNA achieves a measured peak gain of 19.5 dB with a fractional 3-dB gain bandwidth (FBW) of 83.8%, covering the whole <inline-formula> <tex-math notation=\"LaTeX\">$K$ </tex-math></inline-formula>-band and <inline-formula> <tex-math notation=\"LaTeX\">$Ka$ </tex-math></inline-formula>-band. The measured NF is 2.6–3.5 dB from 20 to 43 GHz. To the best of our knowledge, the proposed LNA achieves the highest 3-dB BW and FBW with competitive NF. The measured input 1-dB gain compression point (<inline-formula> <tex-math notation=\"LaTeX\">$text {IP}_{mathrm {1,dB}}$ </tex-math></inline-formula>) ranges from −23 to −18.5 dBm over the entire 3-dB gain bandwidth.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1083-1086"},"PeriodicalIF":3.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43505943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-01DOI: 10.1109/LMWC.2022.3167988
Chih-Cheng Lin, Shang Hong, S. Hsu
This letter presents a high-speed optical modulator driver with a large output swing in 90-nm CMOS technology. A new topology of cascade swing compensation (CSC) output stage is proposed for protecting the transistors from breakdown using dynamic gate biasing without extra RC networks. To enhance the bandwidth and gain, the active feedback with T-coil peaking and the negative capacitance with series peaking are employed in the preamplifier and main driver, respectively. Under a power consumption of 767 mW, the measured results demonstrate an operating data rate up to 40 Gb/s with a maximum differential output swing of $4.5~V_{mathrm {ppd}}$ obtained at 32 Gb/s.
{"title":"A 40-Gb/s Modulator Driver Using Cascade Swing Compensation in 90 nm CMOS","authors":"Chih-Cheng Lin, Shang Hong, S. Hsu","doi":"10.1109/LMWC.2022.3167988","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3167988","url":null,"abstract":"This letter presents a high-speed optical modulator driver with a large output swing in 90-nm CMOS technology. A new topology of cascade swing compensation (CSC) output stage is proposed for protecting the transistors from breakdown using dynamic gate biasing without extra <italic>RC</italic> networks. To enhance the bandwidth and gain, the active feedback with T-coil peaking and the negative capacitance with series peaking are employed in the preamplifier and main driver, respectively. Under a power consumption of 767 mW, the measured results demonstrate an operating data rate up to 40 Gb/s with a maximum differential output swing of <inline-formula> <tex-math notation=\"LaTeX\">$4.5~V_{mathrm {ppd}}$ </tex-math></inline-formula> obtained at 32 Gb/s.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1103-1106"},"PeriodicalIF":3.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43287089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-01DOI: 10.1109/LMWC.2022.3161152
Shifeng Li, Lijun Ma, Leiyang Wang, Xiao Lei, Bang Wu, G. Cheng, Feng Liu
Herein, based on a rounded rectangle p-i-n diode with the minimum radius allowed by the process and a 0.8- $boldsymbol {mu }mathbf {m}$ thick I-layer, a high-power wideband monolithic limiter was realized by using GaAs p-i-n process. At 16 GHz, the maximum handling power of the monolithic limiter is up to 400 W (56 dBm), while the output power is less than 45 mW (16.5 dBm). Meantime, the insertion loss of the limiter is less than 0.55 dB and the return loss is better than −15 dB in the frequency range of 10–18 GHz, which has little effect on the signal of the receiver. It demonstrates that the limiter has a significant potential in high-frequency and high-power phased-array radars and communication systems.
{"title":"High Power 10–18 GHz Monolithic Limiter Based on GaAs p-i-n Technology","authors":"Shifeng Li, Lijun Ma, Leiyang Wang, Xiao Lei, Bang Wu, G. Cheng, Feng Liu","doi":"10.1109/LMWC.2022.3161152","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3161152","url":null,"abstract":"Herein, based on a rounded rectangle p-i-n diode with the minimum radius allowed by the process and a 0.8- $boldsymbol {mu }mathbf {m}$ thick I-layer, a high-power wideband monolithic limiter was realized by using GaAs p-i-n process. At 16 GHz, the maximum handling power of the monolithic limiter is up to 400 W (56 dBm), while the output power is less than 45 mW (16.5 dBm). Meantime, the insertion loss of the limiter is less than 0.55 dB and the return loss is better than −15 dB in the frequency range of 10–18 GHz, which has little effect on the signal of the receiver. It demonstrates that the limiter has a significant potential in high-frequency and high-power phased-array radars and communication systems.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1107-1110"},"PeriodicalIF":3.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45270560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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