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Miniaturized Dual-Band Filter Using Dual-Mode Dielectric Waveguide Resonator 采用双模介质波导谐振器的小型双频带滤波器
IF 3 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2022-12-01 DOI: 10.1109/LMWC.2022.3193424
Zuo Xu, Yongle Wu, Qingxiang Dong, Weimin Wang
This letter presents a novel miniaturized dual-band bandpass filter (BPF) using a dual-mode dielectric waveguide resonator (DWR). The DWR is a cylinder dielectric block with the surface being silver-coated. The two modes are TM010 and TM011 modes, which are used to construct the two passbands. The frequency of them can be adjusted by changing the radius and the height of the cylinder DWR and the frequency space can be controlled independently. The BPF is composed of three cylindrical cavities, which are arranged in an equilateral triangle. The three cavities construct a cascaded trisection (CT) unit, which creates a transmission zero (TZ) at the upper side of the two passbands. Finally, a dual-band BPF using DWR is simulated, manufactured, and measured to exhibit the feasibility of the proposed design. Their results are in good agreement, showing good performance, such as miniaturization, good return loss (RL), and upper stopband selectivity.
本文介绍了一种新型的小型化双频带通滤波器(BPF),该滤波器使用双模介质波导谐振器(DWR)。DWR是一种表面镀银的圆柱体电介质块。这两种模式是TM010和TM011模式,用于构建两个通带。可以通过改变圆柱体DWR的半径和高度来调节它们的频率,并且可以独立地控制频率空间。BPF由三个圆柱形空腔组成,这些空腔排列成等边三角形。三个腔构成级联三段(CT)单元,在两个通带的上侧产生传输零点(TZ)。最后,模拟、制造和测量了一个使用DWR的双频带BPF,以展示所提出设计的可行性。它们的结果一致,显示出良好的性能,如小型化、良好的回波损耗(RL)和上阻带选择性。
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引用次数: 7
A 39-GHz Phase-Inverting Variable Gain Power Amplifier in 65-nm CMOS for 5G Communication 用于5G通信的65纳米CMOS 39 ghz反相变增益功率放大器
IF 3 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2022-11-01 DOI: 10.1109/LMWC.2022.3180999
Xuexue Zhang, Xiaokang Niu, Qin Chen, Xin Chen, Depeng Cheng, Jing Feng, Jun Feng, Lianming Li
This letter presents a 39-GHz phase-inverting variable gain power amplifier (VGPA) for 5G communication. Adopting a Gilbert structure-based variable gain amplifier (VGA) stage, the VGPA realized the dB-linear gain control characteristic as well as 180° phase inversion. At 0°/180° phase states, the 39-GHz VGPA achieves the maximum gain of 38.7/38.9 dB with gain tuning range of 5.6/5.2 dB, respectively. Over 38–43 GHz, the phase inversion error is limited within 5.9°, and the rms phase error is less than 3.6°/2.2°. Meanwhile, with the metal interleaving coplanar transformer matching network, this VGPA achieves 17.7/17.6-dBm Psat and 13.2/13.36-dBm OP1 dB, with the power added efficiency (PAE) of 35%/34.5% and 13.6%/14.4% at the saturation and 1-dB compression points, respectively. Over the gain control states, the OP1 dB fluctuation is less than 0.3 dB. Implemented in a 65-nm CMOS process, the proposed VGPA consumes 150 mW with a chip area of 0.3 mm2.
这封信介绍了一种用于5G通信的39 ghz逆变变增益功率放大器(VGPA)。VGPA采用基于Gilbert结构的可变增益放大器(VGA)级,实现了db线性增益控制特性和180°相位反转。在0°/180°相位状态下,39 ghz VGPA的最大增益分别为38.7/38.9 dB,增益调谐范围为5.6/5.2 dB。在38 ~ 43 GHz范围内,相位反转误差控制在5.9°以内,均方根相位误差小于3.6°/2.2°。同时,在金属交错共面变压器匹配网络下,该VGPA在饱和和1db压缩点分别达到17.7/17.6 dbm Psat和13.2/13.36 dbm OP1 dB,功率附加效率(PAE)分别为35%/34.5%和13.6%/14.4%。在增益控制状态下,OP1 dB波动小于0.3 dB。该VGPA采用65纳米CMOS工艺,功耗为150mw,芯片面积为0.3 mm2。
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引用次数: 1
A Coaxial to Air-Filled Substrate Integrated Waveguide Transition With Near-Octave Bandwidth 近倍频宽的同轴到充气基板集成波导跃迁
IF 3 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2022-11-01 DOI: 10.1109/LMWC.2022.3179641
S. Choudhury, A. Mohan, M. Bozzi
In this letter, a wideband coaxial to air-filled waveguide transition is proposed, which has been realized by the substrate integrated waveguide (SIW) technology. The present design incorporates several air-filled vias of varying hole diameter to efficiently match the impedance over a wide operating bandwidth in the dominant TE10 mode, hence replacing the need for dielectric taper or larger footprint. A transition prototype has been designed and tested to validate the results. The measured return loss is better than 15 dB and insertion loss of 1 ± 0.1 dB over the band of interest (9.5–15 GHz), hence portraying a near-octave bandwidth from the proposed design.
在这封信中,提出了一个宽带同轴到充气波导的过渡,这是由衬底集成波导(SIW)技术实现的。目前的设计包含了几个不同孔径的充气通孔,以有效地匹配主要TE10模式下宽工作带宽上的阻抗,从而取代了对介电锥度或更大占地面积的需求。设计并测试了一个转换原型以验证结果。在目标频段(9.5-15 GHz)上,测量到的回波损耗优于15 dB,插入损耗为1±0.1 dB,因此描述了所提出设计的近倍频程带宽。
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引用次数: 0
A Tangent Approximation Coefficient Extraction Method for Instantaneous Sample Indexed Magnitude-Selective Affine Behavioral Model 一种瞬时样本索引幅度选择仿射行为模型的切线近似系数提取方法
IF 3 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2022-11-01 DOI: 10.1109/LMWC.2022.3186036
Zhuang Xu, Jianfeng Zhai, Kai Wang, Jiawen Liu, Xuefa Zhai, Yan Guo, Chao Yu
The coefficients of digital predistortion (DPD) models are often extracted by the least square (LS) method, which has high computational complexity because of the operations of the large matrix. In this letter, a low complexity coefficient extraction method for instantaneous sample indexed magnitude-selective affine (I-MSA) model is proposed. The proposed method uses the tangent of the midpoint of the piecewise function to fit the curve. Therefore, the LS coefficient extraction only needs a small amount of data near the midpoint, rather than using all the data in the segmented region. Simulation and experimental results have confirmed that compared with the original LS method, the proposed method has similar modeling accuracy and linearization performance, but the computational complexity of coefficient extraction is greatly reduced.
数字预失真(DPD)模型的系数通常采用最小二乘法提取,由于矩阵运算量大,最小二乘法具有较高的计算复杂度。本文提出了一种用于瞬时样本索引幅度选择性仿射(I-MSA)模型的低复杂度系数提取方法。所提出的方法使用分段函数中点的切线来拟合曲线。因此,LS系数提取只需要中点附近的少量数据,而不需要使用分割区域中的所有数据。仿真和实验结果表明,与原来的LS方法相比,该方法具有相似的建模精度和线性化性能,但大大降低了系数提取的计算复杂度。
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引用次数: 0
A 2-Bit Voltage-Controlled Oscillator (VCO) for Multiband Wireless Applications 用于多波段无线应用的2位压控振荡器(VCO)
IF 3 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2022-11-01 DOI: 10.1109/LMWC.2022.3182020
S. Hamidi, D. Dawn
This letter presents a fully-integrated 2-bit CMOS voltage-controlled oscillator (VCO) along with a 2-bit buffer, which delivers the highest RF output power among recently reported state-of-the-art to the best of the authors’ knowledge. The proposed 2-bit VCO is designed and fabricated in a $0.18-mu text{m}$ CMOS process with a die size of 1.2 mm $times$ 1.2 mm, which covers four frequency bands of interest. Fine-tuning at each of the four frequency bands is also obtained by utilizing two varactors. The proposed 2-bit VCO delivers a single-ended output power of 6.5/6.8/10.6/12.5 dBm at 0.930/1.157/1.436/1.917 GHz, respectively. This 2-bit VCO can cover frequency ranges of 930–1005, 1046–1157, 1248–1436, and 1540–1917 MHz, thus providing a total frequency bandwidth of 751 MHz. The proposed 2-bit VCO at each frequency band demonstrates −99, −93, −90, and −86 dBc/Hz for phase noise, and −150, −150, −160, and −168 dBc/Hz for figure-of-merit (FOM), respectively.
这封信介绍了一个完全集成的2位CMOS压控振荡器(VCO)和一个2位缓冲器,据作者所知,它在最近报道的最先进的技术中提供了最高的RF输出功率。所提出的2位VCO是在$0.18-mu text{m}$ CMOS工艺中设计和制造的,其芯片尺寸为$ 1.2 mm $ × $ 1.2 mm,涵盖了四个感兴趣的频段。在每个四个频段的微调也得到了利用两个变容器。所提出的2位VCO在0.930/1.157/1.436/1.917 GHz时的单端输出功率分别为6.5/6.8/10.6/12.5 dBm。这个2位VCO可以覆盖930-1005、1046-1157、1248-1436和1540-1917 MHz的频率范围,从而提供751 MHz的总频率带宽。所提出的2位VCO在每个频段的相位噪声分别为- 99、- 93、- 90和- 86 dBc/Hz,品质因数(FOM)分别为- 150、- 150、- 160和- 168 dBc/Hz。
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引用次数: 1
A 208–233-GHz Frequency Doubler With 1.1% Power-Added Efficiency in 28-nm CMOS 208–233 GHz倍频器,在28 nm CMOS中具有1.1%的功率添加效率
IF 3 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2022-11-01 DOI: 10.1109/LMWC.2022.3180082
Hai-Hong Fu, Kai Li, Kaixue Ma
This letter presents a fully integrated frequency doubler in the TSMC 28-nm CMOS technology. MOS transistor capacitor neutralization is introduced in the differential driving amplifier, which shows better robustness than MOM capacitor neutralization under PVT variations. Besides, a stacked transformer-based balun is designed to achieve good balance performance. The effect of dummy metal on the performance of the proposed balun is also discussed. The measured results show that the 3-dB bandwidth is 25 GHz (208–233 GHz) and the peak power-added efficiency is 1.1% with a dc power consumption of 26.4 mW at 222 GHz. The peak conversion gain is −7.2 dB and the variation in conversion gain is less than 1 dB within −7- to 1-dBm input power range. Moreover, the chip size is $492times 412,,mu text{m}^{2}$ , including GSG and DC pads.
这封信介绍了台积电28纳米CMOS技术中的完全集成倍频器。在差分驱动放大器中引入MOS晶体管电容器中和,在PVT变化下表现出比MOM电容器中和更好的鲁棒性。此外,设计了一种基于堆叠变压器的巴伦,以实现良好的平衡性能。还讨论了虚设金属对所提出的巴伦性能的影响。测量结果表明,3dB带宽为25 GHz(208–233 GHz),峰值功率增加效率为1.1%,222 GHz下的直流功耗为26.4 mW。峰值转换增益为−7.2 dB,在−7至1-dBm输入功率范围内,转换增益的变化小于1 dB。此外,芯片尺寸为$492×412,,mutext{m}^{2}$,包括GSG和DC焊盘。
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引用次数: 1
5.85-mW 3.1–23.7-GHz Two-Stage CMOS VGA With 2.53-dB NF Using Concurrent Current Steering 5.85 mw 3.1 - 23.7 ghz两级CMOS VGA与2.53 db NF使用并发电流转向
IF 3 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2022-11-01 DOI: 10.1109/LMWC.2022.3189593
Jin-Fa Chang, Yo‐Sheng Lin
A low-power and low noise-figure (NF) 3.1–23.7-GHz CMOS variable-gain amplifier (VGA) is presented. The VGA composes of a complimentary common-source (CCS) first stage, followed by a common-source (CS) second stage. Low power and NF and wideband $S_{11}$ and $S_{21}$ are achieved due to the current-reused CCS input stage with multiple inductive impedance matching and gain compensation. A large gain tuning range (with low NF) is achieved due to the concurrent gate–voltage tuning (or current steering) of the first and the second stages. The VGA consumes 5.85 mW (at $V_{mathrm {ctrl}}$ of 1 V) and achieves excellent 3-dB bandwidth ( $f_{3,mathrm {dB}}$ ) of 20.6 GHz (3.1–23.7 GHz), maximum $S_{21}$ of 11.9 dB, minimum NF (NFmin) of 2.53 dB, average NF (NFavg) of 3.97 dB, small group delay (GD) variation of ±16.5 ps, and input third-order intercept point (IIP3) of −6.5 dBm. Moreover, the VGA achieves a decent gain tuning range of 23.4 dB (−5.4 to 18 dB) for $V_{mathrm {ctrl}}$ of 0.6–1.6 V. The chip area is 0.364 mm2.
介绍了一种低功耗低噪声系数(NF)3.1–23.7-GHz CMOS可变增益放大器(VGA)。VGA由互补公共源(CCS)第一级和公共源(CS)第二级组成。由于具有多重电感阻抗匹配和增益补偿的电流复用CCS输入级,实现了低功率和NF以及宽带$S{11}$和$S{21}$。由于第一级和第二级同时进行栅极电压调谐(或电流控制),实现了大的增益调谐范围(具有低NF)。VGA消耗5.85 mW(在1V的$V_{mathrm{ctrl}}$下),并实现了20.6 GHz(3.1–23.7 GHz)的出色的3dB带宽($f_{3,mathrm}dB}$)、11.9 dB的最大$S_{21}$、2.53 dB的最小NF(NFmin)、3.97 dB的平均NF(NFavg)、±16.5 ps的小组延迟(GD)变化和−6.5 dBm的输入三阶截距点(IIP3)。此外,对于0.6–1.6 V的$V_{mathrm{ctrl}}$,VGA实现了23.4 dB(−5.4至18 dB)的良好增益调谐范围。芯片面积为0.364 mm2。
{"title":"5.85-mW 3.1–23.7-GHz Two-Stage CMOS VGA With 2.53-dB NF Using Concurrent Current Steering","authors":"Jin-Fa Chang, Yo‐Sheng Lin","doi":"10.1109/LMWC.2022.3189593","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3189593","url":null,"abstract":"A low-power and low noise-figure (NF) 3.1–23.7-GHz CMOS variable-gain amplifier (VGA) is presented. The VGA composes of a complimentary common-source (CCS) first stage, followed by a common-source (CS) second stage. Low power and NF and wideband <inline-formula> <tex-math notation=\"LaTeX\">$S_{11}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation=\"LaTeX\">$S_{21}$ </tex-math></inline-formula> are achieved due to the current-reused CCS input stage with multiple inductive impedance matching and gain compensation. A large gain tuning range (with low NF) is achieved due to the concurrent gate–voltage tuning (or current steering) of the first and the second stages. The VGA consumes 5.85 mW (at <inline-formula> <tex-math notation=\"LaTeX\">$V_{mathrm {ctrl}}$ </tex-math></inline-formula> of 1 V) and achieves excellent 3-dB bandwidth (<inline-formula> <tex-math notation=\"LaTeX\">$f_{3,mathrm {dB}}$ </tex-math></inline-formula>) of 20.6 GHz (3.1–23.7 GHz), maximum <inline-formula> <tex-math notation=\"LaTeX\">$S_{21}$ </tex-math></inline-formula> of 11.9 dB, minimum NF (NFmin) of 2.53 dB, average NF (NFavg) of 3.97 dB, small group delay (GD) variation of ±16.5 ps, and input third-order intercept point (IIP3) of −6.5 dBm. Moreover, the VGA achieves a decent gain tuning range of 23.4 dB (−5.4 to 18 dB) for <inline-formula> <tex-math notation=\"LaTeX\">$V_{mathrm {ctrl}}$ </tex-math></inline-formula> of 0.6–1.6 V. The chip area is 0.364 mm2.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1331-1334"},"PeriodicalIF":3.0,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48509057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Compact Wide-Range Frequency and Bandwidth Reconfigurable Filter 一种紧凑型宽频带可重构滤波器
IF 3 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2022-11-01 DOI: 10.1109/LMWC.2022.3178722
Mingen Tian, Zhihe Long, Lijun Feng, Leilei He, Tianliang Zhang
This letter proposes a wide-range reconfigurable bandpass filter (WRBPF) based on the cross-shape triple-mode resonator. Varactor diodes and switching diodes are utilized at the ends of the resonator and the positions of external coupling, which combines the two working modes of the low-frequency band and high-frequency band, greatly broaden the tunable range of the center frequency ( $f_{0}$ ). When the 3-dB bandwidth of WRBPF is 180 MHz, $f_{0}$ can be adjusted from 0.78 to 1.93 GHz, and the relative adjustment range is 84.9%. When $f_{0}$ is 1.355 GHz, the absolute bandwidth can be adjusted from 110 to 950 MHz, and the relative bandwidth adjustment range is 8.1%–70.1%. Moreover, the circuit size of WRBPF is only $0.29,,lambda g,,times 0.22,,lambda g$ . The experimental results show that WRBPF has not only a simple structure but also an excellent performance.
本文提出了一种基于十字形三模谐振器的宽范围可重构带通滤波器(WRBPF)。在谐振器的两端和外部耦合的位置使用了变容二极管和开关二极管,它结合了低频带和高频带的两种工作模式,极大地拓宽了中心频率($f_{0}$)的可调谐范围。当WRBPF的3dB带宽为180MHz时,$f_{0}$可以从0.78调整到1.93GHz,相对调整范围为84.9%。当$f_{0}$为1.355GHz时,绝对带宽可以从110调整到950MHz,相对带宽调整范围为8.1%-70.1%。此外,WRBPF电路尺寸仅为$0.29,,lambda g,、times 0.22,和lambda g$。实验结果表明,WRBPF不仅结构简单,而且性能优异。
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引用次数: 1
Frequency Division Multiplexer With Directional Filters in Multilayer LCP Films at - and -Band 带和带多层LCP膜带方向滤波器的频分复用器
IF 3 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2022-11-01 DOI: 10.1109/LMWC.2022.3177606
Mengfa Wang, Baoqing Zhang, Zhaolin Li, Yiming Wang, Qinglei Guo, Weihong Liu, Y. Yashchyshyn, Aimin Song, Yifei Zhang
A quasi-reflectionless frequency division multiplexer (FDM) with directional filters (DFs) in multilayer liquid crystal polymer (LCP) substrates is proposed for $E$ - and $W$ -band applications. The in-series cascaded DFs are designed at 74, 84, and 94 GHz, each of which comprises two microstrip lines in the first layer, two pairs of coupling slots in the second layer, and loop resonators in the third layer. The distance between DFs is optimized for suppressing reflection and insertion losses, and the asymmetric distribution of DFs is designed to obtain a low profile. The experimental data demonstrate a 3-dB passband of 8.3%, 8.8%, and 9.7% centered at 74, 84, and 94 GHz, respectively, for the proposed FDM, showing a good match with the simulation. The corresponding insertion loss is measured as 3.63, 3.4, and 2.72 dB at 74, 84, and 94 GHz, respectively. The proposed device may find many applications in multiband and ultrawideband communication and radar systems.
提出了一种在多层液晶聚合物(LCP)衬底上具有定向滤波器的准无反射频分复用器(FDM),用于$E$和$W$波段。串联级联df设计在74,84和94 GHz,每个df由第一层的两条微带线,第二层的两对耦合槽和第三层的环路谐振器组成。优化了df之间的距离以抑制反射和插入损耗,设计了df的不对称分布以获得低轮廓。实验数据表明,所提出的FDM在74 GHz、84 GHz和94 GHz的通频带分别为8.3%、8.8%和9.7%,与仿真结果吻合较好。相应的插入损耗在74、84和94 GHz时分别为3.63、3.4和2.72 dB。该器件在多波段、超宽带通信和雷达系统中具有广泛的应用前景。
{"title":"Frequency Division Multiplexer With Directional Filters in Multilayer LCP Films at - and -Band","authors":"Mengfa Wang, Baoqing Zhang, Zhaolin Li, Yiming Wang, Qinglei Guo, Weihong Liu, Y. Yashchyshyn, Aimin Song, Yifei Zhang","doi":"10.1109/LMWC.2022.3177606","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3177606","url":null,"abstract":"A quasi-reflectionless frequency division multiplexer (FDM) with directional filters (DFs) in multilayer liquid crystal polymer (LCP) substrates is proposed for <inline-formula> <tex-math notation=\"LaTeX\">$E$ </tex-math></inline-formula>- and <inline-formula> <tex-math notation=\"LaTeX\">$W$ </tex-math></inline-formula>-band applications. The in-series cascaded DFs are designed at 74, 84, and 94 GHz, each of which comprises two microstrip lines in the first layer, two pairs of coupling slots in the second layer, and loop resonators in the third layer. The distance between DFs is optimized for suppressing reflection and insertion losses, and the asymmetric distribution of DFs is designed to obtain a low profile. The experimental data demonstrate a 3-dB passband of 8.3%, 8.8%, and 9.7% centered at 74, 84, and 94 GHz, respectively, for the proposed FDM, showing a good match with the simulation. The corresponding insertion loss is measured as 3.63, 3.4, and 2.72 dB at 74, 84, and 94 GHz, respectively. The proposed device may find many applications in multiband and ultrawideband communication and radar systems.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"21 2","pages":"1287-1290"},"PeriodicalIF":3.0,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41306191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Resolution Direct Digital Synthesis Transmitter Architecture Using Dithering for Multiband 5G NR Mobile Applications 一种用于多频带5G NR移动应用的低分辨率直接数字合成发射机结构
IF 3 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2022-11-01 DOI: 10.1109/LMWC.2022.3182662
You-Huei Chen, Shu-Chen Lin, Jui-Hsin Hung, Hao-Shun Yang, Jau-Horng Chen, Y. Chen
This letter presents a low-resolution multiband transmitter architecture using direct digital synthesis (DDS) with dithering. Modern modulated signals constructed by a low-resolution digital-to-analog converter (DAC) suffer from quantization errors and distortions. The proposed technique reduces the quantization problems with the use of a proper oversampling ratio (OSR) and the dithering technique. This technique has lower cost and lower complexity compared to conventional transmitters while maintaining linearity performance. A 50-MHz 5G NR 256-quadratic-amplitude modulation (QAM) signal is used for concept validation at bands n1, n40, and n50. The proposed work achieved the adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of under −30 dBc and 3.5%, respectively. A single 3-bit 10-GS/s radio frequency (RF) DAC is used where the performance is similar to a conventional transmitter using a pair of 5-bit baseband in-phase and quadrature (IQ) DACs.
这封信介绍了一种使用带抖动的直接数字合成(DDS)的低分辨率多频带发射机结构。由低分辨率数模转换器(DAC)构造的现代调制信号遭受量化误差和失真。所提出的技术通过使用适当的过采样率(OSR)和抖动技术来减少量化问题。与传统发射机相比,该技术具有更低的成本和更低的复杂性,同时保持线性性能。50MHz 5G NR 256二次幅度调制(QAM)信号用于频带n1、n40和n50的概念验证。所提出的工作分别实现了−30 dBc和3.5%以下的相邻信道泄漏率(ACLR)和误差矢量幅度(EVM)要求。使用单个3比特10-GS/s射频(RF)DAC,其中性能类似于使用一对5比特基带同相和正交(IQ)DAC的传统发射机。
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引用次数: 0
期刊
IEEE Microwave and Wireless Components Letters
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