Pub Date : 2022-12-01DOI: 10.1109/LMWC.2022.3193722
M. Baranowski, Łukasz Balewski, A. Lamecki, M. Mrozowski, J. Galdeano
This letter presents a novel design for a 3-D-printed circular waveguide dual-mode (CWDM) filter with a modified cavity shape. The modification leads to a wide spurious-free stopband, which is highly desirable for channel separation in waveguide contiguous output multiplexers (OMUXs) in satellite communication systems. The new resonant cavity design is a result of applying shape deformation to a basic circular cavity in order to move away and suppress parasitic modes. A fourth-order Ku-band channel filter with two transmission zeros (TZs) is designed, fabricated by additive manufacturing (AM) in one piece and measured. In comparison with the state-of-the-art design of a stepped CWDM filter, an improvement of approximately 35% wider spurious-free range is achieved.
{"title":"A Circular Waveguide Dual-Mode Filter With Improved Out-of-Band Performance for Satellite Communication Systems","authors":"M. Baranowski, Łukasz Balewski, A. Lamecki, M. Mrozowski, J. Galdeano","doi":"10.1109/LMWC.2022.3193722","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3193722","url":null,"abstract":"This letter presents a novel design for a 3-D-printed circular waveguide dual-mode (CWDM) filter with a modified cavity shape. The modification leads to a wide spurious-free stopband, which is highly desirable for channel separation in waveguide contiguous output multiplexers (OMUXs) in satellite communication systems. The new resonant cavity design is a result of applying shape deformation to a basic circular cavity in order to move away and suppress parasitic modes. A fourth-order Ku-band channel filter with two transmission zeros (TZs) is designed, fabricated by additive manufacturing (AM) in one piece and measured. In comparison with the state-of-the-art design of a stepped CWDM filter, an improvement of approximately 35% wider spurious-free range is achieved.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1403-1406"},"PeriodicalIF":3.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44794875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/LMWC.2022.3184044
Gui-Ying Liu, Wei‐Jun Chen, Jun Quan
Based on an auxiliary differential equation (ADE) and a new temporal basis function, we propose a 3-D ADE finite-difference time-domain method (FDTD) with weighted Laguerre polynomials (WLPs), 3-D ADE-WLP-FDTD for short, to calculate wave propagation in general dispersive materials. Our proposed method introduces a linear combination of three WLPs as a temporal basis to improve computational efficiency and reduce memory usage. The ADE technique, which can effectively model dispersive media, was used to establish the relationship between the electric displacement vector and electric field intensity. Two numerical examples were presented to validate the advantages of the proposed approach. The simulation results reveal that compared with the conventional ADE-WLP-FDTD method, the proposed method can speed up the computational process and reduce memory usage with comparable accuracy.
{"title":"A General ADE-WLP-FDTD Method With a New Temporal Basis for Wave Propagation","authors":"Gui-Ying Liu, Wei‐Jun Chen, Jun Quan","doi":"10.1109/LMWC.2022.3184044","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3184044","url":null,"abstract":"Based on an auxiliary differential equation (ADE) and a new temporal basis function, we propose a 3-D ADE finite-difference time-domain method (FDTD) with weighted Laguerre polynomials (WLPs), 3-D ADE-WLP-FDTD for short, to calculate wave propagation in general dispersive materials. Our proposed method introduces a linear combination of three WLPs as a temporal basis to improve computational efficiency and reduce memory usage. The ADE technique, which can effectively model dispersive media, was used to establish the relationship between the electric displacement vector and electric field intensity. Two numerical examples were presented to validate the advantages of the proposed approach. The simulation results reveal that compared with the conventional ADE-WLP-FDTD method, the proposed method can speed up the computational process and reduce memory usage with comparable accuracy.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1391-1394"},"PeriodicalIF":3.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43252993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, a 10–43-GHz low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) is designed in a commercial 0.15-$mu text{m}$ GaAs E-mode pseudomorphic high electron mobility transistor (pHEMT) technology. In the proposed LNA circuit, a novel coupled-line (CL)-based positive feedback structure is employed with the bandpass characteristic. By carefully tuning its coupling factor and arm length, the center frequency $f_{c}$ and the intensity of the feedback can be controlled, respectively. Subsequently, targeting $f_{c}$ at the higher cutting edge of the working band leads to compensated gain roll-off and extended bandwidth. Incorporating three-stage common-source (CS) architectures, an LNA prototype is fabricated with a size of 1.05 mm2 including pads. Under 2-V voltage drain drain (VDD), good performance is obtained, including 24.6-dB peak gain with 3-dB bandwidth of 33 GHz, 2.4–3.0-dB noise figure (NF), 54.5 ± 13.8-ps group delay, and 12.3/21.5-dBm best output power at 1 dB gain compression (OP1dB)/output third order intercept point (OIP3). The total dc power is 110 mW.
{"title":"A Broadband 10–43-GHz High-Gain LNA MMIC Using Coupled-Line Feedback in 0.15-μm GaAs pHEMT Technology","authors":"Xu Yan, Pengyu Yu, Jingyuan Zhang, Siping Gao, Yongxin Guo","doi":"10.1109/LMWC.2022.3193007","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3193007","url":null,"abstract":"In this letter, a 10–43-GHz low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) is designed in a commercial 0.15-<inline-formula> <tex-math notation=\"LaTeX\">$mu text{m}$ </tex-math></inline-formula> GaAs E-mode pseudomorphic high electron mobility transistor (pHEMT) technology. In the proposed LNA circuit, a novel coupled-line (CL)-based positive feedback structure is employed with the bandpass characteristic. By carefully tuning its coupling factor and arm length, the center frequency <inline-formula> <tex-math notation=\"LaTeX\">$f_{c}$ </tex-math></inline-formula> and the intensity of the feedback can be controlled, respectively. Subsequently, targeting <inline-formula> <tex-math notation=\"LaTeX\">$f_{c}$ </tex-math></inline-formula> at the higher cutting edge of the working band leads to compensated gain roll-off and extended bandwidth. Incorporating three-stage common-source (CS) architectures, an LNA prototype is fabricated with a size of 1.05 mm2 including pads. Under 2-V voltage drain drain (VDD), good performance is obtained, including 24.6-dB peak gain with 3-dB bandwidth of 33 GHz, 2.4–3.0-dB noise figure (NF), 54.5 ± 13.8-ps group delay, and 12.3/21.5-dBm best output power at 1 dB gain compression (OP1dB)/output third order intercept point (OIP3). The total dc power is 110 mW.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1459-1462"},"PeriodicalIF":3.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41450969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/LMWC.2022.3186406
Ping Zhao
This letter proposes a direct matrix synthesis approach for filters with cascaded extracted-pole (EP) sections. The novel synthesis technique is based on the observation that an EP section is a special case of a singlet with a zero mainline coupling. With proper phase lengths inserted into a cross-coupled network, cascaded EP sections can be directly synthesized from the canonical wheel form by a sequence of elementary matrix operations. In this letter, the equation for the suitable phaselength is derived, and the matrix transformation strategy to synthesize cascaded EP sections is developed. Numerical synthesis examples are provided to validate the novel synthesis approach.
{"title":"Matrix Synthesis for Filters With Cascaded Extracted-Pole Sections","authors":"Ping Zhao","doi":"10.1109/LMWC.2022.3186406","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3186406","url":null,"abstract":"This letter proposes a direct matrix synthesis approach for filters with cascaded extracted-pole (EP) sections. The novel synthesis technique is based on the observation that an EP section is a special case of a singlet with a zero mainline coupling. With proper phase lengths inserted into a cross-coupled network, cascaded EP sections can be directly synthesized from the canonical wheel form by a sequence of elementary matrix operations. In this letter, the equation for the suitable phaselength is derived, and the matrix transformation strategy to synthesize cascaded EP sections is developed. Numerical synthesis examples are provided to validate the novel synthesis approach.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1383-1386"},"PeriodicalIF":3.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44507235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/LMWC.2022.3189401
Ankit Kumar Pandey, A. K. Saxena
In this letter, the current source implementations are presented for the hybrid implicit–explicit finite-difference time-domain (HIE-FDTD), the improved HIE-FDTD, and the leapfrog HIE-FDTD methods. The asymmetry and the field errors of these HIE-FDTD methods are investigated for all possible values of the time index parameters. The proposed implementations give very low asymmetry and field errors for all the three HIE–FDTD methods. The field errors given by these HIE-FDTD methods are lower than those given by the alternating direction implicit finite-difference time-domain (ADI-FDTD) method.
{"title":"Current Source Implementations for the HIE-FDTD Methods","authors":"Ankit Kumar Pandey, A. K. Saxena","doi":"10.1109/LMWC.2022.3189401","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3189401","url":null,"abstract":"In this letter, the current source implementations are presented for the hybrid implicit–explicit finite-difference time-domain (HIE-FDTD), the improved HIE-FDTD, and the leapfrog HIE-FDTD methods. The asymmetry and the field errors of these HIE-FDTD methods are investigated for all possible values of the time index parameters. The proposed implementations give very low asymmetry and field errors for all the three HIE–FDTD methods. The field errors given by these HIE-FDTD methods are lower than those given by the alternating direction implicit finite-difference time-domain (ADI-FDTD) method.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1379-1382"},"PeriodicalIF":3.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49103353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/LMWC.2022.3193166
E. Arnieri, F. Greco, L. Boccia, G. Amendola
This letter presents a novel vertical waveguide-to-microstrip self-diplexing transition for dual-band applications. The transition is realized with standard printed circuit board (PCB) manufacturing processing, making it suitable for mass production and practical applications. A standard waveguide is screwed on the topside of the stack-up. Dual-band self-diplexing operation is achieved by coupling two microstrips (one for each band) to two radiating patches through H-shaped slots. The operating bandwidth has been enhanced by adding two parasitic patches above the radiating ones. Metalized via holes are used to form a cage around the rectangular waveguide and the microstrips to prevent power leakage. A prototype has been fabricated to operate at K/Ka frequency band. The experimental results show a −10 dB matching bandwidth of 20% and 14% for the lower and upper bands, respectively. Within these ranges, the maximum measured insertion loss is about 0.6 and 0.7 dB, respectively.
{"title":"Vertical Waveguide-to-Microstrip Self-Diplexing Transition for Dual-Band Applications","authors":"E. Arnieri, F. Greco, L. Boccia, G. Amendola","doi":"10.1109/LMWC.2022.3193166","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3193166","url":null,"abstract":"This letter presents a novel vertical waveguide-to-microstrip self-diplexing transition for dual-band applications. The transition is realized with standard printed circuit board (PCB) manufacturing processing, making it suitable for mass production and practical applications. A standard waveguide is screwed on the topside of the stack-up. Dual-band self-diplexing operation is achieved by coupling two microstrips (one for each band) to two radiating patches through H-shaped slots. The operating bandwidth has been enhanced by adding two parasitic patches above the radiating ones. Metalized via holes are used to form a cage around the rectangular waveguide and the microstrips to prevent power leakage. A prototype has been fabricated to operate at K/Ka frequency band. The experimental results show a −10 dB matching bandwidth of 20% and 14% for the lower and upper bands, respectively. Within these ranges, the maximum measured insertion loss is about 0.6 and 0.7 dB, respectively.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1407-1410"},"PeriodicalIF":3.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46805065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/LMWC.2022.3192440
Taehun Kim, Hui-Dong Lee, Bonghyuk Park, Seunghyun Jang, Sunwoo Kong, Changkun Park
This study presents a high-linearity K - band single-pole double-throw (SPDT) switch with asymmetric topology in a 65-nm CMOS process for 5G applications. To simultaneously obtain high power-handling capability and high isolation in the Tx and Rx modes, respectively, we propose an SPDT switch using asymmetric topology and the stacked-transistor technique. In both the Tx/Rx modes, the proposed SPDT switch operates with an insertion loss of less than 2.1 dB and isolation better than 22.5 dB in the frequency range 20–25 GHz. At 22 GHz, the measurement results of the input 1-dB compression point (IP1 dB) are 32.5 and 4.7 dBm in Tx and Rx modes, respectively. The chip core size of the proposed SPDT switch is 0.03 mm2.
{"title":"Design of a K-Band High-Linearity Asymmetric SPDT CMOS Switch Using a Stacked Transistor","authors":"Taehun Kim, Hui-Dong Lee, Bonghyuk Park, Seunghyun Jang, Sunwoo Kong, Changkun Park","doi":"10.1109/LMWC.2022.3192440","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3192440","url":null,"abstract":"This study presents a high-linearity K - band single-pole double-throw (SPDT) switch with asymmetric topology in a 65-nm CMOS process for 5G applications. To simultaneously obtain high power-handling capability and high isolation in the Tx and Rx modes, respectively, we propose an SPDT switch using asymmetric topology and the stacked-transistor technique. In both the Tx/Rx modes, the proposed SPDT switch operates with an insertion loss of less than 2.1 dB and isolation better than 22.5 dB in the frequency range 20–25 GHz. At 22 GHz, the measurement results of the input 1-dB compression point (IP1 dB) are 32.5 and 4.7 dBm in Tx and Rx modes, respectively. The chip core size of the proposed SPDT switch is 0.03 mm2.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1443-1446"},"PeriodicalIF":3.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48746564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/LMWC.2022.3192488
Eren Vardarli, P. Sakalas, M. Schröter
The theory, design, and implementation of a millimeter-wave (mm-wave) two-stage common-emitter (CE) low noise amplifier (LNA) using a 130-nm silicon-germanium (SiGe):C Bipolar CMOS technology is presented. The LNA was optimized for wideband performance from 62 to 110 GHz for both mm-wave radar/sensing and wireless communication applications. A two-stage broadband noise and impedance matching technique is used to obtain a relativity flat gain (13.5 dB) and noise figure (NF) (4.5 dB) across the E-/W-band. Low-voltage $(V_{text {CC}}=0.7,,text {V})$ and low-power (5.9 mW) operation is achieved by forward biasing the base–collector junction, while the wideband capability is further improved by a T-type input matching network utilizing constant quality factor curves. To the best of authors’ knowledge, the presented LNA has the widest 3-dB bandwidth with the lowest power consumption in the literature for silicon-based E-/W-band LNAs.
{"title":"A 5.9 mW E-/W-Band SiGe-HBT LNA With 48 GHz 3-dB Bandwidth and 4.5-dB Noise Figure","authors":"Eren Vardarli, P. Sakalas, M. Schröter","doi":"10.1109/LMWC.2022.3192488","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3192488","url":null,"abstract":"The theory, design, and implementation of a millimeter-wave (mm-wave) two-stage common-emitter (CE) low noise amplifier (LNA) using a 130-nm silicon-germanium (SiGe):C Bipolar CMOS technology is presented. The LNA was optimized for wideband performance from 62 to 110 GHz for both mm-wave radar/sensing and wireless communication applications. A two-stage broadband noise and impedance matching technique is used to obtain a relativity flat gain (13.5 dB) and noise figure (NF) (4.5 dB) across the E-/W-band. Low-voltage $(V_{text {CC}}=0.7,,text {V})$ and low-power (5.9 mW) operation is achieved by forward biasing the base–collector junction, while the wideband capability is further improved by a T-type input matching network utilizing constant quality factor curves. To the best of authors’ knowledge, the presented LNA has the widest 3-dB bandwidth with the lowest power consumption in the literature for silicon-based E-/W-band LNAs.","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1451-1454"},"PeriodicalIF":3.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42649909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/LMWC.2022.3186805
Hang Zhou, J. Perez-Cisneros, Björn Langborn, T. Eriksson, C. Fager
This letter presents a power amplifier (PA) design and network synthesis approach to achieve wideband and efficient performance with a very compact circuit size. A design method is presented in detail to convert a canonical filter-based high-order matching network to the proposed matching configuration with transistor parasitic and packaged elements absorption, and a compact passive network footprint. As a proof of concept, a prototype GaN HEMT PA is implemented. Starting from a fourth-order output network filter, the inductances and capacitance of the filter elements are re-organized to model, and thus absorb the output parasitics of the transistor, leading to a compact footprint with only four transmission lines. The measured results show that the prototype PA achieves an output power of 41.9–44.3 dBm and a 55%–74% drain efficiency, over a record-high decade bandwidth (0.35–3.55 GHz).
{"title":"Design of a Compact GaN Power Amplifier With High Efficiency and Beyond Decade Bandwidth","authors":"Hang Zhou, J. Perez-Cisneros, Björn Langborn, T. Eriksson, C. Fager","doi":"10.1109/LMWC.2022.3186805","DOIUrl":"https://doi.org/10.1109/LMWC.2022.3186805","url":null,"abstract":"This letter presents a power amplifier (PA) design and network synthesis approach to achieve wideband and efficient performance with a very compact circuit size. A design method is presented in detail to convert a canonical filter-based high-order matching network to the proposed matching configuration with transistor parasitic and packaged elements absorption, and a compact passive network footprint. As a proof of concept, a prototype GaN HEMT PA is implemented. Starting from a fourth-order output network filter, the inductances and capacitance of the filter elements are re-organized to model, and thus absorb the output parasitics of the transistor, leading to a compact footprint with only four transmission lines. The measured results show that the prototype PA achieves an output power of 41.9–44.3 dBm and a 55%–74% drain efficiency, over a record-high decade bandwidth (0.35–3.55 GHz).","PeriodicalId":13130,"journal":{"name":"IEEE Microwave and Wireless Components Letters","volume":"32 1","pages":"1439-1442"},"PeriodicalIF":3.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45429581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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